source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd@ 10078

Last change on this file since 10078 was 10078, checked in by neise, 12 years ago
possible to choose, which socket is used for data transmission. only socket 0 for every event or sockets 1..7
File size: 31.0 KB
Line 
1----------------------------------------------------------------------------------
2-- Company:
3-- Engineer:
4--
5-- Create Date: 11:48:48 11/10/2009
6-- Design Name:
7-- Module Name: w5300_modul - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description:
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22use IEEE.STD_LOGIC_ARITH.ALL;
23use IEEE.STD_LOGIC_UNSIGNED.ALL;
24library FACT_FAD_lib;
25use FACT_FAD_lib.fad_definitions.ALL;
26
27---- Uncomment the following library declaration if instantiating
28---- any Xilinx primitives in this code.
29--library UNISIM;
30--use UNISIM.VComponents.all;
31
32ENTITY w5300_modul IS
33 generic(
34 RAM_ADDR_WIDTH : integer := 14
35 );
36 PORT(
37 clk : IN std_logic;
38 wiz_reset : OUT std_logic := '1';
39 addr : OUT std_logic_vector (9 DOWNTO 0);
40 data : INOUT std_logic_vector (15 DOWNTO 0);
41 cs : OUT std_logic := '1';
42 wr : OUT std_logic := '1';
43 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
44 rd : OUT std_logic := '1';
45 int : IN std_logic;
46 write_length : IN std_logic_vector (16 DOWNTO 0);
47 ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
48 ram_data : IN std_logic_vector (15 DOWNTO 0);
49 ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
50 data_valid : IN std_logic;
51 data_valid_ack : OUT std_logic := '0';
52 busy : OUT std_logic := '1';
53 write_header_flag, write_end_flag : IN std_logic;
54 fifo_channels : IN std_logic_vector (3 downto 0);
55 s_trigger : OUT std_logic := '0';
56 new_config : OUT std_logic := '0';
57 config_started : in std_logic;
58 config_addr : out std_logic_vector (7 downto 0);
59 config_data : inout std_logic_vector (15 downto 0) := (others => 'Z');
60 config_wr_en : out std_logic := '0';
61 config_rd_en : out std_logic := '0';
62 -- --
63 config_rw_ack, config_rw_ready : in std_logic;
64 -- --
65 config_busy : in std_logic;
66
67
68
69 denable : out std_logic := '0'; -- default domino wave off
70 dwrite_enable : out std_logic := '0'; -- default DWRITE low.
71 sclk_enable : out std_logic := '1'; -- default DWRITE HIGH.
72 ps_direction : out std_logic := '1'; -- default phase shift upwards
73 ps_do_phase_shift : out std_logic := '0'; --pulse this to phase shift once
74 ps_reset : out std_logic := '0'; -- pulse this to reset the variable phase shift
75
76 srclk_enable : out std_logic := '1'; -- default SRCLK on.
77
78 socks_waiting : out std_logic;
79 socks_connected: out std_logic
80 );
81
82-- Declarations
83
84END w5300_modul ;
85
86architecture Behavioral of w5300_modul is
87
88type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA,
89 INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY,
90 SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, READ_DATA);
91type state_write_type is (WR_START, WR_LENGTH, WR_WAIT1, WR_01, WR_02, WR_03, WR_04, WR_05, WR_05a, WR_05b, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2,
92 WR_ENDFLAG, WR_ENDFLAG1, WR_ENDFLAG2, WR_ENDFLAG3);
93type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04);
94type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06);
95type state_read_data_type is (RD_1, RD_2, RD_3, RD_4, RD_5, RD_6, RD_WAIT, RD_WAIT1, RD_END);
96
97signal RST_TIME : std_logic_vector(19 downto 0) := X"7A120";
98
99signal par_addr : std_logic_vector (9 downto 0) := (OTHERS => '0');
100signal par_data : std_logic_vector (15 downto 0) := (OTHERS => '0');
101signal data_read : std_logic_vector (15 downto 0) := (OTHERS => '0');
102signal adc_data_addr : std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
103
104signal state_init, next_state , next_state_tmp : state_init_type := RESET;
105signal count : std_logic_vector (2 downto 0) := "000";
106signal state_write : state_write_type := WR_START;
107signal state_interrupt_1 : state_interrupt_1_type := IR1_01;
108signal state_interrupt_2 : state_interrupt_2_type := IR2_01;
109signal state_read_data : state_read_data_type := RD_1;
110
111signal interrupt_ignore : std_logic := '1';
112signal int_flag : std_logic := '0';
113signal ram_access : std_logic := '0';
114
115signal zaehler : std_logic_vector (19 downto 0) := (OTHERS => '0');
116signal data_cnt : integer := 0;
117signal drs_cnt : integer :=0;
118signal channel_cnt : integer range 0 to 9 :=0;
119signal socket_cnt : std_logic_vector (2 downto 0) := "000";
120signal roi_max : std_logic_vector (10 downto 0);
121signal data_end : integer := 0;
122
123signal socket_tx_free : std_logic_vector (31 downto 0) := (others => '0');
124signal write_length_bytes : std_logic_vector (16 downto 0);
125
126signal socket_rx_received : std_logic_vector (31 downto 0) := (others => '0');
127signal chk_recv_cntr : integer range 0 to 10000 := 0;
128
129-- --
130signal wait_cntr : integer range 0 to 10000 := 0;
131-- --
132
133signal rx_packets_cnt : std_logic_vector (15 downto 0);
134signal next_packet_data : std_logic := '0';
135signal new_config_flag : std_logic := '0';
136
137signal trigger_stop : std_logic := '1';
138
139signal local_write_length : std_logic_vector (16 DOWNTO 0);
140signal local_ram_start_addr : std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
141signal local_ram_addr : std_logic_vector (RAM_ADDR_WIDTH-1 downto 0);
142signal local_socket_nr : std_logic_vector (2 DOWNTO 0);
143signal local_write_header_flag, local_write_end_flag : std_logic;
144signal local_fifo_channels : std_logic_vector (3 downto 0);
145
146signal data_valid_int : std_logic := '0';
147
148-- only for debugging
149--signal error_cnt : std_logic_vector (7 downto 0) := (others => '0');
150--signal last_trigger_id : std_logic_vector (15 downto 0) := (others => '0');
151
152
153-- signals for different socket modes: DN 04.01.11
154signal socket_nr_counter : integer range 1 to 7 :=1; --used to determine which socket is used for data sending
155signal socket_send_mode : std_logic := '0'; -- if 0 data is send via socket 0; if 1 data is send via the other sockets.
156
157begin
158
159 --synthesis translate_off
160 RST_TIME <= X"00120";
161 --synthesis translate_on
162
163
164 w5300_init_proc : process (clk, int)
165 begin
166
167 if rising_edge (clk) then
168
169 -- Interrupt low
170 if (int = '0') and (interrupt_ignore = '0') then
171 case state_interrupt_1 is
172 when IR1_01 =>
173 int_flag <= '1';
174 busy <= '1';
175 state_interrupt_1 <= IR1_02;
176 when IR1_02 =>
177 state_interrupt_1 <= IR1_03;
178 when IR1_03 =>
179 state_init <= INTERRUPT;
180 socket_cnt <= "000";
181 ram_access <= '0';
182 zaehler <= X"00000";
183 count <= "000";
184 int_flag <= '0';
185 interrupt_ignore <= '1';
186 state_interrupt_1 <= IR1_04;
187 when others =>
188 null;
189 end case;
190 end if; -- int = '0'
191
192 if int_flag = '0' then
193 case state_init is
194 -- Interrupt
195 when INTERRUPT =>
196 case state_interrupt_2 is
197 when IR2_01 =>
198 par_addr <= W5300_IR;
199 state_init <= READ_REG;
200 next_state <= INTERRUPT;
201 state_interrupt_2 <= IR2_02;
202 when IR2_02 =>
203 if (data_read (conv_integer(socket_cnt)) = '1') then -- Sx Interrupt
204 state_interrupt_2 <= IR2_03;
205 else
206 socket_cnt <= socket_cnt + 1;
207 if (socket_cnt = 7) then
208 state_interrupt_2 <= IR2_06;
209 else
210 state_interrupt_2 <= IR2_02;
211 end if;
212 end if;
213 when IR2_03 =>
214 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; -- Sx Interrupt Register
215 state_init <= READ_REG;
216 next_state <= INTERRUPT;
217 state_interrupt_2 <= IR2_04;
218 when IR2_04 =>
219 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC;
220 par_data <= data_read; -- clear Interrupts
221 state_init <= WRITE_REG;
222 next_state <= INTERRUPT;
223 state_interrupt_2 <= IR2_05;
224 when IR2_05 =>
225 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
226 par_data <= X"0010"; -- CLOSE
227 state_init <= WRITE_REG;
228 next_state <= INTERRUPT;
229 socket_cnt <= socket_cnt + 1;
230 if (socket_cnt = 7) then
231 state_interrupt_2 <= IR2_06;
232 else
233 state_interrupt_2 <= IR2_01;
234 end if;
235
236 when IR2_06 =>
237 state_interrupt_1 <= IR1_01;
238 state_interrupt_2 <= IR2_01;
239 socket_cnt <= "000";
240 state_init <= RESET;
241 end case;
242
243 -- reset W5300
244 when RESET =>
245 socket_send_mode <= '0';
246 busy <= '1';
247 zaehler <= zaehler + 1;
248 socks_waiting <= '0';
249 socks_connected <= '0';
250 wiz_reset <= '0';
251-- led <= X"FF";
252 if (zaehler >= X"00064") then -- wait 2µs
253 wiz_reset <= '1';
254 end if;
255 if (zaehler = RST_TIME) then -- wait 10ms
256 zaehler <= X"00000";
257 socket_cnt <= "000";
258 count <= "000";
259 ram_access <= '0';
260 interrupt_ignore <= '0';
261 rd <= '1';
262 wr <= '1';
263 cs <= '1';
264 state_write <= WR_START;
265 state_init <= INIT;
266 end if;
267
268 -- Init
269 when INIT =>
270 par_addr <= W5300_MR;
271 par_data <= X"0000";
272 state_init <= WRITE_REG;
273 next_state <= IM;
274
275 -- Interrupt Mask
276 when IM =>
277 par_addr <= W5300_IMR;
278 par_data <= X"00FF"; -- S0-S7 Interrupts
279 state_init <= WRITE_REG;
280 next_state <= MT;
281
282 -- Memory Type
283 when MT =>
284 par_addr <= W5300_MTYPER;
285 par_data <= X"7FFF"; -- 8K RX, 120K TX-Buffer
286 state_init <= WRITE_REG;
287 next_state <= STX;
288
289 -- Socket TX Memory Size
290 when STX =>
291 par_data <= X"0F0F"; -- 15K TX
292
293 par_addr <= W5300_TMS01R;
294 state_init <=WRITE_REG;
295 next_state <= STX1;
296 when STX1 =>
297 par_addr <= W5300_TMS23R;
298 state_init <=WRITE_REG;
299 next_state <= STX2;
300 when STX2 =>
301 par_addr <= W5300_TMS45R;
302 state_init <=WRITE_REG;
303 next_state <= STX3;
304 when STX3 =>
305 par_addr <= W5300_TMS67R;
306 state_init <=WRITE_REG;
307 next_state <= SRX;
308
309 -- Socket RX Memory Size
310 when SRX =>
311 par_data <= X"0101"; -- 1K RX
312
313 par_addr <= W5300_RMS01R;
314 state_init <=WRITE_REG;
315 next_state <= SRX1;
316 when SRX1 =>
317 par_addr <= W5300_RMS23R;
318 state_init <=WRITE_REG;
319 next_state <= SRX2;
320 when SRX2 =>
321 par_addr <= W5300_RMS45R;
322 state_init <=WRITE_REG;
323 next_state <= SRX3;
324 when SRX3 =>
325 par_addr <= W5300_RMS67R;
326 state_init <=WRITE_REG;
327 next_state <= MAC;
328
329 -- MAC
330 when MAC =>
331 par_addr <= W5300_SHAR;
332 par_data <= MAC_ADDRESS (0);
333 state_init <= WRITE_REG;
334 next_state <= MAC1;
335 when MAC1 =>
336 par_addr <= W5300_SHAR + 2;
337 par_data <= MAC_ADDRESS (1);
338 state_init <= WRITE_REG;
339 next_state <= MAC2;
340 when MAC2 =>
341 par_addr <= W5300_SHAR + 4;
342 par_data <= MAC_ADDRESS (2);
343 state_init <= WRITE_REG;
344 next_state <= GW;
345
346 -- Gateway
347 when GW =>
348 par_addr <= W5300_GAR;
349 par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (0),8);
350 par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (1),8);
351 state_init <= WRITE_REG;
352 next_state <= GW1;
353 when GW1 =>
354 par_addr <= W5300_GAR + 2;
355 par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (2),8);
356 par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (3),8);
357 state_init <= WRITE_REG;
358 next_state <= SNM;
359
360 -- Subnet Mask
361 when SNM =>
362 par_addr <= W5300_SUBR;
363 par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (0),8);
364 par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (1),8);
365 state_init <= WRITE_REG;
366 next_state <= SNM1;
367 when SNM1 =>
368 par_addr <= W5300_SUBR + 2;
369 par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (2),8);
370 par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (3),8);
371 state_init <= WRITE_REG;
372 next_state <= IP;
373 -- Own IP-Address
374 when IP =>
375 par_addr <= W5300_SIPR;
376 par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (0),8);
377 par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (1),8);
378 state_init <= WRITE_REG;
379 next_state <= IP1;
380 when IP1 =>
381 par_addr <= W5300_SIPR + 2;
382 par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (2),8);
383 par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (3),8);
384 state_init <= WRITE_REG;
385 next_state <= SI;
386-- when TIMEOUT =>
387-- par_addr <= W5300_RTR;
388-- par_data <= X"07D0"; -- 0x07D0 = 200ms
389-- state_init <= WRITE_REG;
390-- next_state <= RETRY;
391-- when RETRY =>
392-- par_addr <= W5300_RCR;
393-- par_data <= X"0008";
394-- state_init <= WRITE_REG;
395-- next_state <= SI;
396--
397
398 -- Socket Init
399 when SI =>
400 par_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC;
401 par_data <= X"0101"; -- ALIGN, TCP
402 state_init <= WRITE_REG;
403 next_state <= SI1;
404 -- Sx Interrupt Mask
405 when SI1 =>
406 par_addr <= W5300_S0_IMR + socket_cnt * W5300_S_INC;
407 par_data <= X"000A"; -- TIMEOUT, DISCON
408 state_init <= WRITE_REG;
409 next_state <= SI2;
410 when SI2 =>
411 par_addr <= W5300_S0_PORTR + socket_cnt * W5300_S_INC;
412 par_data <= conv_std_logic_vector(FIRST_PORT + unsigned (socket_cnt), 16);
413 state_init <= WRITE_REG;
414 next_state <= SI3;
415 when SI3 =>
416 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
417 par_data <= X"0001"; -- OPEN
418 state_init <= WRITE_REG;
419 next_state <= SI4;
420 when SI4 =>
421 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
422 state_init <= READ_REG;
423 next_state <= SI5;
424 when SI5 =>
425 if (data_read (7 downto 0) = X"13") then -- is open?
426 state_init <= SI6;
427 else
428 state_init <= SI4;
429 end if;
430 when SI6 =>
431 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
432 par_data <= X"0002"; -- LISTEN
433 state_init <= WRITE_REG;
434 socket_cnt <= socket_cnt + 1;
435 if (socket_cnt = 7) then
436 socket_cnt <= "000";
437 next_state <= ESTABLISH; -- All Sockets open
438 else
439 next_state <= SI; -- Next Socket
440 end if;
441 -- End Socket Init
442
443 when ESTABLISH =>
444 socks_waiting <= '1';
445 socks_connected <= '0';
446 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
447 state_init <= READ_REG;
448 next_state <= EST1;
449 when EST1 =>
450-- led <= data_read (7 downto 0);
451-- led <= X"00";
452 case data_read (7 downto 0) is
453 when X"17" => -- established
454 if (socket_cnt = 7) then
455 socket_cnt <= "000";
456 busy <= '0';
457 state_init <= MAIN;
458 else
459 socket_cnt <= socket_cnt + 1;
460 state_init <= ESTABLISH;
461 end if;
462 when others =>
463 state_init <= ESTABLISH;
464 end case;
465
466 when CONFIG =>
467-- led <= X"F0";
468 new_config <= '1';
469 if (config_started = '1') then
470-- led <= X"0F";
471 new_config <= '0';
472 state_init <= MAIN;
473 end if;
474
475 -- main "loop"
476 when MAIN =>
477 socks_waiting <= '0';
478 socks_connected <= '1';
479
480 ps_do_phase_shift <= '0';
481 ps_reset <= '0';
482 if (trigger_stop = '1') then
483 s_trigger <= '0';
484 end if;
485 data_valid_ack <= '0';
486 state_init <= MAIN1;
487 data_valid_int <= data_valid;
488 when MAIN1 =>
489 if (chk_recv_cntr = 1000) then
490 chk_recv_cntr <= 0;
491 state_read_data <= RD_1;
492 state_init <= READ_DATA;
493 busy <= '1';
494 else
495 chk_recv_cntr <= chk_recv_cntr + 1;
496 state_init <= MAIN2;
497 end if;
498 when MAIN2 =>
499 busy <= '0';
500 if (data_valid = '1') then
501 data_valid_int <= '0';
502 busy <= '1';
503 local_write_length <= write_length;
504 local_ram_start_addr <= ram_start_addr;
505 local_ram_addr <= (others => '0');
506 local_write_header_flag <= write_header_flag;
507 local_write_end_flag <= write_end_flag;
508 local_fifo_channels <= fifo_channels;
509-- data_valid_ack <= '1';
510-- next_state <= MAIN;
511-- state_init <= WRITE_DATA;
512 state_init <= MAIN3;
513 else
514 state_init <= MAIN1;
515 end if;
516 when MAIN3 =>
517-- led <= local_ram_start_addr (7 downto 0);
518 data_valid_ack <= '1';
519 next_state <= MAIN;
520 state_init <= WRITE_DATA;
521
522
523 -- read data from socket 0
524 when READ_DATA =>
525 case state_read_data is
526 when RD_1 =>
527 par_addr <= W5300_S0_RX_RSR;
528 state_init <= READ_REG;
529 next_state <= READ_DATA;
530 state_read_data <= RD_2;
531 when RD_2 =>
532 socket_rx_received (31 downto 16) <= data_read;
533 par_addr <= W5300_S0_RX_RSR + X"2";
534 state_init <= READ_REG;
535 next_state <= READ_DATA;
536 state_read_data <= RD_3;
537 when RD_3 =>
538 socket_rx_received (15 downto 0) <= data_read;
539 state_read_data <= RD_4;
540 when RD_4 =>
541 if (socket_rx_received (16 downto 0) > ('0' & X"000")) then
542 rx_packets_cnt <= socket_rx_received (16 downto 1); -- socket_rx_received / 2
543 state_read_data <= RD_5;
544 else
545 busy <= '0';
546 state_init <= MAIN;
547 end if;
548 when RD_5 =>
549 if (rx_packets_cnt > 0) then
550 rx_packets_cnt <= rx_packets_cnt - '1';
551 par_addr <= W5300_S0_RX_FIFOR;
552 state_init <= READ_REG;
553 next_state <= READ_DATA;
554 state_read_data <= RD_6;
555 else
556 state_read_data <= RD_END;
557 end if;
558 when RD_6 =>
559-- led <= data_read (15 downto 8);
560 -- read command
561 if (next_packet_data = '0') then
562 case data_read (15 downto 8) is
563
564 when CMD_START => -- all data will be send via socket 1..7
565 socket_send_mode <= '1';
566 state_read_data <= RD_5;
567 when CMD_STOP => -- all data will be send via socket 0
568 socket_send_mode <= '0';
569 state_read_data <= RD_5;
570
571
572 when CMD_TRIGGER =>
573 trigger_stop <= '1';
574 s_trigger <= '1';
575 state_read_data <= RD_5;
576 when CMD_DWRITE_RUN =>
577 dwrite_enable <= '1';
578 state_read_data <= RD_5;
579 when CMD_DWRITE_STOP =>
580 dwrite_enable <= '0';
581 state_read_data <= RD_5;
582 when CMD_SCLK_ON =>
583 sclk_enable <= '1';
584 state_read_data <= RD_5;
585 when CMD_SCLK_OFF =>
586 sclk_enable <= '0';
587 state_read_data <= RD_5;
588 when CMD_DENABLE =>
589 denable <= '1';
590 state_read_data <= RD_5;
591 when CMD_DDISABLE =>
592 denable <= '0';
593 state_read_data <= RD_5;
594 when CMD_TRIGGER_C =>
595 trigger_stop <= '0';
596 s_trigger <= '1';
597 state_read_data <= RD_5;
598 when CMD_TRIGGER_S =>
599 trigger_stop <= '1';
600 state_read_data <= RD_5;
601 -- phase shift commands here:
602 when CMD_PS_DO =>
603 ps_do_phase_shift <= '1';
604 state_read_data <= RD_5;
605 when CMD_PS_DIRINC =>
606 ps_direction <= '1';
607 state_read_data <= RD_5;
608 when CMD_PS_RESET =>
609 ps_reset <= '1';
610 state_read_data <= RD_5;
611 when CMD_SRCLK_ON =>
612 srclk_enable <= '1';
613 state_read_data <= RD_5;
614 when CMD_SRCLK_OFF =>
615 srclk_enable <= '0';
616 state_read_data <= RD_5;
617 when CMD_PS_DIRDEC =>
618 ps_direction <= '0';
619 state_read_data <= RD_5;
620 when CMD_WRITE =>
621 next_packet_data <= '1';
622 config_addr <= data_read (7 downto 0);
623 state_read_data <= RD_5;
624 when others =>
625 state_read_data <= RD_5;
626 end case;
627 -- read data
628 else
629 if (config_busy = '0') then
630 config_data <= data_read;
631 config_wr_en <= '1';
632 new_config_flag <= '1';
633 next_packet_data <= '0';
634 state_read_data <= RD_WAIT;
635 end if;
636 end if;
637 when RD_WAIT =>
638 if (config_rw_ack = '1') then
639 state_read_data <= RD_WAIT1;
640 end if;
641 when RD_WAIT1 =>
642 if (config_rw_ready = '1') then
643 config_data <= (others => 'Z');
644 config_wr_en <= '0';
645 state_read_data <= RD_5;
646 end if;
647 when RD_END =>
648 par_addr <= W5300_S0_CR;
649 par_data <= X"0040"; -- RECV
650 state_init <= WRITE_REG;
651 if (new_config_flag = '1') then
652 new_config_flag <= '0';
653 next_state <= CONFIG;
654 else
655 next_state <= MAIN;
656 end if;
657
658 end case; -- state_data_read
659
660
661
662 when WRITE_DATA =>
663 case state_write is
664 when WR_START =>
665 if (local_write_header_flag = '1') then
666 ram_addr <= local_ram_start_addr + 5; -- Address of Trigger-ID (15 downto 0) ????
667 end if;
668 state_write <= WR_WAIT1;
669 when WR_WAIT1 =>
670 state_write <= WR_LENGTH;
671 when WR_LENGTH =>
672 if (local_write_header_flag = '1') then
673 if (socket_send_mode = '1') then -- send via all sockets
674 local_socket_nr <= conv_std_logic_vector(socket_nr_counter, 3);
675 if (socket_nr_counter < 7) then
676 socket_nr_counter <= socket_nr_counter + 1;
677 else
678 socket_nr_counter <= 1;
679 end if;
680 else -- only send via socket 0\
681 local_socket_nr <= "000";
682 end if;
683 end if;
684 next_state_tmp <= next_state;
685 write_length_bytes <= local_write_length (15 downto 0) & '0'; -- shift left (*2)
686 data_cnt <= 0;
687 state_write <= WR_01;
688 -- Check FIFO Size
689 when WR_01 =>
690 par_addr <= W5300_S0_TX_FSR + local_socket_nr * W5300_S_INC;
691 state_init <= READ_REG;
692 next_state <= WRITE_DATA;
693 state_write <= WR_02;
694 when WR_02 =>
695 socket_tx_free (31 downto 16) <= data_read;
696 par_addr <= W5300_S0_TX_FSR + (local_socket_nr * W5300_S_INC) + X"2";
697 state_init <= READ_REG;
698 next_state <= WRITE_DATA;
699 state_write <= WR_03;
700 when WR_03 =>
701 socket_tx_free (15 downto 0) <= data_read;
702 state_write <= WR_04;
703 when WR_04 =>
704
705-- led <= socket_tx_free (15 downto 8);
706
707-- if (socket_tx_free (16 downto 0) < write_length_bytes) then
708 if (socket_tx_free (16 downto 0) < W5300_TX_FIFO_SIZE_8B) then
709 state_write <= WR_01;
710 else
711 if (local_write_header_flag = '1') then
712 state_write <= WR_FIFO;
713 else
714 state_write <= WR_ADC;
715 end if;
716 end if;
717
718 -- Fill FIFO
719
720 -- Write Header
721 when WR_FIFO =>
722 ram_addr <= local_ram_start_addr + local_ram_addr;
723 state_write <= WR_FIFO1;
724 when WR_FIFO1 =>
725 data_cnt <= data_cnt + 1;
726 if (data_cnt < PACKAGE_HEADER_LENGTH) then --???
727 local_ram_addr <= local_ram_addr + 1;
728 if (data_cnt = 2 or data_cnt = 5 or data_cnt = 8 ) then -- skip empty words
729 local_ram_addr <= local_ram_addr + 2;
730 end if;
731 if (data_cnt = 9) then -- skip empty words
732 local_ram_addr <= local_ram_addr + 4;
733 end if;
734 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
735 ram_access <= '1';
736 state_init <= WRITE_REG;
737 next_state <= WRITE_DATA;
738 state_write <= WR_FIFO;
739 else
740 state_write <= WR_ADC;
741 end if;
742 -- End Write Header
743
744 -- Write ADC-Data
745 ---- Start...
746 when WR_ADC =>
747 adc_data_addr <= local_ram_start_addr + local_ram_addr;
748 drs_cnt <= 0;
749 channel_cnt <= 1;
750 data_cnt <= 0;
751 roi_max <= (others => '0');
752 data_end <= 3;
753 state_write <= WR_ADC1;
754
755 ---- Write Channel
756 when WR_ADC1 =>
757 -- read ROI and set end of Channel-Data
758 if (data_cnt = 3) then
759 data_end <= conv_integer (ram_data) + 3;
760 if (ram_data > roi_max) then
761 roi_max <= ram_data (10 downto 0);
762 end if;
763 end if;
764 ram_addr <= adc_data_addr + drs_cnt + (data_cnt * 4);
765 state_write <= WR_ADC2;
766 when WR_ADC2 =>
767 if (data_cnt < data_end) then
768 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
769 ram_access <= '1';
770 state_init <= WRITE_REG;
771 next_state <= WRITE_DATA;
772 data_cnt <= data_cnt + 1;
773 state_write <= WR_ADC1;
774 else
775 -- Next DRS
776 if (drs_cnt < 3) then
777 drs_cnt <= drs_cnt + 1;
778 data_cnt <= 0;
779 data_end <= 3;
780 state_write <= WR_ADC1;
781 else
782 -- Next Channel
783 if (channel_cnt < local_fifo_channels) then
784 channel_cnt <= channel_cnt + 1;
785 roi_max <= (others => '0');
786 drs_cnt <= 0;
787 data_cnt <= 0;
788 data_end <= 3;
789 adc_data_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4);
790 state_write <= WR_ADC1;
791 else
792 -- Ready
793 if (local_write_end_flag = '1') then
794 state_write <= WR_ENDFLAG;
795 else
796 state_write <= WR_05;
797 end if;
798 end if;
799 end if;
800 end if;
801 -- End Write ADC-Data
802
803 -- Write End Package Flag
804 when WR_ENDFLAG =>
805 ram_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4);
806 state_write <= WR_ENDFLAG1;
807 when WR_ENDFLAG1 =>
808 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
809 ram_access <= '1';
810 state_init <= WRITE_REG;
811 next_state <= WRITE_DATA;
812 state_write <= WR_ENDFLAG2;
813 when WR_ENDFLAG2 =>
814 ram_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4) + 1;
815 state_write <= WR_ENDFLAG3;
816 when WR_ENDFLAG3 =>
817 state_init <= WRITE_REG;
818 next_state <= WRITE_DATA;
819 state_write <= WR_05a;
820
821 -- End Write End Package Flag
822
823 -- Wait????
824 when WR_05a =>
825 if (wait_cntr < 10) then -- 3000 works???
826 wait_cntr <= wait_cntr + 1;
827 else
828 wait_cntr <= 0;
829 state_write <= WR_05b;
830 end if;
831 when WR_05b =>
832 state_write <= WR_05;
833
834 --Send FIFO
835 when WR_05 =>
836 ram_access <= '0';
837 par_addr <= W5300_S0_TX_WRSR + local_socket_nr * W5300_S_INC;
838 par_data <= (0 => write_length_bytes (16), others => '0');
839 state_init <= WRITE_REG;
840 state_write <= WR_06;
841 when WR_06 =>
842 par_addr <= W5300_S0_TX_WRSR + (local_socket_nr * W5300_S_INC) + X"2";
843 par_data <= write_length_bytes (15 downto 0);
844 state_init <= WRITE_REG;
845 state_write <= WR_07;
846 when WR_07 =>
847 par_addr <= W5300_S0_CR + local_socket_nr * W5300_S_INC;
848 par_data <= X"0020"; -- Send
849 state_init <= WRITE_REG;
850 state_write <= WR_08;
851 when others =>
852 state_init <= next_state_tmp;
853 state_write <= WR_START;
854 end case;
855 -- End WRITE_DATA
856
857 when READ_REG =>
858 case count is
859 when "000" =>
860 cs <= '0';
861 rd <= '0';
862 wr <= '1';
863 data <= (others => 'Z'); -- !!!!!!!!!!
864 count <= "001";
865 addr <= par_addr;
866 when "001" =>
867 count <= "010";
868 when "010" =>
869 count <= "100";
870 when "100" =>
871 data_read <= data;
872 count <= "110";
873 when "110" =>
874 count <= "111";
875 when "111" =>
876 cs <= '1';
877 rd <= '1';
878 count <= "000";
879 state_init <= next_state;
880 when others =>
881 null;
882 end case;
883
884 when WRITE_REG =>
885 case count is
886 when "000" =>
887 cs <= '0';
888 wr <= '0';
889 rd <= '1';
890 addr <= par_addr;
891 if (ram_access = '1') then
892 data <= ram_data;
893 else
894 data <= par_data;
895 end if;
896 count <= "100";
897 when "100" =>
898 count <= "101";
899 when "101" =>
900 count <= "110";
901 when "110" =>
902 cs <= '1';
903 wr <= '1';
904 state_init <= next_state;
905 count <= "000";
906 when others =>
907 null;
908 end case;
909
910 when others =>
911 null;
912 end case;
913 end if; -- int_flag = '0'
914
915 end if; -- rising_edge (clk)
916
917 end process w5300_init_proc;
918
919end Behavioral;
920
Note: See TracBrowser for help on using the repository browser.