source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd@ 10129

Last change on this file since 10129 was 10129, checked in by neise, 11 years ago
checking before change of Event Header structure. added REFCLK counter and ADC CLK PS output. In case of missing REFCLK, DENEABLE should be pulled low. (untested)
File size: 34.7 KB
Line 
1----------------------------------------------------------------------------------
2-- Company:
3-- Engineer:
4--
5-- Create Date: 11:48:48 11/10/2009
6-- Design Name:
7-- Module Name: w5300_modul - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description:
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22use IEEE.STD_LOGIC_ARITH.ALL;
23use IEEE.STD_LOGIC_UNSIGNED.ALL;
24library FACT_FAD_lib;
25use FACT_FAD_lib.fad_definitions.ALL;
26
27---- Uncomment the following library declaration if instantiating
28---- any Xilinx primitives in this code.
29--library UNISIM;
30--use UNISIM.VComponents.all;
31
32ENTITY w5300_modul IS
33 generic(
34 RAM_ADDR_WIDTH : integer := 14
35 );
36 PORT(
37 clk : IN std_logic;
38 wiz_reset : OUT std_logic := '1';
39 addr : OUT std_logic_vector (9 DOWNTO 0);
40 data : INOUT std_logic_vector (15 DOWNTO 0);
41 cs : OUT std_logic := '1';
42 wr : OUT std_logic := '1';
43 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
44 rd : OUT std_logic := '1';
45 int : IN std_logic;
46 write_length : IN std_logic_vector (16 DOWNTO 0);
47 ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
48 ram_data : IN std_logic_vector (15 DOWNTO 0);
49 ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
50 data_valid : IN std_logic;
51 data_valid_ack : OUT std_logic := '0';
52 busy : OUT std_logic := '1';
53 write_header_flag, write_end_flag : IN std_logic;
54 fifo_channels : IN std_logic_vector (3 downto 0);
55 -- softtrigger:
56 s_trigger : OUT std_logic := '0';
57 c_trigger_enable: out std_logic := '0';
58 c_trigger_mult: out std_logic_vector (7 DOWNTO 0) := (OTHERS => '1'); --subject to changes
59 --
60 new_config : OUT std_logic := '0';
61 config_started : in std_logic;
62 config_addr : out std_logic_vector (7 downto 0);
63 config_data : inout std_logic_vector (15 downto 0) := (others => 'Z');
64 config_wr_en : out std_logic := '0';
65 config_rd_en : out std_logic := '0';
66 -- --
67 config_rw_ack, config_rw_ready : in std_logic;
68 -- --
69 config_busy : in std_logic;
70
71 MAC_jumper : in std_logic_vector (1 downto 0);
72 BoardID : in std_logic_vector (3 downto 0);
73 CrateID : in std_logic_vector (1 downto 0);
74
75 denable : out std_logic := '0'; -- default domino wave off
76 dwrite_enable : out std_logic := '0'; -- default DWRITE low.
77 sclk_enable : out std_logic := '1'; -- default DWRITE HIGH.
78 ps_direction : out std_logic := '1'; -- default phase shift upwards
79 ps_do_phase_shift : out std_logic := '0'; --pulse this to phase shift once
80 ps_reset : out std_logic := '0'; -- pulse this to reset the variable phase shift
81
82 srclk_enable : out std_logic := '1'; -- default SRCLK on.
83
84 trigger_enable : out std_logic := '0'; -- default triggers are NOT accepted
85
86 socks_waiting : out std_logic;
87 socks_connected: out std_logic
88 );
89
90-- Declarations
91
92END w5300_modul ;
93
94architecture Behavioral of w5300_modul is
95
96type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA,
97 INIT, LOCATE, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY,
98 SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, READ_DATA);
99type state_write_type is (WR_START, WR_LENGTH, WR_WAIT1, WR_01, WR_02, WR_03, WR_04, WR_05, WR_05a, WR_05b, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2,
100 WR_ENDFLAG, WR_ENDFLAG1, WR_ENDFLAG2, WR_ENDFLAG3);
101type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04);
102type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06);
103type state_read_data_type is (RD_1, RD_2, RD_3, RD_4, RD_5, RD_6, RD_WAIT, RD_WAIT1, RD_END);
104
105signal RST_TIME : std_logic_vector(19 downto 0) := X"7A120";
106
107signal par_addr : std_logic_vector (9 downto 0) := (OTHERS => '0');
108signal par_data : std_logic_vector (15 downto 0) := (OTHERS => '0');
109signal data_read : std_logic_vector (15 downto 0) := (OTHERS => '0');
110signal adc_data_addr : std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
111
112signal state_init, next_state , next_state_tmp : state_init_type := RESET;
113signal count : std_logic_vector (2 downto 0) := "000";
114signal state_write : state_write_type := WR_START;
115signal state_interrupt_1 : state_interrupt_1_type := IR1_01;
116signal state_interrupt_2 : state_interrupt_2_type := IR2_01;
117signal state_read_data : state_read_data_type := RD_1;
118
119signal interrupt_ignore : std_logic := '1';
120signal int_flag : std_logic := '0';
121signal ram_access : std_logic := '0';
122
123signal zaehler : std_logic_vector (19 downto 0) := (OTHERS => '0');
124signal data_cnt : integer := 0;
125signal drs_cnt : integer :=0;
126signal channel_cnt : integer range 0 to 9 :=0;
127signal socket_cnt : std_logic_vector (2 downto 0) := "000";
128signal roi_max : std_logic_vector (10 downto 0);
129signal data_end : integer := 0;
130
131signal socket_tx_free : std_logic_vector (31 downto 0) := (others => '0');
132signal write_length_bytes : std_logic_vector (16 downto 0);
133
134signal socket_rx_received : std_logic_vector (31 downto 0) := (others => '0');
135signal chk_recv_cntr : integer range 0 to 10000 := 0;
136
137-- --
138signal wait_cntr : integer range 0 to 10000 := 0;
139-- --
140
141signal rx_packets_cnt : std_logic_vector (15 downto 0);
142signal next_packet_data : std_logic := '0';
143signal new_config_flag : std_logic := '0';
144
145signal trigger_stop : std_logic := '1';
146
147signal local_write_length : std_logic_vector (16 DOWNTO 0);
148signal local_ram_start_addr : std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
149signal local_ram_addr : std_logic_vector (RAM_ADDR_WIDTH-1 downto 0);
150signal local_socket_nr : std_logic_vector (2 DOWNTO 0);
151signal local_write_header_flag, local_write_end_flag : std_logic;
152signal local_fifo_channels : std_logic_vector (3 downto 0);
153
154signal data_valid_int : std_logic := '0';
155
156signal FAD_in_cam : std_logic := '0';
157signal FAD_at_ETHZ : std_logic := '0';
158signal bid : std_logic_vector (3 downto 0);
159signal cid : std_logic_vector (1 downto 0);
160
161
162-- only for debugging
163--signal error_cnt : std_logic_vector (7 downto 0) := (others => '0');
164--signal last_trigger_id : std_logic_vector (15 downto 0) := (others => '0');
165
166
167-- signals for different socket modes: DN 04.01.11
168signal socket_nr_counter : integer range 1 to 7 :=1; --used to determine which socket is used for data sending
169signal socket_send_mode : std_logic := '0'; -- if 0 data is send via socket 0; if 1 data is send via the other sockets.
170
171signal mac_loc : mac_type;
172signal ip_loc : ip_type;
173signal gateway_loc : ip_type;
174signal netmask_loc : ip_type;
175
176
177begin
178
179 --synthesis translate_off
180 RST_TIME <= X"00120";
181 --synthesis translate_on
182
183
184 w5300_init_proc : process (clk, int)
185 begin
186
187 if rising_edge (clk) then
188
189 -- Interrupt low
190 if (int = '0') and (interrupt_ignore = '0') then
191 case state_interrupt_1 is
192 when IR1_01 =>
193 int_flag <= '1';
194 busy <= '1';
195 state_interrupt_1 <= IR1_02;
196 when IR1_02 =>
197 state_interrupt_1 <= IR1_03;
198 when IR1_03 =>
199 state_init <= INTERRUPT;
200 socket_cnt <= "000";
201 ram_access <= '0';
202 zaehler <= X"00000";
203 count <= "000";
204 int_flag <= '0';
205 interrupt_ignore <= '1';
206 state_interrupt_1 <= IR1_04;
207 when others =>
208 null;
209 end case;
210 end if; -- int = '0'
211
212 if int_flag = '0' then
213 case state_init is
214 -- Interrupt
215 when INTERRUPT =>
216 case state_interrupt_2 is
217 when IR2_01 =>
218 par_addr <= W5300_IR;
219 state_init <= READ_REG;
220 next_state <= INTERRUPT;
221 state_interrupt_2 <= IR2_02;
222 when IR2_02 =>
223 if (data_read (conv_integer(socket_cnt)) = '1') then -- Sx Interrupt
224 state_interrupt_2 <= IR2_03;
225 else
226 socket_cnt <= socket_cnt + 1;
227 if (socket_cnt = 7) then
228 state_interrupt_2 <= IR2_06;
229 else
230 state_interrupt_2 <= IR2_02;
231 end if;
232 end if;
233 when IR2_03 =>
234 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; -- Sx Interrupt Register
235 state_init <= READ_REG;
236 next_state <= INTERRUPT;
237 state_interrupt_2 <= IR2_04;
238 when IR2_04 =>
239 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC;
240 par_data <= data_read; -- clear Interrupts
241 state_init <= WRITE_REG;
242 next_state <= INTERRUPT;
243 state_interrupt_2 <= IR2_05;
244 when IR2_05 =>
245 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
246 par_data <= X"0010"; -- CLOSE
247 state_init <= WRITE_REG;
248 next_state <= INTERRUPT;
249 socket_cnt <= socket_cnt + 1;
250 if (socket_cnt = 7) then
251 state_interrupt_2 <= IR2_06;
252 else
253 state_interrupt_2 <= IR2_01;
254 end if;
255
256 when IR2_06 =>
257 state_interrupt_1 <= IR1_01;
258 state_interrupt_2 <= IR2_01;
259 socket_cnt <= "000";
260 state_init <= RESET;
261 end case;
262
263 -- reset W5300
264 when RESET =>
265 socket_send_mode <= '0';
266 busy <= '1';
267 zaehler <= zaehler + 1;
268 socks_waiting <= '0';
269 socks_connected <= '0';
270 wiz_reset <= '0';
271-- led <= X"FF";
272 if (zaehler >= X"00064") then -- wait 2µs
273 wiz_reset <= '1';
274 end if;
275 if (zaehler = RST_TIME) then -- wait 10ms
276 zaehler <= X"00000";
277 socket_cnt <= "000";
278 count <= "000";
279 ram_access <= '0';
280 interrupt_ignore <= '0';
281 rd <= '1';
282 wr <= '1';
283 cs <= '1';
284 state_write <= WR_START;
285 state_init <= INIT;
286 end if;
287
288 -- Init
289 when INIT =>
290 -- status of MAC jumpers is synched in
291 -- and Board- and CrateID are synched in
292 FAD_in_cam <= MAC_jumper(1); -- see position of jumpers in FACT logbook
293 FAD_at_ETHZ <= MAC_jumper(0); -- MAC_jumper(1) is where D_T(7) was; MAC_jumper(0) is where D_T(6) was;
294 bid <= BoardID;
295 cid <= CrateID;
296 --
297 par_addr <= W5300_MR;
298 par_data <= X"0000";
299 state_init <= WRITE_REG;
300 next_state <= LOCATE;
301
302 when LOCATE =>
303 state_init <= IM;
304
305 if (FAD_in_cam = '1') then
306 -- if BID = "1111" and CID="11" then FAD is not really in cam
307 -- back to INIT !! endless loop
308 if (bid = "1111" and cid="11") then
309 -- this should never happen!!!!!
310 -- impossible to find this out, if in cam
311 state_init <= INIT;
312 else -- everything is fine
313 -- IP & MAC are calculated from BID & CID
314 -- code here
315 gateway_loc <= CAM_GATEWAY;
316 netmask_loc <= CAM_NETMASK;
317 mac_loc <= (CAM_MAC_prefix (0), CAM_MAC_prefix (1) , conv_std_logic_vector ( conv_integer(cid)*10+conv_integer(bid) , 16) );
318 ip_loc <= ( CAM_IP_PREFIX(0) , CAM_IP_PREFIX(1) , IP_offset + conv_integer(cid) , IP_offset + conv_integer(bid) );
319 end if;
320 else -- FAD is tested, either at ETHZ or at TUDO AND either with FMP or without.
321 if ( FAD_at_ETHZ = '0' ) then
322 -- easy FAD is at TUDO -> only one choice.
323 mac_loc <= MAC_FAD0;
324 ip_loc <= IP_TUDO;
325 gateway_loc <= TUDO_GATEWAY;
326 netmask_loc <= TUDO_NETMASK;
327 else -- FAD is at ETHZ but not in cam --> IP lookup table is needed.
328 if (bid = "1111" and cid="11") then -- FAD is not in crate
329 mac_loc <= MAC_FAD0;
330 ip_loc <= IP_ETHZ_FAD0;
331 gateway_loc <= ETHZ_GATEWAY;
332 netmask_loc <= ETHZ_NETMASK;
333 else
334 -- FAD is at ETHZ and in crate:
335 -- crate ID is not of importance.
336 -- we only have 3 MACs and IPs so far, so only the first boardIDs are allowed.
337 if ( conv_integer(bid) < MAC_LIST'length) then
338 gateway_loc <= ETHZ_GATEWAY;
339 netmask_loc <= ETHZ_NETMASK;
340 mac_loc <= MAC_LIST(conv_integer(bid));
341 ip_loc <= IP_LIST(conv_integer(bid));
342 end if; -- conv_integer
343 end if; -- bid=1111 & cid=11
344 end if; --FAD_at_ETHZ = 0
345 end if; --FAD_in_cam = 1
346
347 -- Interrupt Mask
348 when IM =>
349 par_addr <= W5300_IMR;
350 par_data <= X"00FF"; -- S0-S7 Interrupts
351 state_init <= WRITE_REG;
352 next_state <= MT;
353
354 -- Memory Type
355 when MT =>
356 par_addr <= W5300_MTYPER;
357 par_data <= X"7FFF"; -- 8K RX, 120K TX-Buffer
358 state_init <= WRITE_REG;
359 next_state <= STX;
360
361 -- Socket TX Memory Size
362 when STX =>
363 par_data <= X"0F0F"; -- 15K TX
364
365 par_addr <= W5300_TMS01R;
366 state_init <=WRITE_REG;
367 next_state <= STX1;
368 when STX1 =>
369 par_addr <= W5300_TMS23R;
370 state_init <=WRITE_REG;
371 next_state <= STX2;
372 when STX2 =>
373 par_addr <= W5300_TMS45R;
374 state_init <=WRITE_REG;
375 next_state <= STX3;
376 when STX3 =>
377 par_addr <= W5300_TMS67R;
378 state_init <=WRITE_REG;
379 next_state <= SRX;
380
381 -- Socket RX Memory Size
382 when SRX =>
383 par_data <= X"0101"; -- 1K RX
384
385 par_addr <= W5300_RMS01R;
386 state_init <=WRITE_REG;
387 next_state <= SRX1;
388 when SRX1 =>
389 par_addr <= W5300_RMS23R;
390 state_init <=WRITE_REG;
391 next_state <= SRX2;
392 when SRX2 =>
393 par_addr <= W5300_RMS45R;
394 state_init <=WRITE_REG;
395 next_state <= SRX3;
396 when SRX3 =>
397 par_addr <= W5300_RMS67R;
398 state_init <=WRITE_REG;
399 next_state <= MAC;
400
401 -- MAC
402 when MAC =>
403 par_addr <= W5300_SHAR;
404 par_data <= mac_loc(0);
405 state_init <= WRITE_REG;
406 next_state <= MAC1;
407 when MAC1 =>
408 par_addr <= W5300_SHAR + 2;
409 par_data <= mac_loc(1);
410 state_init <= WRITE_REG;
411 next_state <= MAC2;
412 when MAC2 =>
413 par_addr <= W5300_SHAR + 4;
414 par_data <= mac_loc(2);
415 state_init <= WRITE_REG;
416 next_state <= GW;
417
418 -- Gateway
419 when GW =>
420 par_addr <= W5300_GAR;
421 par_data (15 downto 8) <= conv_std_logic_vector(gateway_loc(0),8);
422 par_data (7 downto 0) <= conv_std_logic_vector(gateway_loc(1),8);
423 state_init <= WRITE_REG;
424 next_state <= GW1;
425 when GW1 =>
426 par_addr <= W5300_GAR + 2;
427 par_data (15 downto 8) <= conv_std_logic_vector(gateway_loc(2),8);
428 par_data (7 downto 0) <= conv_std_logic_vector(gateway_loc(3),8);
429 state_init <= WRITE_REG;
430 next_state <= SNM;
431
432 -- Subnet Mask
433 when SNM =>
434 par_addr <= W5300_SUBR;
435 par_data (15 downto 8) <= conv_std_logic_vector(netmask_loc(0),8);
436 par_data (7 downto 0) <= conv_std_logic_vector(netmask_loc(1),8);
437 state_init <= WRITE_REG;
438 next_state <= SNM1;
439 when SNM1 =>
440 par_addr <= W5300_SUBR + 2;
441 par_data (15 downto 8) <= conv_std_logic_vector(netmask_loc(2),8);
442 par_data (7 downto 0) <= conv_std_logic_vector(netmask_loc(3),8);
443 state_init <= WRITE_REG;
444 next_state <= IP;
445 -- Own IP-Address
446 when IP =>
447 par_addr <= W5300_SIPR;
448 par_data (15 downto 8) <= conv_std_logic_vector(ip_loc(0),8);
449 par_data (7 downto 0) <= conv_std_logic_vector(ip_loc(1),8);
450 state_init <= WRITE_REG;
451 next_state <= IP1;
452 when IP1 =>
453 par_addr <= W5300_SIPR + 2;
454 par_data (15 downto 8) <= conv_std_logic_vector(ip_loc(2),8);
455 par_data (7 downto 0) <= conv_std_logic_vector(ip_loc(3),8);
456 state_init <= WRITE_REG;
457 next_state <= SI;
458-- when TIMEOUT =>
459-- par_addr <= W5300_RTR;
460-- par_data <= X"07D0"; -- 0x07D0 = 200ms
461-- state_init <= WRITE_REG;
462-- next_state <= RETRY;
463-- when RETRY =>
464-- par_addr <= W5300_RCR;
465-- par_data <= X"0008";
466-- state_init <= WRITE_REG;
467-- next_state <= SI;
468--
469
470 -- Socket Init
471 when SI =>
472 par_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC;
473 par_data <= X"0101"; -- ALIGN, TCP
474 state_init <= WRITE_REG;
475 next_state <= SI1;
476 -- Sx Interrupt Mask
477 when SI1 =>
478 par_addr <= W5300_S0_IMR + socket_cnt * W5300_S_INC;
479 par_data <= X"000A"; -- TIMEOUT, DISCON
480 state_init <= WRITE_REG;
481 next_state <= SI2;
482 when SI2 =>
483 par_addr <= W5300_S0_PORTR + socket_cnt * W5300_S_INC;
484 par_data <= conv_std_logic_vector(FIRST_PORT + unsigned (socket_cnt), 16);
485 state_init <= WRITE_REG;
486 next_state <= SI3;
487 when SI3 =>
488 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
489 par_data <= X"0001"; -- OPEN
490 state_init <= WRITE_REG;
491 next_state <= SI4;
492 when SI4 =>
493 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
494 state_init <= READ_REG;
495 next_state <= SI5;
496 when SI5 =>
497 if (data_read (7 downto 0) = X"13") then -- is open?
498 state_init <= SI6;
499 else
500 state_init <= SI4;
501 end if;
502 when SI6 =>
503 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
504 par_data <= X"0002"; -- LISTEN
505 state_init <= WRITE_REG;
506 socket_cnt <= socket_cnt + 1;
507 if (socket_cnt = 7) then
508 socket_cnt <= "000";
509 next_state <= ESTABLISH; -- All Sockets open
510 else
511 next_state <= SI; -- Next Socket
512 end if;
513 -- End Socket Init
514
515 when ESTABLISH =>
516 socks_waiting <= '1';
517 socks_connected <= '0';
518 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
519 state_init <= READ_REG;
520 next_state <= EST1;
521 when EST1 =>
522-- led <= data_read (7 downto 0);
523-- led <= X"00";
524 case data_read (7 downto 0) is
525 when X"17" => -- established
526 if (socket_cnt = 7) then
527 socket_cnt <= "000";
528 busy <= '0';
529 state_init <= MAIN;
530 else
531 socket_cnt <= socket_cnt + 1;
532 state_init <= ESTABLISH;
533 end if;
534 when others =>
535 state_init <= ESTABLISH;
536 end case;
537
538 when CONFIG =>
539-- led <= X"F0";
540 new_config <= '1';
541 if (config_started = '1') then
542-- led <= X"0F";
543 new_config <= '0';
544 state_init <= MAIN;
545 end if;
546
547 -- main "loop"
548 when MAIN =>
549 socks_waiting <= '0';
550 socks_connected <= '1';
551
552 ps_do_phase_shift <= '0';
553 ps_reset <= '0';
554 if (trigger_stop = '1') then
555 s_trigger <= '0';
556 end if;
557 data_valid_ack <= '0';
558 state_init <= MAIN1;
559 data_valid_int <= data_valid;
560 when MAIN1 =>
561 if (chk_recv_cntr = 1000) then
562 chk_recv_cntr <= 0;
563 state_read_data <= RD_1;
564 state_init <= READ_DATA;
565 busy <= '1';
566 else
567 chk_recv_cntr <= chk_recv_cntr + 1;
568 state_init <= MAIN2;
569 end if;
570 when MAIN2 =>
571 busy <= '0';
572 if (data_valid = '1') then
573 data_valid_int <= '0';
574 busy <= '1';
575 local_write_length <= write_length;
576 local_ram_start_addr <= ram_start_addr;
577 local_ram_addr <= (others => '0');
578 local_write_header_flag <= write_header_flag;
579 local_write_end_flag <= write_end_flag;
580 local_fifo_channels <= fifo_channels;
581-- data_valid_ack <= '1';
582-- next_state <= MAIN;
583-- state_init <= WRITE_DATA;
584 state_init <= MAIN3;
585 else
586 state_init <= MAIN1;
587 end if;
588 when MAIN3 =>
589-- led <= local_ram_start_addr (7 downto 0);
590 data_valid_ack <= '1';
591 next_state <= MAIN;
592 state_init <= WRITE_DATA;
593
594
595 -- read data from socket 0
596 when READ_DATA =>
597 case state_read_data is
598 when RD_1 =>
599 par_addr <= W5300_S0_RX_RSR;
600 state_init <= READ_REG;
601 next_state <= READ_DATA;
602 state_read_data <= RD_2;
603 when RD_2 =>
604 socket_rx_received (31 downto 16) <= data_read;
605 par_addr <= W5300_S0_RX_RSR + X"2";
606 state_init <= READ_REG;
607 next_state <= READ_DATA;
608 state_read_data <= RD_3;
609 when RD_3 =>
610 socket_rx_received (15 downto 0) <= data_read;
611 state_read_data <= RD_4;
612 when RD_4 =>
613 if (socket_rx_received (16 downto 0) > ('0' & X"000")) then
614 rx_packets_cnt <= socket_rx_received (16 downto 1); -- socket_rx_received / 2
615 state_read_data <= RD_5;
616 else
617 busy <= '0';
618 state_init <= MAIN;
619 end if;
620 when RD_5 =>
621 if (rx_packets_cnt > 0) then
622 rx_packets_cnt <= rx_packets_cnt - '1';
623 par_addr <= W5300_S0_RX_FIFOR;
624 state_init <= READ_REG;
625 next_state <= READ_DATA;
626 state_read_data <= RD_6;
627 else
628 state_read_data <= RD_END;
629 end if;
630 when RD_6 =>
631-- led <= data_read (15 downto 8);
632 -- read command
633 if (next_packet_data = '0') then
634 case data_read (15 downto 8) is
635
636 when CMD_START => -- all data will be send via socket 1..7
637 socket_send_mode <= '1';
638 state_read_data <= RD_5;
639 when CMD_STOP => -- all data will be send via socket 0
640 socket_send_mode <= '0';
641 state_read_data <= RD_5;
642
643
644 when CMD_TRIGGER =>
645 trigger_stop <= '1';
646 s_trigger <= '1';
647 state_read_data <= RD_5;
648 when CMD_DWRITE_RUN =>
649 dwrite_enable <= '1';
650 state_read_data <= RD_5;
651 when CMD_DWRITE_STOP =>
652 dwrite_enable <= '0';
653 state_read_data <= RD_5;
654 when CMD_SCLK_ON =>
655 sclk_enable <= '1';
656 state_read_data <= RD_5;
657 when CMD_SCLK_OFF =>
658 sclk_enable <= '0';
659 state_read_data <= RD_5;
660 when CMD_DENABLE =>
661 denable <= '1';
662 state_read_data <= RD_5;
663 when CMD_DDISABLE =>
664 denable <= '0';
665 state_read_data <= RD_5;
666 when CMD_TRIGGER_C =>
667 c_trigger_enable <= '1';
668 --trigger_stop <= '0';
669 --s_trigger <= '1';
670 state_read_data <= RD_5;
671 when CMD_TRIGGER_S =>
672 c_trigger_enable <= '0';
673 --trigger_stop <= '1';
674 state_read_data <= RD_5;
675 when CMD_SET_TRIGGER_MULT =>
676 c_trigger_mult <= data_read (7 downto 0);
677 state_read_data <= RD_5;
678
679 -- phase shift commands here:
680 when CMD_PS_DO =>
681 ps_do_phase_shift <= '1';
682 state_read_data <= RD_5;
683 when CMD_PS_DIRINC =>
684 ps_direction <= '1';
685 state_read_data <= RD_5;
686 when CMD_PS_RESET =>
687 ps_reset <= '1';
688 state_read_data <= RD_5;
689
690 when CMD_SRCLK_ON =>
691 srclk_enable <= '1';
692 state_read_data <= RD_5;
693 when CMD_SRCLK_OFF =>
694 srclk_enable <= '0';
695 state_read_data <= RD_5;
696
697 when CMD_TRIGGERS_ON =>
698 trigger_enable <= '1';
699 state_read_data <= RD_5;
700 when CMD_TRIGGERS_OFF =>
701 trigger_enable <= '0';
702 state_read_data <= RD_5;
703
704
705 when CMD_PS_DIRDEC =>
706 ps_direction <= '0';
707 state_read_data <= RD_5;
708 when CMD_WRITE =>
709 next_packet_data <= '1';
710 config_addr <= data_read (7 downto 0);
711 state_read_data <= RD_5;
712 when others =>
713 state_read_data <= RD_5;
714 end case;
715 -- read data
716 else
717 if (config_busy = '0') then
718 config_data <= data_read;
719 config_wr_en <= '1';
720 new_config_flag <= '1';
721 next_packet_data <= '0';
722 state_read_data <= RD_WAIT;
723 end if;
724 end if;
725 when RD_WAIT =>
726 if (config_rw_ack = '1') then
727 state_read_data <= RD_WAIT1;
728 end if;
729 when RD_WAIT1 =>
730 if (config_rw_ready = '1') then
731 config_data <= (others => 'Z');
732 config_wr_en <= '0';
733 state_read_data <= RD_5;
734 end if;
735 when RD_END =>
736 par_addr <= W5300_S0_CR;
737 par_data <= X"0040"; -- RECV
738 state_init <= WRITE_REG;
739 if (new_config_flag = '1') then
740 new_config_flag <= '0';
741 next_state <= CONFIG;
742 else
743 next_state <= MAIN;
744 end if;
745
746 end case; -- state_data_read
747
748
749
750 when WRITE_DATA =>
751 case state_write is
752 when WR_START =>
753 if (local_write_header_flag = '1') then
754 ram_addr <= local_ram_start_addr + 5; -- Address of Trigger-ID (15 downto 0) ????
755 end if;
756 state_write <= WR_WAIT1;
757 when WR_WAIT1 =>
758 state_write <= WR_LENGTH;
759 when WR_LENGTH =>
760 if (local_write_header_flag = '1') then
761 if (socket_send_mode = '1') then -- send via all sockets
762 local_socket_nr <= conv_std_logic_vector(socket_nr_counter, 3);
763 if (socket_nr_counter < 7) then
764 socket_nr_counter <= socket_nr_counter + 1;
765 else
766 socket_nr_counter <= 1;
767 end if;
768 else -- only send via socket 0\
769 local_socket_nr <= "000";
770 end if;
771 end if;
772 next_state_tmp <= next_state;
773 write_length_bytes <= local_write_length (15 downto 0) & '0'; -- shift left (*2)
774 data_cnt <= 0;
775 state_write <= WR_01;
776 -- Check FIFO Size
777 when WR_01 =>
778 par_addr <= W5300_S0_TX_FSR + local_socket_nr * W5300_S_INC;
779 state_init <= READ_REG;
780 next_state <= WRITE_DATA;
781 state_write <= WR_02;
782 when WR_02 =>
783 socket_tx_free (31 downto 16) <= data_read;
784 par_addr <= W5300_S0_TX_FSR + (local_socket_nr * W5300_S_INC) + X"2";
785 state_init <= READ_REG;
786 next_state <= WRITE_DATA;
787 state_write <= WR_03;
788 when WR_03 =>
789 socket_tx_free (15 downto 0) <= data_read;
790 state_write <= WR_04;
791 when WR_04 =>
792
793-- led <= socket_tx_free (15 downto 8);
794
795-- if (socket_tx_free (16 downto 0) < write_length_bytes) then
796 if (socket_tx_free (16 downto 0) < W5300_TX_FIFO_SIZE_8B) then
797 state_write <= WR_01;
798 else
799 if (local_write_header_flag = '1') then
800 state_write <= WR_FIFO;
801 else
802 state_write <= WR_ADC;
803 end if;
804 end if;
805
806 -- Fill FIFO
807
808 -- Write Header
809 when WR_FIFO =>
810 ram_addr <= local_ram_start_addr + local_ram_addr;
811 state_write <= WR_FIFO1;
812 when WR_FIFO1 =>
813 data_cnt <= data_cnt + 1;
814 if (data_cnt < PACKAGE_HEADER_LENGTH) then --???
815 local_ram_addr <= local_ram_addr + 1;
816 if (data_cnt = 2 or data_cnt = 5 or data_cnt = 8 ) then -- skip empty words
817 local_ram_addr <= local_ram_addr + 2;
818 end if;
819 if (data_cnt = 9) then -- skip empty words
820 local_ram_addr <= local_ram_addr + 4;
821 end if;
822 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
823 ram_access <= '1';
824 state_init <= WRITE_REG;
825 next_state <= WRITE_DATA;
826 state_write <= WR_FIFO;
827 else
828 state_write <= WR_ADC;
829 end if;
830 -- End Write Header
831
832 -- Write ADC-Data
833 ---- Start...
834 when WR_ADC =>
835 adc_data_addr <= local_ram_start_addr + local_ram_addr;
836 drs_cnt <= 0;
837 channel_cnt <= 1;
838 data_cnt <= 0;
839 roi_max <= (others => '0');
840 data_end <= 3;
841 state_write <= WR_ADC1;
842
843 ---- Write Channel
844 when WR_ADC1 =>
845 -- read ROI and set end of Channel-Data
846 if (data_cnt = 3) then
847 data_end <= conv_integer (ram_data) + 3;
848 if (ram_data > roi_max) then
849 roi_max <= ram_data (10 downto 0);
850 end if;
851 end if;
852 ram_addr <= adc_data_addr + drs_cnt + (data_cnt * 4);
853 state_write <= WR_ADC2;
854 when WR_ADC2 =>
855 if (data_cnt < data_end) then
856 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
857 ram_access <= '1';
858 state_init <= WRITE_REG;
859 next_state <= WRITE_DATA;
860 data_cnt <= data_cnt + 1;
861 state_write <= WR_ADC1;
862 else
863 -- Next DRS
864 if (drs_cnt < 3) then
865 drs_cnt <= drs_cnt + 1;
866 data_cnt <= 0;
867 data_end <= 3;
868 state_write <= WR_ADC1;
869 else
870 -- Next Channel
871 if (channel_cnt < local_fifo_channels) then
872 channel_cnt <= channel_cnt + 1;
873 roi_max <= (others => '0');
874 drs_cnt <= 0;
875 data_cnt <= 0;
876 data_end <= 3;
877 adc_data_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4);
878 state_write <= WR_ADC1;
879 else
880 -- Ready
881 if (local_write_end_flag = '1') then
882 state_write <= WR_ENDFLAG;
883 else
884 state_write <= WR_05;
885 end if;
886 end if;
887 end if;
888 end if;
889 -- End Write ADC-Data
890
891 -- Write End Package Flag
892 when WR_ENDFLAG =>
893 ram_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4);
894 state_write <= WR_ENDFLAG1;
895 when WR_ENDFLAG1 =>
896 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
897 ram_access <= '1';
898 state_init <= WRITE_REG;
899 next_state <= WRITE_DATA;
900 state_write <= WR_ENDFLAG2;
901 when WR_ENDFLAG2 =>
902 ram_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4) + 1;
903 state_write <= WR_ENDFLAG3;
904 when WR_ENDFLAG3 =>
905 state_init <= WRITE_REG;
906 next_state <= WRITE_DATA;
907 state_write <= WR_05a;
908
909 -- End Write End Package Flag
910
911 -- Wait????
912 when WR_05a =>
913 if (wait_cntr < 10) then -- 3000 works???
914 wait_cntr <= wait_cntr + 1;
915 else
916 wait_cntr <= 0;
917 state_write <= WR_05b;
918 end if;
919 when WR_05b =>
920 state_write <= WR_05;
921
922 --Send FIFO
923 when WR_05 =>
924 ram_access <= '0';
925 par_addr <= W5300_S0_TX_WRSR + local_socket_nr * W5300_S_INC;
926 par_data <= (0 => write_length_bytes (16), others => '0');
927 state_init <= WRITE_REG;
928 state_write <= WR_06;
929 when WR_06 =>
930 par_addr <= W5300_S0_TX_WRSR + (local_socket_nr * W5300_S_INC) + X"2";
931 par_data <= write_length_bytes (15 downto 0);
932 state_init <= WRITE_REG;
933 state_write <= WR_07;
934 when WR_07 =>
935 par_addr <= W5300_S0_CR + local_socket_nr * W5300_S_INC;
936 par_data <= X"0020"; -- Send
937 state_init <= WRITE_REG;
938 state_write <= WR_08;
939 when others =>
940 state_init <= next_state_tmp;
941 state_write <= WR_START;
942 end case;
943 -- End WRITE_DATA
944
945 when READ_REG =>
946 case count is
947 when "000" =>
948 cs <= '0';
949 rd <= '0';
950 wr <= '1';
951 data <= (others => 'Z'); -- !!!!!!!!!!
952 count <= "001";
953 addr <= par_addr;
954 when "001" =>
955 count <= "010";
956 when "010" =>
957 count <= "100";
958 when "100" =>
959 data_read <= data;
960 count <= "110";
961 when "110" =>
962 count <= "111";
963 when "111" =>
964 cs <= '1';
965 rd <= '1';
966 count <= "000";
967 state_init <= next_state;
968 when others =>
969 null;
970 end case;
971
972 when WRITE_REG =>
973 case count is
974 when "000" =>
975 cs <= '0';
976 wr <= '0';
977 rd <= '1';
978 addr <= par_addr;
979 if (ram_access = '1') then
980 data <= ram_data;
981 else
982 data <= par_data;
983 end if;
984 count <= "100";
985 when "100" =>
986 count <= "101";
987 when "101" =>
988 count <= "110";
989 when "110" =>
990 cs <= '1';
991 wr <= '1';
992 state_init <= next_state;
993 count <= "000";
994 when others =>
995 null;
996 end case;
997
998 when others =>
999 null;
1000 end case;
1001 end if; -- int_flag = '0'
1002
1003 end if; -- rising_edge (clk)
1004
1005 end process w5300_init_proc;
1006
1007end Behavioral;
1008
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