source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd@ 10137

Last change on this file since 10137 was 10137, checked in by neise, 11 years ago
added some comments and did some formating
File size: 36.6 KB
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1-- Module Name: w5300_modul - Behavioral
2library IEEE;
3use IEEE.STD_LOGIC_1164.ALL;
4use IEEE.STD_LOGIC_ARITH.ALL;
5use IEEE.STD_LOGIC_UNSIGNED.ALL;
6library FACT_FAD_lib;
7use FACT_FAD_lib.fad_definitions.ALL;
8
9ENTITY w5300_modul IS
10 generic(
11 RAM_ADDR_WIDTH : integer := 14
12 );
13 PORT(
14 clk : IN std_logic;
15 wiz_reset : OUT std_logic := '1';
16 addr : OUT std_logic_vector (9 DOWNTO 0);
17 data : INOUT std_logic_vector (15 DOWNTO 0);
18 cs : OUT std_logic := '1';
19 wr : OUT std_logic := '1';
20 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
21 rd : OUT std_logic := '1';
22 int : IN std_logic;
23 write_length : IN std_logic_vector (16 DOWNTO 0);
24 ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
25 ram_data : IN std_logic_vector (15 DOWNTO 0);
26 ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
27 data_valid : IN std_logic;
28 data_valid_ack : OUT std_logic := '0';
29 busy : OUT std_logic := '1';
30 write_header_flag, write_end_flag : IN std_logic;
31 fifo_channels : IN std_logic_vector (3 downto 0);
32 -- softtrigger:
33 s_trigger : OUT std_logic := '0';
34 c_trigger_enable: out std_logic := '0';
35 c_trigger_mult: out std_logic_vector (7 DOWNTO 0) := (OTHERS => '1'); --subject to changes
36
37 -- FAD configuration signals:
38 ------------------------------------------------------------------------------
39 -- start entire configuration chain
40 new_config : OUT std_logic := '0';
41 config_started : in std_logic;
42 -- read/write configRAM
43 config_addr : out std_logic_vector (7 downto 0);
44 config_data : inout std_logic_vector (15 downto 0) := (others => 'Z');
45 config_wr_en : out std_logic := '0';
46 config_rd_en : out std_logic := '0';
47 config_rw_ack, config_rw_ready : in std_logic;
48 config_busy : in std_logic;
49 ------------------------------------------------------------------------------
50
51 -- MAC/IP calculation signals:
52 ------------------------------------------------------------------------------
53 MAC_jumper : in std_logic_vector (1 downto 0);
54 BoardID : in std_logic_vector (3 downto 0);
55 CrateID : in std_logic_vector (1 downto 0);
56 ------------------------------------------------------------------------------
57
58 -- user controllable enable signals
59 ------------------------------------------------------------------------------
60 trigger_enable : out std_logic := '0'; -- default triggers are NOT accepted
61 denable : out std_logic := '0'; -- default domino wave off
62 dwrite_enable : out std_logic := '0'; -- default DWRITE low.
63 sclk_enable : out std_logic := '1'; -- default DWRITE HIGH.
64 srclk_enable : out std_logic := '1'; -- default SRCLK on.
65 ------------------------------------------------------------------------------
66
67 -- ADC CLK generator, is able to shift phase with respect to X_50M
68 -- these signals control the behavior of the digital clock manager (DCM)
69 ------------------------------------------------------------------------------
70 ps_direction : out std_logic := '1'; -- default phase shift upwards
71 ps_do_phase_shift : out std_logic := '0'; --pulse this to phase shift once
72 ps_reset : out std_logic := '0'; -- pulse this to reset the variable phase shift
73 ------------------------------------------------------------------------------
74
75 -- signals used to control FAD LED bahavior:
76 -- one of the three LEDs is used for com-status info
77 ------------------------------------------------------------------------------
78 socks_waiting : out std_logic;
79 socks_connected: out std_logic
80 ------------------------------------------------------------------------------
81
82
83 );
84END w5300_modul ;
85
86architecture Behavioral of w5300_modul is
87
88type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA,
89 INIT, LOCATE, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY,
90 SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, READ_DATA);
91type state_write_type is (WR_START, WR_LENGTH, WR_WAIT1, WR_01, WR_02, WR_03, WR_04, WR_05, WR_05a, WR_05b, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2,
92 WR_ENDFLAG, WR_ENDFLAG1, WR_ENDFLAG2, WR_ENDFLAG3);
93type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04);
94type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06);
95type state_read_data_type is (RD_1, RD_2, RD_3, RD_4, RD_5, RD_6, RD_WAIT, RD_WAIT1, RD_END);
96
97signal RST_TIME : std_logic_vector(19 downto 0) := X"7A120";
98
99signal par_addr : std_logic_vector (9 downto 0) := (OTHERS => '0');
100signal par_data : std_logic_vector (15 downto 0) := (OTHERS => '0');
101signal data_read : std_logic_vector (15 downto 0) := (OTHERS => '0');
102signal adc_data_addr : std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
103
104signal state_init, next_state , next_state_tmp : state_init_type := RESET;
105signal count : std_logic_vector (2 downto 0) := "000";
106signal state_write : state_write_type := WR_START;
107signal state_interrupt_1 : state_interrupt_1_type := IR1_01;
108signal state_interrupt_2 : state_interrupt_2_type := IR2_01;
109signal state_read_data : state_read_data_type := RD_1;
110
111signal interrupt_ignore : std_logic := '1';
112signal int_flag : std_logic := '0';
113signal ram_access : std_logic := '0';
114
115signal zaehler : std_logic_vector (19 downto 0) := (OTHERS => '0');
116signal data_cnt : integer := 0;
117signal drs_cnt : integer :=0;
118signal channel_cnt : integer range 0 to 9 :=0;
119signal socket_cnt : std_logic_vector (2 downto 0) := "000";
120signal roi_max : std_logic_vector (10 downto 0);
121signal data_end : integer := 0;
122
123signal socket_tx_free : std_logic_vector (31 downto 0) := (others => '0');
124signal write_length_bytes : std_logic_vector (16 downto 0);
125
126signal socket_rx_received : std_logic_vector (31 downto 0) := (others => '0');
127signal chk_recv_cntr : integer range 0 to 10000 := 0;
128
129-- --
130signal wait_cntr : integer range 0 to 10000 := 0;
131-- --
132
133signal rx_packets_cnt : std_logic_vector (15 downto 0);
134signal next_packet_data : std_logic := '0';
135signal new_config_flag : std_logic := '0';
136
137signal trigger_stop : std_logic := '1';
138
139signal local_write_length : std_logic_vector (16 DOWNTO 0);
140signal local_ram_start_addr : std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
141signal local_ram_addr : std_logic_vector (RAM_ADDR_WIDTH-1 downto 0);
142signal local_socket_nr : std_logic_vector (2 DOWNTO 0);
143signal local_write_header_flag, local_write_end_flag : std_logic;
144signal local_fifo_channels : std_logic_vector (3 downto 0);
145
146signal data_valid_int : std_logic := '0';
147
148
149-- signals used for MAC/IP calculation:
150-- these 2 synch in, the jumper state.
151signal FAD_in_cam : std_logic := '0';
152signal FAD_at_ETHZ : std_logic := '0';
153-- these 2 synch in the FMP lines encoding the FAD position in the cam.
154signal bid : std_logic_vector (3 downto 0);
155signal cid : std_logic_vector (1 downto 0);
156-- these are just used as local variables, to make reading easier.
157signal mac_loc : mac_type;
158signal ip_loc : ip_type;
159signal gateway_loc : ip_type;
160signal netmask_loc : ip_type;
161
162 -- signals for synching in asynchronous input signals
163 ------------------------------------------------------------------------------
164 signal w5300_interrupt_sr : std_logic_vector(1 downto 0);
165 ------------------------------------------------------------------------------
166
167
168-- only for debugging
169--signal error_cnt : std_logic_vector (7 downto 0) := (others => '0');
170--signal last_trigger_id : std_logic_vector (15 downto 0) := (others => '0');
171
172
173-- signals for different socket modes: DN 04.01.11
174signal socket_nr_counter : integer range 1 to 7 :=1; --used to determine which socket is used for data sending
175signal socket_send_mode : std_logic := '0'; -- if 0 data is send via socket 0; if 1 data is send via the other sockets.
176
177begin
178
179 --synthesis translate_off
180 RST_TIME <= X"00120";
181 --synthesis translate_on
182
183
184 w5300_proc : process (clk)
185 begin
186 if rising_edge (clk) then
187 -- synch asynchronous input in:
188 w5300_interrupt_sr <= w5300_interrupt_sr(1) & int;
189
190 -- interrupt is handled synchronously
191 -- W5300 pulls low its interrpt line in case of:
192 -- ??? I don't know ... connection loss ???
193
194 if (w5300_interrupt_sr = "01") and (interrupt_ignore = '0') then
195 case state_interrupt_1 is
196 when IR1_01 =>
197 int_flag <= '1';
198 busy <= '1';
199 state_interrupt_1 <= IR1_02; --wait one cycle
200 when IR1_02 =>
201 state_interrupt_1 <= IR1_03;
202 when IR1_03 =>
203 state_init <= INTERRUPT;
204 socket_cnt <= "000";
205 ram_access <= '0';
206 zaehler <= X"00000"; --what is this zaehler counting?
207 count <= "000"; --what is this count counting?
208 int_flag <= '0';
209 interrupt_ignore <= '1';
210 state_interrupt_1 <= IR1_04; --this state is not existing? bad coding habit???
211 when others =>
212 null;
213 end case;
214 end if; -- int = '0'
215
216 if int_flag = '0' then
217 case state_init is
218 -- Interrupt
219 when INTERRUPT =>
220 case state_interrupt_2 is
221 when IR2_01 =>
222 par_addr <= W5300_IR;
223 state_init <= READ_REG;
224 next_state <= INTERRUPT;
225 state_interrupt_2 <= IR2_02;
226
227 -- check if it was a Sx Interrupt of Socket n
228 -- therfor: loop over all channel.
229 -- if the loop ended but no Sx Interrupt was found --> IR2_06
230 -- if an Sx Interrupt was found go to --> IR2_03 and check what happened.
231 when IR2_02 =>
232 if (data_read (conv_integer(socket_cnt)) = '1') then -- Sx Interrupt
233 state_interrupt_2 <= IR2_03;
234 else
235 socket_cnt <= socket_cnt + 1;
236 if (socket_cnt = 7) then
237 state_interrupt_2 <= IR2_06;
238 else
239 state_interrupt_2 <= IR2_02; -- go on with loop
240 end if;
241 end if;
242
243 -- check the Interrupt register of the Socket, which caused the Interrupt.
244 when IR2_03 =>
245 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; -- Sx Interrupt Register
246 state_init <= READ_REG;
247 next_state <= INTERRUPT;
248 state_interrupt_2 <= IR2_04;
249 -- before checking what happened, clear the Interrupt register, so we can proceed.
250 when IR2_04 =>
251 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC;
252 par_data <= data_read; -- clear Interrupts
253 state_init <= WRITE_REG;
254 next_state <= INTERRUPT;
255 state_interrupt_2 <= IR2_05;
256 -- send the command to close this socket
257 -- then go back and read the main Interrupt register again,
258 -- if this was not Socket 7 ... if it was Socket 7, we're done anyway.
259 when IR2_05 =>
260 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
261 par_data <= X"0010"; -- CLOSE
262 state_init <= WRITE_REG;
263 next_state <= INTERRUPT;
264 socket_cnt <= socket_cnt + 1;
265 if (socket_cnt = 7) then
266 state_interrupt_2 <= IR2_06;
267 else
268 state_interrupt_2 <= IR2_01;
269 end if;
270
271 -- we go on and reset, the W5300 and this entire state machine.
272 when IR2_06 =>
273 state_interrupt_1 <= IR1_01;
274 state_interrupt_2 <= IR2_01;
275 socket_cnt <= "000";
276 state_init <= RESET;
277 end case;
278
279 -- reset W5300
280 when RESET =>
281 socket_send_mode <= '0';
282 busy <= '1';
283 zaehler <= zaehler + 1;
284 socks_waiting <= '0';
285 socks_connected <= '0';
286 wiz_reset <= '0';
287 --led <= X"FF";
288 if (zaehler >= X"00064") then -- wait 2µs
289 wiz_reset <= '1';
290 end if;
291 if (zaehler = RST_TIME) then -- wait 10ms
292 zaehler <= X"00000";
293 socket_cnt <= "000";
294 count <= "000";
295 ram_access <= '0';
296 interrupt_ignore <= '0';
297 rd <= '1';
298 wr <= '1';
299 cs <= '1';
300 state_write <= WR_START;
301 state_init <= INIT;
302 end if;
303
304 -- Init
305 when INIT =>
306 -- status of MAC jumpers is synched in
307 -- and Board- and CrateID are synched in
308 FAD_in_cam <= MAC_jumper(1); -- see position of jumpers in FACT logbook
309 FAD_at_ETHZ <= MAC_jumper(0); -- MAC_jumper(1) is where D_T(7) was; MAC_jumper(0) is where D_T(6) was;
310 bid <= BoardID;
311 cid <= CrateID;
312 par_addr <= W5300_MR;
313 par_data <= X"0000";
314 state_init <= WRITE_REG;
315 next_state <= LOCATE;
316
317 when LOCATE =>
318 state_init <= IM;
319
320 if (FAD_in_cam = '1') then
321 if (bid = "1111" and cid="11") then
322 -- if BID = "1111" and CID="11" then FAD is not really in cam
323 -- I don't know what to do now.
324 -- I could wait a long time, and then just assume, I was not in cam.
325 -- this should never happen!!!!!
326 -- impossible to find this out, if in cam
327 state_init <= INIT;
328 else -- everything is fine
329 -- IP & MAC are calculated from BID & CID
330 -- code here
331 gateway_loc <= CAM_GATEWAY;
332 netmask_loc <= CAM_NETMASK;
333 mac_loc <= (CAM_MAC_prefix (0), CAM_MAC_prefix (1) , conv_std_logic_vector ( conv_integer(cid)*10+conv_integer(bid) , 16) );
334 ip_loc <= ( CAM_IP_PREFIX(0) , CAM_IP_PREFIX(1) , IP_offset + conv_integer(cid) , IP_offset + conv_integer(bid) );
335 end if;
336 else -- FAD is tested, either at ETHZ or at TUDO AND either with FMP or without.
337 if ( FAD_at_ETHZ = '0' ) then
338 -- easy FAD is at TUDO -> only one choice.
339 mac_loc <= MAC_FAD0;
340 ip_loc <= IP_TUDO;
341 gateway_loc <= TUDO_GATEWAY;
342 netmask_loc <= TUDO_NETMASK;
343 else -- FAD is at ETHZ but not in cam --> IP lookup table is needed.
344 if (bid = "1111" and cid="11") then -- FAD is not in crate
345 mac_loc <= MAC_FAD0;
346 ip_loc <= IP_ETHZ_FAD0;
347 gateway_loc <= ETHZ_GATEWAY;
348 netmask_loc <= ETHZ_NETMASK;
349 else
350 -- FAD is at ETHZ and in crate:
351 -- crate ID is not of importance.
352 -- we only have 3 MACs and IPs so far, so only the first boardIDs are allowed.
353 if ( conv_integer(bid) < MAC_LIST'length) then
354 gateway_loc <= ETHZ_GATEWAY;
355 netmask_loc <= ETHZ_NETMASK;
356 mac_loc <= MAC_LIST(conv_integer(bid));
357 ip_loc <= IP_LIST(conv_integer(bid));
358 end if; -- conv_integer
359 end if; -- bid=1111 & cid=11
360 end if; --FAD_at_ETHZ = 0
361 end if; --FAD_in_cam = 1
362
363 -- Interrupt Mask
364 when IM =>
365 par_addr <= W5300_IMR;
366 par_data <= X"00FF"; -- S0-S7 Interrupts
367 state_init <= WRITE_REG;
368 next_state <= MT;
369
370 -- Memory Type
371 when MT =>
372 par_addr <= W5300_MTYPER;
373 par_data <= X"7FFF"; -- 8K RX, 120K TX-Buffer
374 state_init <= WRITE_REG;
375 next_state <= STX;
376
377 -- Socket TX Memory Size
378 when STX =>
379 par_data <= X"0F0F"; -- 15K TX
380
381 par_addr <= W5300_TMS01R;
382 state_init <=WRITE_REG;
383 next_state <= STX1;
384 when STX1 =>
385 par_addr <= W5300_TMS23R;
386 state_init <=WRITE_REG;
387 next_state <= STX2;
388 when STX2 =>
389 par_addr <= W5300_TMS45R;
390 state_init <=WRITE_REG;
391 next_state <= STX3;
392 when STX3 =>
393 par_addr <= W5300_TMS67R;
394 state_init <=WRITE_REG;
395 next_state <= SRX;
396
397 -- Socket RX Memory Size
398 when SRX =>
399 par_data <= X"0101"; -- 1K RX
400
401 par_addr <= W5300_RMS01R;
402 state_init <=WRITE_REG;
403 next_state <= SRX1;
404 when SRX1 =>
405 par_addr <= W5300_RMS23R;
406 state_init <=WRITE_REG;
407 next_state <= SRX2;
408 when SRX2 =>
409 par_addr <= W5300_RMS45R;
410 state_init <=WRITE_REG;
411 next_state <= SRX3;
412 when SRX3 =>
413 par_addr <= W5300_RMS67R;
414 state_init <=WRITE_REG;
415 next_state <= MAC;
416
417 -- MAC
418 when MAC =>
419 par_addr <= W5300_SHAR;
420 par_data <= mac_loc(0);
421 state_init <= WRITE_REG;
422 next_state <= MAC1;
423 when MAC1 =>
424 par_addr <= W5300_SHAR + 2;
425 par_data <= mac_loc(1);
426 state_init <= WRITE_REG;
427 next_state <= MAC2;
428 when MAC2 =>
429 par_addr <= W5300_SHAR + 4;
430 par_data <= mac_loc(2);
431 state_init <= WRITE_REG;
432 next_state <= GW;
433
434 -- Gateway
435 when GW =>
436 par_addr <= W5300_GAR;
437 par_data (15 downto 8) <= conv_std_logic_vector(gateway_loc(0),8);
438 par_data (7 downto 0) <= conv_std_logic_vector(gateway_loc(1),8);
439 state_init <= WRITE_REG;
440 next_state <= GW1;
441 when GW1 =>
442 par_addr <= W5300_GAR + 2;
443 par_data (15 downto 8) <= conv_std_logic_vector(gateway_loc(2),8);
444 par_data (7 downto 0) <= conv_std_logic_vector(gateway_loc(3),8);
445 state_init <= WRITE_REG;
446 next_state <= SNM;
447
448 -- Subnet Mask
449 when SNM =>
450 par_addr <= W5300_SUBR;
451 par_data (15 downto 8) <= conv_std_logic_vector(netmask_loc(0),8);
452 par_data (7 downto 0) <= conv_std_logic_vector(netmask_loc(1),8);
453 state_init <= WRITE_REG;
454 next_state <= SNM1;
455 when SNM1 =>
456 par_addr <= W5300_SUBR + 2;
457 par_data (15 downto 8) <= conv_std_logic_vector(netmask_loc(2),8);
458 par_data (7 downto 0) <= conv_std_logic_vector(netmask_loc(3),8);
459 state_init <= WRITE_REG;
460 next_state <= IP;
461 -- Own IP-Address
462 when IP =>
463 par_addr <= W5300_SIPR;
464 par_data (15 downto 8) <= conv_std_logic_vector(ip_loc(0),8);
465 par_data (7 downto 0) <= conv_std_logic_vector(ip_loc(1),8);
466 state_init <= WRITE_REG;
467 next_state <= IP1;
468 when IP1 =>
469 par_addr <= W5300_SIPR + 2;
470 par_data (15 downto 8) <= conv_std_logic_vector(ip_loc(2),8);
471 par_data (7 downto 0) <= conv_std_logic_vector(ip_loc(3),8);
472 state_init <= WRITE_REG;
473 next_state <= SI;
474-- when TIMEOUT =>
475-- par_addr <= W5300_RTR;
476-- par_data <= X"07D0"; -- 0x07D0 = 200ms
477-- state_init <= WRITE_REG;
478-- next_state <= RETRY;
479-- when RETRY =>
480-- par_addr <= W5300_RCR;
481-- par_data <= X"0008";
482-- state_init <= WRITE_REG;
483-- next_state <= SI;
484--
485
486 -- Socket Init
487 when SI =>
488 par_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC;
489 par_data <= X"0101"; -- ALIGN, TCP
490 state_init <= WRITE_REG;
491 next_state <= SI1;
492 -- Sx Interrupt Mask
493 when SI1 =>
494 par_addr <= W5300_S0_IMR + socket_cnt * W5300_S_INC;
495 par_data <= X"000A"; -- TIMEOUT, DISCON
496 state_init <= WRITE_REG;
497 next_state <= SI2;
498 when SI2 =>
499 par_addr <= W5300_S0_PORTR + socket_cnt * W5300_S_INC;
500 par_data <= conv_std_logic_vector(FIRST_PORT + unsigned (socket_cnt), 16);
501 state_init <= WRITE_REG;
502 next_state <= SI3;
503 when SI3 =>
504 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
505 par_data <= X"0001"; -- OPEN
506 state_init <= WRITE_REG;
507 next_state <= SI4;
508 when SI4 =>
509 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
510 state_init <= READ_REG;
511 next_state <= SI5;
512 when SI5 =>
513 if (data_read (7 downto 0) = X"13") then -- is open?
514 state_init <= SI6;
515 else
516 state_init <= SI4;
517 end if;
518 when SI6 =>
519 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
520 par_data <= X"0002"; -- LISTEN
521 state_init <= WRITE_REG;
522 socket_cnt <= socket_cnt + 1;
523 if (socket_cnt = 7) then
524 socket_cnt <= "000";
525 next_state <= ESTABLISH; -- All Sockets open
526 else
527 next_state <= SI; -- Next Socket
528 end if;
529 -- End Socket Init
530
531 when ESTABLISH =>
532 socks_waiting <= '1';
533 socks_connected <= '0';
534 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
535 state_init <= READ_REG;
536 next_state <= EST1;
537 when EST1 =>
538-- led <= data_read (7 downto 0);
539-- led <= X"00";
540 case data_read (7 downto 0) is
541 when X"17" => -- established
542 if (socket_cnt = 7) then
543 socket_cnt <= "000";
544 busy <= '0';
545 state_init <= MAIN;
546 else
547 socket_cnt <= socket_cnt + 1;
548 state_init <= ESTABLISH;
549 end if;
550 when others =>
551 state_init <= ESTABLISH;
552 end case;
553
554 when CONFIG =>
555-- led <= X"F0";
556 new_config <= '1';
557 if (config_started = '1') then
558-- led <= X"0F";
559 new_config <= '0';
560 state_init <= MAIN;
561 end if;
562
563 -- main "loop"
564 when MAIN =>
565 socks_waiting <= '0';
566 socks_connected <= '1';
567
568 ps_do_phase_shift <= '0';
569 ps_reset <= '0';
570 if (trigger_stop = '1') then
571 s_trigger <= '0';
572 end if;
573 data_valid_ack <= '0';
574 state_init <= MAIN1;
575 data_valid_int <= data_valid;
576 when MAIN1 =>
577 if (chk_recv_cntr = 1000) then
578 chk_recv_cntr <= 0;
579 state_read_data <= RD_1;
580 state_init <= READ_DATA;
581 busy <= '1';
582 else
583 chk_recv_cntr <= chk_recv_cntr + 1;
584 state_init <= MAIN2;
585 end if;
586 when MAIN2 =>
587 busy <= '0';
588 if (data_valid = '1') then
589 data_valid_int <= '0';
590 busy <= '1';
591 local_write_length <= write_length;
592 local_ram_start_addr <= ram_start_addr;
593 local_ram_addr <= (others => '0');
594 local_write_header_flag <= write_header_flag;
595 local_write_end_flag <= write_end_flag;
596 local_fifo_channels <= fifo_channels;
597-- data_valid_ack <= '1';
598-- next_state <= MAIN;
599-- state_init <= WRITE_DATA;
600 state_init <= MAIN3;
601 else
602 state_init <= MAIN1;
603 end if;
604 when MAIN3 =>
605-- led <= local_ram_start_addr (7 downto 0);
606 data_valid_ack <= '1';
607 next_state <= MAIN;
608 state_init <= WRITE_DATA;
609
610
611 -- read data from socket 0
612 when READ_DATA =>
613 case state_read_data is
614 when RD_1 =>
615 par_addr <= W5300_S0_RX_RSR;
616 state_init <= READ_REG;
617 next_state <= READ_DATA;
618 state_read_data <= RD_2;
619 when RD_2 =>
620 socket_rx_received (31 downto 16) <= data_read;
621 par_addr <= W5300_S0_RX_RSR + X"2";
622 state_init <= READ_REG;
623 next_state <= READ_DATA;
624 state_read_data <= RD_3;
625 when RD_3 =>
626 socket_rx_received (15 downto 0) <= data_read;
627 state_read_data <= RD_4;
628 when RD_4 =>
629 if (socket_rx_received (16 downto 0) > ('0' & X"000")) then
630 rx_packets_cnt <= socket_rx_received (16 downto 1); -- socket_rx_received / 2
631 state_read_data <= RD_5;
632 else
633 busy <= '0';
634 state_init <= MAIN;
635 end if;
636 when RD_5 =>
637 if (rx_packets_cnt > 0) then
638 rx_packets_cnt <= rx_packets_cnt - '1';
639 par_addr <= W5300_S0_RX_FIFOR;
640 state_init <= READ_REG;
641 next_state <= READ_DATA;
642 state_read_data <= RD_6;
643 else
644 state_read_data <= RD_END;
645 end if;
646 when RD_6 =>
647-- led <= data_read (15 downto 8);
648 -- read command
649 if (next_packet_data = '0') then
650 case data_read (15 downto 8) is
651
652 when CMD_START => -- all data will be send via socket 1..7
653 socket_send_mode <= '1';
654 state_read_data <= RD_5;
655 when CMD_STOP => -- all data will be send via socket 0
656 socket_send_mode <= '0';
657 state_read_data <= RD_5;
658
659
660 when CMD_TRIGGER =>
661 trigger_stop <= '1';
662 s_trigger <= '1';
663 state_read_data <= RD_5;
664 when CMD_DWRITE_RUN =>
665 dwrite_enable <= '1';
666 state_read_data <= RD_5;
667 when CMD_DWRITE_STOP =>
668 dwrite_enable <= '0';
669 state_read_data <= RD_5;
670 when CMD_SCLK_ON =>
671 sclk_enable <= '1';
672 state_read_data <= RD_5;
673 when CMD_SCLK_OFF =>
674 sclk_enable <= '0';
675 state_read_data <= RD_5;
676 when CMD_DENABLE =>
677 denable <= '1';
678 state_read_data <= RD_5;
679 when CMD_DDISABLE =>
680 denable <= '0';
681 state_read_data <= RD_5;
682 when CMD_TRIGGER_C =>
683 c_trigger_enable <= '1';
684 --trigger_stop <= '0';
685 --s_trigger <= '1';
686 state_read_data <= RD_5;
687 when CMD_TRIGGER_S =>
688 c_trigger_enable <= '0';
689 --trigger_stop <= '1';
690 state_read_data <= RD_5;
691 when CMD_SET_TRIGGER_MULT =>
692 c_trigger_mult <= data_read (7 downto 0);
693 state_read_data <= RD_5;
694
695 -- phase shift commands here:
696 when CMD_PS_DO =>
697 ps_do_phase_shift <= '1';
698 state_read_data <= RD_5;
699 when CMD_PS_DIRINC =>
700 ps_direction <= '1';
701 state_read_data <= RD_5;
702 when CMD_PS_RESET =>
703 ps_reset <= '1';
704 state_read_data <= RD_5;
705
706 when CMD_SRCLK_ON =>
707 srclk_enable <= '1';
708 state_read_data <= RD_5;
709 when CMD_SRCLK_OFF =>
710 srclk_enable <= '0';
711 state_read_data <= RD_5;
712
713 when CMD_TRIGGERS_ON =>
714 trigger_enable <= '1';
715 state_read_data <= RD_5;
716 when CMD_TRIGGERS_OFF =>
717 trigger_enable <= '0';
718 state_read_data <= RD_5;
719
720
721 when CMD_PS_DIRDEC =>
722 ps_direction <= '0';
723 state_read_data <= RD_5;
724 when CMD_WRITE =>
725 next_packet_data <= '1';
726 config_addr <= data_read (7 downto 0);
727 state_read_data <= RD_5;
728 when others =>
729 state_read_data <= RD_5;
730 end case;
731 -- read data
732 else
733 if (config_busy = '0') then
734 config_data <= data_read;
735 config_wr_en <= '1';
736 new_config_flag <= '1';
737 next_packet_data <= '0';
738 state_read_data <= RD_WAIT;
739 end if;
740 end if;
741 when RD_WAIT =>
742 if (config_rw_ack = '1') then
743 state_read_data <= RD_WAIT1;
744 end if;
745 when RD_WAIT1 =>
746 if (config_rw_ready = '1') then
747 config_data <= (others => 'Z');
748 config_wr_en <= '0';
749 state_read_data <= RD_5;
750 end if;
751 when RD_END =>
752 par_addr <= W5300_S0_CR;
753 par_data <= X"0040"; -- RECV
754 state_init <= WRITE_REG;
755 if (new_config_flag = '1') then
756 new_config_flag <= '0';
757 next_state <= CONFIG;
758 else
759 next_state <= MAIN;
760 end if;
761
762 end case; -- state_data_read
763
764
765
766 when WRITE_DATA =>
767 case state_write is
768 when WR_START =>
769 if (local_write_header_flag = '1') then
770 ram_addr <= local_ram_start_addr + 5; -- Address of Trigger-ID (15 downto 0) ????
771 end if;
772 state_write <= WR_WAIT1;
773 when WR_WAIT1 =>
774 state_write <= WR_LENGTH;
775 when WR_LENGTH =>
776 if (local_write_header_flag = '1') then
777 if (socket_send_mode = '1') then -- send via all sockets
778 local_socket_nr <= conv_std_logic_vector(socket_nr_counter, 3);
779 if (socket_nr_counter < 7) then
780 socket_nr_counter <= socket_nr_counter + 1;
781 else
782 socket_nr_counter <= 1;
783 end if;
784 else -- only send via socket 0\
785 local_socket_nr <= "000";
786 end if;
787 end if;
788 next_state_tmp <= next_state;
789 write_length_bytes <= local_write_length (15 downto 0) & '0'; -- shift left (*2)
790 data_cnt <= 0;
791 state_write <= WR_01;
792 -- Check FIFO Size
793 when WR_01 =>
794 par_addr <= W5300_S0_TX_FSR + local_socket_nr * W5300_S_INC;
795 state_init <= READ_REG;
796 next_state <= WRITE_DATA;
797 state_write <= WR_02;
798 when WR_02 =>
799 socket_tx_free (31 downto 16) <= data_read;
800 par_addr <= W5300_S0_TX_FSR + (local_socket_nr * W5300_S_INC) + X"2";
801 state_init <= READ_REG;
802 next_state <= WRITE_DATA;
803 state_write <= WR_03;
804 when WR_03 =>
805 socket_tx_free (15 downto 0) <= data_read;
806 state_write <= WR_04;
807 when WR_04 =>
808
809-- led <= socket_tx_free (15 downto 8);
810
811-- if (socket_tx_free (16 downto 0) < write_length_bytes) then
812 if (socket_tx_free (16 downto 0) < W5300_TX_FIFO_SIZE_8B) then
813 state_write <= WR_01;
814 else
815 if (local_write_header_flag = '1') then
816 state_write <= WR_FIFO;
817 else
818 state_write <= WR_ADC;
819 end if;
820 end if;
821
822 -- Fill FIFO
823
824 -- Write Header
825 when WR_FIFO =>
826 ram_addr <= local_ram_start_addr + local_ram_addr;
827 state_write <= WR_FIFO1;
828 when WR_FIFO1 =>
829 data_cnt <= data_cnt + 1;
830 if (data_cnt < PACKAGE_HEADER_LENGTH) then --???
831 local_ram_addr <= local_ram_addr + 1;
832 if (data_cnt = 2 or data_cnt = 5 or data_cnt = 8 ) then -- skip empty words
833 local_ram_addr <= local_ram_addr + 2;
834 end if;
835 if (data_cnt = 9) then -- skip empty words
836 local_ram_addr <= local_ram_addr + 4;
837 end if;
838 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
839 ram_access <= '1';
840 state_init <= WRITE_REG;
841 next_state <= WRITE_DATA;
842 state_write <= WR_FIFO;
843 else
844 state_write <= WR_ADC;
845 end if;
846 -- End Write Header
847
848 -- Write ADC-Data
849 ---- Start...
850 when WR_ADC =>
851 adc_data_addr <= local_ram_start_addr + local_ram_addr;
852 drs_cnt <= 0;
853 channel_cnt <= 1;
854 data_cnt <= 0;
855 roi_max <= (others => '0');
856 data_end <= 3;
857 state_write <= WR_ADC1;
858
859 ---- Write Channel
860 when WR_ADC1 =>
861 -- read ROI and set end of Channel-Data
862 if (data_cnt = 3) then
863 data_end <= conv_integer (ram_data) + 3;
864 if (ram_data > roi_max) then
865 roi_max <= ram_data (10 downto 0);
866 end if;
867 end if;
868 ram_addr <= adc_data_addr + drs_cnt + (data_cnt * 4);
869 state_write <= WR_ADC2;
870 when WR_ADC2 =>
871 if (data_cnt < data_end) then
872 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
873 ram_access <= '1';
874 state_init <= WRITE_REG;
875 next_state <= WRITE_DATA;
876 data_cnt <= data_cnt + 1;
877 state_write <= WR_ADC1;
878 else
879 -- Next DRS
880 if (drs_cnt < 3) then
881 drs_cnt <= drs_cnt + 1;
882 data_cnt <= 0;
883 data_end <= 3;
884 state_write <= WR_ADC1;
885 else
886 -- Next Channel
887 if (channel_cnt < local_fifo_channels) then
888 channel_cnt <= channel_cnt + 1;
889 roi_max <= (others => '0');
890 drs_cnt <= 0;
891 data_cnt <= 0;
892 data_end <= 3;
893 adc_data_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4);
894 state_write <= WR_ADC1;
895 else
896 -- Ready
897 if (local_write_end_flag = '1') then
898 state_write <= WR_ENDFLAG;
899 else
900 state_write <= WR_05;
901 end if;
902 end if;
903 end if;
904 end if;
905 -- End Write ADC-Data
906
907 -- Write End Package Flag
908 when WR_ENDFLAG =>
909 ram_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4);
910 state_write <= WR_ENDFLAG1;
911 when WR_ENDFLAG1 =>
912 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
913 ram_access <= '1';
914 state_init <= WRITE_REG;
915 next_state <= WRITE_DATA;
916 state_write <= WR_ENDFLAG2;
917 when WR_ENDFLAG2 =>
918 ram_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4) + 1;
919 state_write <= WR_ENDFLAG3;
920 when WR_ENDFLAG3 =>
921 state_init <= WRITE_REG;
922 next_state <= WRITE_DATA;
923 state_write <= WR_05a;
924
925 -- End Write End Package Flag
926
927 -- Wait????
928 when WR_05a =>
929 if (wait_cntr < 10) then -- 3000 works???
930 wait_cntr <= wait_cntr + 1;
931 else
932 wait_cntr <= 0;
933 state_write <= WR_05b;
934 end if;
935 when WR_05b =>
936 state_write <= WR_05;
937
938 --Send FIFO
939 when WR_05 =>
940 ram_access <= '0';
941 par_addr <= W5300_S0_TX_WRSR + local_socket_nr * W5300_S_INC;
942 par_data <= (0 => write_length_bytes (16), others => '0');
943 state_init <= WRITE_REG;
944 state_write <= WR_06;
945 when WR_06 =>
946 par_addr <= W5300_S0_TX_WRSR + (local_socket_nr * W5300_S_INC) + X"2";
947 par_data <= write_length_bytes (15 downto 0);
948 state_init <= WRITE_REG;
949 state_write <= WR_07;
950 when WR_07 =>
951 par_addr <= W5300_S0_CR + local_socket_nr * W5300_S_INC;
952 par_data <= X"0020"; -- Send
953 state_init <= WRITE_REG;
954 state_write <= WR_08;
955 when others =>
956 state_init <= next_state_tmp;
957 state_write <= WR_START;
958 end case;
959 -- End WRITE_DATA
960
961 when READ_REG =>
962 case count is
963 when "000" =>
964 cs <= '0';
965 rd <= '0';
966 wr <= '1';
967 data <= (others => 'Z'); -- !!!!!!!!!!
968 count <= "001";
969 addr <= par_addr;
970 when "001" =>
971 count <= "010";
972 when "010" =>
973 count <= "100";
974 when "100" =>
975 data_read <= data;
976 count <= "110";
977 when "110" =>
978 count <= "111";
979 when "111" =>
980 cs <= '1';
981 rd <= '1';
982 count <= "000";
983 state_init <= next_state;
984 when others =>
985 null;
986 end case;
987
988 when WRITE_REG =>
989 case count is
990 when "000" =>
991 cs <= '0';
992 wr <= '0';
993 rd <= '1';
994 addr <= par_addr;
995 if (ram_access = '1') then
996 data <= ram_data;
997 else
998 data <= par_data;
999 end if;
1000 count <= "100";
1001 when "100" =>
1002 count <= "101";
1003 when "101" =>
1004 count <= "110";
1005 when "110" =>
1006 cs <= '1';
1007 wr <= '1';
1008 state_init <= next_state;
1009 count <= "000";
1010 when others =>
1011 null;
1012 end case;
1013
1014 when others =>
1015 null;
1016 end case;
1017 end if; -- int_flag = '0'
1018
1019 end if; -- rising_edge (clk)
1020
1021 end process w5300_proc;
1022
1023end Behavioral;
1024
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