source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd@ 9912

Last change on this file since 9912 was 9912, checked in by neise, 12 years ago
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1----------------------------------------------------------------------------------
2-- Company:
3-- Engineer:
4--
5-- Create Date: 11:48:48 11/10/2009
6-- Design Name:
7-- Module Name: w5300_modul - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description:
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22use IEEE.STD_LOGIC_ARITH.ALL;
23use IEEE.STD_LOGIC_UNSIGNED.ALL;
24library FACT_FAD_lib;
25use FACT_FAD_lib.fad_definitions.ALL;
26
27---- Uncomment the following library declaration if instantiating
28---- any Xilinx primitives in this code.
29--library UNISIM;
30--use UNISIM.VComponents.all;
31
32ENTITY w5300_modul IS
33 generic(
34 RAM_ADDR_WIDTH : integer := 14
35 );
36 PORT(
37 clk : IN std_logic;
38 wiz_reset : OUT std_logic := '1';
39 addr : OUT std_logic_vector (9 DOWNTO 0);
40 data : INOUT std_logic_vector (15 DOWNTO 0);
41 cs : OUT std_logic := '1';
42 wr : OUT std_logic := '1';
43 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
44 rd : OUT std_logic := '1';
45 int : IN std_logic;
46 write_length : IN std_logic_vector (16 DOWNTO 0);
47 ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
48 ram_data : IN std_logic_vector (15 DOWNTO 0);
49 ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
50 data_valid : IN std_logic;
51 data_valid_ack : OUT std_logic := '0';
52 busy : OUT std_logic := '1';
53 write_header_flag, write_end_flag : IN std_logic;
54 fifo_channels : IN std_logic_vector (3 downto 0);
55 s_trigger : OUT std_logic := '0';
56 new_config : OUT std_logic := '0';
57 config_started : in std_logic;
58 config_addr : out std_logic_vector (7 downto 0);
59 config_data : inout std_logic_vector (15 downto 0) := (others => 'Z');
60 config_wr_en : out std_logic := '0';
61 config_rd_en : out std_logic := '0';
62 config_busy : in std_logic;
63
64
65
66 denable : out std_logic := '0'; -- default domino wave off
67 dwrite_enable : out std_logic := '0'; -- default DWRITE low.
68 sclk_enable : out std_logic := '1'; -- default DWRITE HIGH.
69 ps_direction : out std_logic := '1'; -- default phase shift upwards
70 ps_do_phase_shift : out std_logic := '0'; --pulse this to phase shift once
71 ps_reset : out std_logic := '0'; -- pulse this to reset the variable phase shift
72
73 srclk_enable : out std_logic := '1' -- default SRCLK on.
74 );
75
76-- Declarations
77
78END w5300_modul ;
79
80architecture Behavioral of w5300_modul is
81
82type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA,
83 INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY,
84 SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, CHK_RECEIVED, READ_DATA);
85type state_write_type is (WR_START, WR_LENGTH, WR_WAIT1, WR_01, WR_02, WR_03, WR_04, WR_05, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2,
86 WR_ENDFLAG, WR_ENDFLAG1, WR_ENDFLAG2, WR_ENDFLAG3);
87type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04);
88type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06);
89type state_read_data_type is (RD_1, RD_2, RD_3, RD_4, RD_5, RD_6, RD_WAIT, RD_WAIT1, RD_END);
90
91signal RST_TIME : std_logic_vector(19 downto 0) := X"7A120";
92
93signal par_addr : std_logic_vector (9 downto 0) := (OTHERS => '0');
94signal par_data : std_logic_vector (15 downto 0) := (OTHERS => '0');
95signal data_read : std_logic_vector (15 downto 0) := (OTHERS => '0');
96signal adc_data_addr : std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
97
98signal state_init, next_state , next_state_tmp : state_init_type := RESET;
99signal count : std_logic_vector (2 downto 0) := "000";
100signal state_write : state_write_type := WR_START;
101signal state_interrupt_1 : state_interrupt_1_type := IR1_01;
102signal state_interrupt_2 : state_interrupt_2_type := IR2_01;
103signal state_read_data : state_read_data_type := RD_1;
104
105signal interrupt_ignore : std_logic := '1';
106signal int_flag : std_logic := '0';
107signal ram_access : std_logic := '0';
108
109signal zaehler : std_logic_vector (19 downto 0) := (OTHERS => '0');
110signal data_cnt : integer := 0;
111signal drs_cnt : integer :=0;
112signal channel_cnt : integer range 0 to 9 :=0;
113signal socket_cnt : std_logic_vector (2 downto 0) := "000";
114signal roi_max : std_logic_vector (10 downto 0);
115signal data_end : integer := 0;
116
117signal socket_tx_free : std_logic_vector (31 downto 0) := (others => '0');
118signal write_length_bytes : std_logic_vector (16 downto 0);
119
120signal socket_rx_received : std_logic_vector (31 downto 0) := (others => '0');
121signal chk_recv_cntr : integer range 0 to 10000 := 0;
122signal rx_packets_cnt : std_logic_vector (15 downto 0);
123signal next_packet_data : std_logic := '0';
124signal new_config_flag : std_logic := '0';
125
126signal trigger_stop : std_logic := '1';
127
128signal local_write_length : std_logic_vector (16 DOWNTO 0);
129signal local_ram_start_addr : std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
130signal local_ram_addr : std_logic_vector (RAM_ADDR_WIDTH-1 downto 0);
131signal local_socket_nr : std_logic_vector (2 DOWNTO 0);
132signal local_write_header_flag, local_write_end_flag : std_logic;
133signal local_fifo_channels : std_logic_vector (3 downto 0);
134
135begin
136
137 --synthesis translate_off
138 RST_TIME <= X"00120";
139 --synthesis translate_on
140
141 w5300_init_proc : process (clk, int)
142 begin
143
144 if rising_edge (clk) then
145
146 -- Interrupt low
147 if (int = '0') and (interrupt_ignore = '0') then
148 case state_interrupt_1 is
149 when IR1_01 =>
150 int_flag <= '1';
151 busy <= '1';
152 state_interrupt_1 <= IR1_02;
153 when IR1_02 =>
154 state_interrupt_1 <= IR1_03;
155 when IR1_03 =>
156 state_init <= INTERRUPT;
157 socket_cnt <= "000";
158 ram_access <= '0';
159 zaehler <= X"00000";
160 count <= "000";
161 int_flag <= '0';
162 interrupt_ignore <= '1';
163 state_interrupt_1 <= IR1_04;
164 when others =>
165 null;
166 end case;
167 end if; -- int = '0'
168
169 if int_flag = '0' then
170 case state_init is
171 -- Interrupt
172 when INTERRUPT =>
173 case state_interrupt_2 is
174 when IR2_01 =>
175 par_addr <= W5300_IR;
176 state_init <= READ_REG;
177 next_state <= INTERRUPT;
178 state_interrupt_2 <= IR2_02;
179 when IR2_02 =>
180 if (data_read (conv_integer(socket_cnt)) = '1') then -- Sx Interrupt
181 state_interrupt_2 <= IR2_03;
182 else
183 socket_cnt <= socket_cnt + 1;
184 if (socket_cnt = 7) then
185 state_interrupt_2 <= IR2_06;
186 else
187 state_interrupt_2 <= IR2_02;
188 end if;
189 end if;
190 when IR2_03 =>
191 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; -- Sx Interrupt Register
192 state_init <= READ_REG;
193 next_state <= INTERRUPT;
194 state_interrupt_2 <= IR2_04;
195 when IR2_04 =>
196 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC;
197 par_data <= data_read; -- clear Interrupts
198 state_init <= WRITE_REG;
199 next_state <= INTERRUPT;
200 state_interrupt_2 <= IR2_05;
201 when IR2_05 =>
202 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
203 par_data <= X"0010"; -- CLOSE
204 state_init <= WRITE_REG;
205 next_state <= INTERRUPT;
206 socket_cnt <= socket_cnt + 1;
207 if (socket_cnt = 7) then
208 state_interrupt_2 <= IR2_06;
209 else
210 state_interrupt_2 <= IR2_01;
211 end if;
212
213 when IR2_06 =>
214 state_interrupt_1 <= IR1_01;
215 state_interrupt_2 <= IR2_01;
216 socket_cnt <= "000";
217 state_init <= RESET;
218 end case;
219
220 -- reset W5300
221 when RESET =>
222 zaehler <= zaehler + 1;
223 wiz_reset <= '0';
224 led <= X"FF";
225 if (zaehler >= X"00064") then -- wait 2µs
226 wiz_reset <= '1';
227 end if;
228 if (zaehler = RST_TIME) then -- wait 10ms
229 zaehler <= X"00000";
230 socket_cnt <= "000";
231 count <= "000";
232 ram_access <= '0';
233 interrupt_ignore <= '0';
234 rd <= '1';
235 wr <= '1';
236 cs <= '1';
237 state_write <= WR_START;
238 state_init <= INIT;
239 end if;
240
241 -- Init
242 when INIT =>
243 par_addr <= W5300_MR;
244 par_data <= X"0000";
245 state_init <= WRITE_REG;
246 next_state <= IM;
247
248 -- Interrupt Mask
249 when IM =>
250 par_addr <= W5300_IMR;
251 par_data <= X"00FF"; -- S0-S7 Interrupts
252 state_init <= WRITE_REG;
253 next_state <= MT;
254
255 -- Memory Type
256 when MT =>
257 par_addr <= W5300_MTYPER;
258 par_data <= X"7FFF"; -- 8K RX, 120K TX-Buffer
259 state_init <= WRITE_REG;
260 next_state <= STX;
261
262 -- Socket TX Memory Size
263 when STX =>
264 par_data <= X"0F0F"; -- 15K TX
265
266 par_addr <= W5300_TMS01R;
267 state_init <=WRITE_REG;
268 next_state <= STX1;
269 when STX1 =>
270 par_addr <= W5300_TMS23R;
271 state_init <=WRITE_REG;
272 next_state <= STX2;
273 when STX2 =>
274 par_addr <= W5300_TMS45R;
275 state_init <=WRITE_REG;
276 next_state <= STX3;
277 when STX3 =>
278 par_addr <= W5300_TMS67R;
279 state_init <=WRITE_REG;
280 next_state <= SRX;
281
282 -- Socket RX Memory Size
283 when SRX =>
284 par_data <= X"0101"; -- 1K RX
285
286 par_addr <= W5300_RMS01R;
287 state_init <=WRITE_REG;
288 next_state <= SRX1;
289 when SRX1 =>
290 par_addr <= W5300_RMS23R;
291 state_init <=WRITE_REG;
292 next_state <= SRX2;
293 when SRX2 =>
294 par_addr <= W5300_RMS45R;
295 state_init <=WRITE_REG;
296 next_state <= SRX3;
297 when SRX3 =>
298 par_addr <= W5300_RMS67R;
299 state_init <=WRITE_REG;
300 next_state <= MAC;
301
302 -- MAC
303 when MAC =>
304 par_addr <= W5300_SHAR;
305 par_data <= MAC_ADDRESS (0);
306 state_init <= WRITE_REG;
307 next_state <= MAC1;
308 when MAC1 =>
309 par_addr <= W5300_SHAR + 2;
310 par_data <= MAC_ADDRESS (1);
311 state_init <= WRITE_REG;
312 next_state <= MAC2;
313 when MAC2 =>
314 par_addr <= W5300_SHAR + 4;
315 par_data <= MAC_ADDRESS (2);
316 state_init <= WRITE_REG;
317 next_state <= GW;
318
319 -- Gateway
320 when GW =>
321 par_addr <= W5300_GAR;
322 par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (0),8);
323 par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (1),8);
324 state_init <= WRITE_REG;
325 next_state <= GW1;
326 when GW1 =>
327 par_addr <= W5300_GAR + 2;
328 par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (2),8);
329 par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (3),8);
330 state_init <= WRITE_REG;
331 next_state <= SNM;
332
333 -- Subnet Mask
334 when SNM =>
335 par_addr <= W5300_SUBR;
336 par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (0),8);
337 par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (1),8);
338 state_init <= WRITE_REG;
339 next_state <= SNM1;
340 when SNM1 =>
341 par_addr <= W5300_SUBR + 2;
342 par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (2),8);
343 par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (3),8);
344 state_init <= WRITE_REG;
345 next_state <= IP;
346 -- Own IP-Address
347 when IP =>
348 par_addr <= W5300_SIPR;
349 par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (0),8);
350 par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (1),8);
351 state_init <= WRITE_REG;
352 next_state <= IP1;
353 when IP1 =>
354 par_addr <= W5300_SIPR + 2;
355 par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (2),8);
356 par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (3),8);
357 state_init <= WRITE_REG;
358 next_state <= TIMEOUT;
359 when TIMEOUT =>
360 par_addr <= W5300_RTR;
361 par_data <= X"07D0"; -- 0x07D0 = 200ms
362 state_init <= WRITE_REG;
363 next_state <= RETRY;
364 when RETRY =>
365 par_addr <= W5300_RCR;
366 par_data <= X"0008";
367 state_init <= WRITE_REG;
368 next_state <= SI;
369
370 -- Socket Init
371 when SI =>
372 par_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC;
373 par_data <= X"0101"; -- ALIGN, TCP
374 state_init <= WRITE_REG;
375 next_state <= SI1;
376 -- Sx Interrupt Mask
377 when SI1 =>
378 par_addr <= W5300_S0_IMR + socket_cnt * W5300_S_INC;
379 par_data <= X"000A"; -- TIMEOUT, DISCON
380 state_init <= WRITE_REG;
381 next_state <= SI2;
382 when SI2 =>
383 par_addr <= W5300_S0_PORTR + socket_cnt * W5300_S_INC;
384 par_data <= conv_std_logic_vector(FIRST_PORT + unsigned (socket_cnt), 16);
385 state_init <= WRITE_REG;
386 next_state <= SI3;
387 when SI3 =>
388 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
389 par_data <= X"0001"; -- OPEN
390 state_init <= WRITE_REG;
391 next_state <= SI4;
392 when SI4 =>
393 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
394 state_init <= READ_REG;
395 next_state <= SI5;
396 when SI5 =>
397 if (data_read (7 downto 0) = X"13") then -- is open?
398 state_init <= SI6;
399 else
400 state_init <= SI4;
401 end if;
402 when SI6 =>
403 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
404 par_data <= X"0002"; -- LISTEN
405 state_init <= WRITE_REG;
406 socket_cnt <= socket_cnt + 1;
407 if (socket_cnt = 7) then
408 socket_cnt <= "000";
409 next_state <= ESTABLISH; -- All Sockets open
410 else
411 next_state <= SI; -- Next Socket
412 end if;
413 -- End Socket Init
414
415 when ESTABLISH =>
416 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
417 state_init <= READ_REG;
418 next_state <= EST1;
419 when EST1 =>
420 led <= data_read (7 downto 0);
421 case data_read (7 downto 0) is
422 when X"17" => -- established
423 if (socket_cnt = 7) then
424 socket_cnt <= "000";
425 busy <= '0';
426 state_init <= MAIN;
427 else
428 socket_cnt <= socket_cnt + 1;
429 state_init <= ESTABLISH;
430 end if;
431 when others =>
432 state_init <= ESTABLISH;
433 end case;
434
435 when CONFIG =>
436 led <= X"F0";
437 new_config <= '1';
438 if (config_started = '1') then
439 led <= X"0F";
440 new_config <= '0';
441 busy <= '0';
442 state_init <= MAIN;
443 end if;
444
445 -- main "loop"
446 when MAIN =>
447 ps_do_phase_shift <= '0';
448 ps_reset <= '0';
449 if (trigger_stop = '1') then
450 s_trigger <= '0';
451 end if;
452 if (chk_recv_cntr = 1000) then
453 chk_recv_cntr <= 0;
454 state_read_data <= RD_1;
455 state_init <= READ_DATA;
456 busy <= '1';
457 else
458 busy <= '0';
459 data_valid_ack <= '0';
460 chk_recv_cntr <= chk_recv_cntr + 1;
461 if (data_valid = '1') then
462 data_valid_ack <= '1';
463 local_write_length <= write_length;
464 local_ram_start_addr <= ram_start_addr;
465 local_ram_addr <= (others => '0');
466 local_write_header_flag <= write_header_flag;
467 local_write_end_flag <= write_end_flag;
468 local_fifo_channels <= fifo_channels;
469 next_state <= MAIN;
470 state_init <= WRITE_DATA;
471 busy <= '1';
472 end if;
473 end if;
474
475 -- read data from socket 0
476 when READ_DATA =>
477 case state_read_data is
478 when RD_1 =>
479 par_addr <= W5300_S0_RX_RSR;
480 state_init <= READ_REG;
481 next_state <= READ_DATA;
482 state_read_data <= RD_2;
483 when RD_2 =>
484 socket_rx_received (31 downto 16) <= data_read;
485 par_addr <= W5300_S0_RX_RSR + X"2";
486 state_init <= READ_REG;
487 next_state <= READ_DATA;
488 state_read_data <= RD_3;
489 when RD_3 =>
490 socket_rx_received (15 downto 0) <= data_read;
491 state_read_data <= RD_4;
492 when RD_4 =>
493 if (socket_rx_received (16 downto 0) > ('0' & X"000")) then
494 rx_packets_cnt <= socket_rx_received (16 downto 1); -- socket_rx_received / 2
495 state_read_data <= RD_5;
496 else
497 busy <= '0';
498 state_init <= MAIN;
499 end if;
500 when RD_5 =>
501 if (rx_packets_cnt > 0) then
502 rx_packets_cnt <= rx_packets_cnt - '1';
503 par_addr <= W5300_S0_RX_FIFOR;
504 state_init <= READ_REG;
505 next_state <= READ_DATA;
506 state_read_data <= RD_6;
507 else
508 state_read_data <= RD_END;
509-- if (new_config_flag = '1') then
510-- new_config_flag <= '0';
511-- state_init <= CONFIG;
512-- else
513-- busy <= '0';
514-- state_init <= MAIN;
515-- end if;
516 end if;
517 when RD_6 =>
518 led <= data_read (15 downto 8);
519 -- read command
520 if (next_packet_data = '0') then
521 case data_read (15 downto 8) is
522 when CMD_TRIGGER =>
523 trigger_stop <= '1';
524 s_trigger <= '1';
525 state_read_data <= RD_WAIT;
526 when CMD_DWRITE_RUN =>
527 dwrite_enable <= '1';
528 state_read_data <= RD_WAIT;
529 when CMD_DWRITE_STOP =>
530 dwrite_enable <= '0';
531 state_read_data <= RD_WAIT;
532 when CMD_SCLK_ON =>
533 sclk_enable <= '1';
534 state_read_data <= RD_WAIT;
535 when CMD_SCLK_OFF =>
536 sclk_enable <= '0';
537 state_read_data <= RD_WAIT;
538 when CMD_DENABLE =>
539 denable <= '1';
540 state_read_data <= RD_WAIT;
541 when CMD_DDISABLE =>
542 denable <= '0';
543 state_read_data <= RD_WAIT;
544 when CMD_TRIGGER_C =>
545 trigger_stop <= '0';
546 s_trigger <= '1';
547 state_read_data <= RD_WAIT;
548 when CMD_TRIGGER_S =>
549 trigger_stop <= '1';
550 state_read_data <= RD_WAIT;
551 -- phase shift commands here:
552 when CMD_PS_DO =>
553 ps_do_phase_shift <= '1';
554 state_read_data <= RD_WAIT;
555 when CMD_PS_DIRINC =>
556 ps_direction <= '1';
557 state_read_data <= RD_WAIT;
558 when CMD_PS_RESET =>
559 ps_reset <= '1';
560 state_read_data <= RD_WAIT;
561 when CMD_SRCLK_ON =>
562 srclk_enable <= '1';
563 state_read_data <= RD_WAIT;
564 when CMD_SRCLK_OFF =>
565 srclk_enable <= '0';
566 state_read_data <= RD_WAIT;
567 when CMD_PS_DIRDEC =>
568 ps_direction <= '0';
569 state_read_data <= RD_WAIT;
570 when CMD_WRITE =>
571 next_packet_data <= '1';
572 config_addr <= data_read (7 downto 0);
573 state_read_data <= RD_5;
574 when others =>
575 state_read_data <= RD_5;
576 end case;
577 -- read data
578 else
579 if (config_busy = '0') then
580 config_data <= data_read;
581 config_wr_en <= '1';
582 new_config_flag <= '1';
583 next_packet_data <= '0';
584 state_read_data <= RD_WAIT;
585 end if;
586 end if;
587 when RD_WAIT =>
588 state_read_data <= RD_WAIT1;
589 when RD_WAIT1 =>
590 config_data <= (others => 'Z');
591 config_wr_en <= '0';
592 state_read_data <= RD_5;
593 when RD_END =>
594 par_addr <= W5300_S0_CR;
595 par_data <= X"0040"; -- RECV
596 state_init <= WRITE_REG;
597 if (new_config_flag = '1') then
598 new_config_flag <= '0';
599 next_state <= CONFIG;
600 else
601-- busy <= '0';
602 next_state <= MAIN;
603 end if;
604
605 end case; -- state_data_read
606
607
608
609 when WRITE_DATA =>
610 case state_write is
611 when WR_START =>
612 if (local_write_header_flag = '1') then
613 ram_addr <= local_ram_start_addr + 5; -- Address of Trigger-ID (15 downto 0) ????
614 end if;
615 state_write <= WR_WAIT1;
616 when WR_WAIT1 =>
617 state_write <= WR_LENGTH;
618 when WR_LENGTH =>
619 if (local_write_header_flag = '1') then
620 local_socket_nr <= ram_data (2 downto 0);
621 end if;
622 next_state_tmp <= next_state;
623 write_length_bytes <= local_write_length (15 downto 0) & '0'; -- shift left (*2)
624 data_cnt <= 0;
625 state_write <= WR_01;
626 -- Check FIFO Size
627 when WR_01 =>
628 par_addr <= W5300_S0_TX_FSR + local_socket_nr * W5300_S_INC;
629 state_init <= READ_REG;
630 next_state <= WRITE_DATA;
631 state_write <= WR_02;
632 when WR_02 =>
633 socket_tx_free (31 downto 16) <= data_read;
634 par_addr <= W5300_S0_TX_FSR + (local_socket_nr * W5300_S_INC) + X"2";
635 state_init <= READ_REG;
636 next_state <= WRITE_DATA;
637 state_write <= WR_03;
638 when WR_03 =>
639 socket_tx_free (15 downto 0) <= data_read;
640 state_write <= WR_04;
641 when WR_04 =>
642 if (socket_tx_free (16 downto 0) < write_length_bytes) then
643 state_write <= WR_01;
644 else
645 if (local_write_header_flag = '1') then
646 state_write <= WR_FIFO;
647 else
648 state_write <= WR_ADC;
649 end if;
650 end if;
651
652 -- Fill FIFO
653
654 -- Write Header
655 when WR_FIFO =>
656 ram_addr <= local_ram_start_addr + local_ram_addr;
657 state_write <= WR_FIFO1;
658 when WR_FIFO1 =>
659 data_cnt <= data_cnt + 1;
660 if (data_cnt < PACKAGE_HEADER_LENGTH) then --???
661 local_ram_addr <= local_ram_addr + 1;
662 if (data_cnt = 2 or data_cnt = 5 or data_cnt = 8 ) then -- skip empty words
663 local_ram_addr <= local_ram_addr + 2;
664 end if;
665 if (data_cnt = 9) then -- skip empty words
666 local_ram_addr <= local_ram_addr + 4;
667 end if;
668 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
669 ram_access <= '1';
670 state_init <= WRITE_REG;
671 next_state <= WRITE_DATA;
672 state_write <= WR_FIFO;
673 else
674 state_write <= WR_ADC;
675 end if;
676 -- End Write Header
677
678 -- Write ADC-Data
679 ---- Start...
680 when WR_ADC =>
681 adc_data_addr <= local_ram_start_addr + local_ram_addr;
682 drs_cnt <= 0;
683 channel_cnt <= 1;
684 data_cnt <= 0;
685 roi_max <= (others => '0');
686 data_end <= 3;
687 state_write <= WR_ADC1;
688
689 ---- Write Channel
690 when WR_ADC1 =>
691 -- read ROI and set end of Channel-Data
692 if (data_cnt = 3) then
693 data_end <= conv_integer (ram_data) + 3;
694 if (ram_data > roi_max) then
695 roi_max <= ram_data (10 downto 0);
696 end if;
697 end if;
698 ram_addr <= adc_data_addr + drs_cnt + (data_cnt * 4);
699 state_write <= WR_ADC2;
700 when WR_ADC2 =>
701 if (data_cnt < data_end) then
702 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
703 ram_access <= '1';
704 state_init <= WRITE_REG;
705 next_state <= WRITE_DATA;
706 data_cnt <= data_cnt + 1;
707 state_write <= WR_ADC1;
708 else
709 -- Next DRS
710 if (drs_cnt < 3) then
711 drs_cnt <= drs_cnt + 1;
712 data_cnt <= 0;
713 data_end <= 3;
714 state_write <= WR_ADC1;
715 else
716 -- Next Channel
717 if (channel_cnt < local_fifo_channels) then
718 channel_cnt <= channel_cnt + 1;
719 roi_max <= (others => '0');
720 drs_cnt <= 0;
721 data_cnt <= 0;
722 data_end <= 3;
723 adc_data_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4);
724 state_write <= WR_ADC1;
725 else
726 -- Ready
727 if (local_write_end_flag = '1') then
728 state_write <= WR_ENDFLAG;
729 else
730 state_write <= WR_05;
731 end if;
732 end if;
733 end if;
734 end if;
735 -- End Write ADC-Data
736
737 -- Write End Package Flag
738 when WR_ENDFLAG =>
739 ram_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4);
740 state_write <= WR_ENDFLAG1;
741 when WR_ENDFLAG1 =>
742 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
743 ram_access <= '1';
744 state_init <= WRITE_REG;
745 next_state <= WRITE_DATA;
746 state_write <= WR_ENDFLAG2;
747 when WR_ENDFLAG2 =>
748 ram_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4) + 1;
749 state_write <= WR_ENDFLAG3;
750 when WR_ENDFLAG3 =>
751 state_init <= WRITE_REG;
752 next_state <= WRITE_DATA;
753 state_write <= WR_05;
754
755 -- End Write End Package Flag
756
757 --Send FIFO
758 when WR_05 =>
759 ram_access <= '0';
760 par_addr <= W5300_S0_TX_WRSR + local_socket_nr * W5300_S_INC;
761 par_data <= (0 => write_length_bytes (16), others => '0');
762 state_init <= WRITE_REG;
763 state_write <= WR_06;
764 when WR_06 =>
765 par_addr <= W5300_S0_TX_WRSR + (local_socket_nr * W5300_S_INC) + X"2";
766 par_data <= write_length_bytes (15 downto 0);
767 state_init <= WRITE_REG;
768 state_write <= WR_07;
769 when WR_07 =>
770 par_addr <= W5300_S0_CR + local_socket_nr * W5300_S_INC;
771 par_data <= X"0020"; -- Send
772 state_init <= WRITE_REG;
773 state_write <= WR_08;
774 when others =>
775-- busy <= '0';
776 state_init <= next_state_tmp;
777 state_write <= WR_START;
778 end case;
779 -- End WRITE_DATA
780
781 when READ_REG =>
782 case count is
783 when "000" =>
784 cs <= '0';
785 rd <= '0';
786 wr <= '1';
787 data <= (others => 'Z'); -- !!!!!!!!!!
788 count <= "001";
789 addr <= par_addr;
790 when "001" =>
791 count <= "010";
792 when "010" =>
793 count <= "100";
794 when "100" =>
795 data_read <= data;
796 count <= "110";
797 when "110" =>
798 count <= "111";
799 when "111" =>
800 cs <= '1';
801 rd <= '1';
802 count <= "000";
803 state_init <= next_state;
804 when others =>
805 null;
806 end case;
807
808 when WRITE_REG =>
809 case count is
810 when "000" =>
811 cs <= '0';
812 wr <= '0';
813 rd <= '1';
814 addr <= par_addr;
815 if (ram_access = '1') then
816 data <= ram_data;
817 else
818 data <= par_data;
819 end if;
820 count <= "100";
821 when "100" =>
822 count <= "101";
823 when "101" =>
824 count <= "110";
825 when "110" =>
826 cs <= '1';
827 wr <= '1';
828 state_init <= next_state;
829 count <= "000";
830 when others =>
831 null;
832 end case;
833
834 when others =>
835 null;
836 end case;
837 end if; -- int_flag = '0'
838
839 end if; -- rising_edge (clk)
840
841 end process w5300_init_proc;
842
843end Behavioral;
844
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