source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd @ 10729

Last change on this file since 10729 was 10729, checked in by neise, 9 years ago
File size: 147.4 KB
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1008xt "93000,68500,95400,69500"
1009st "W_D"
1010blo "93000,69300"
1011tm "WireNameMgr"
1012)
1013)
1014)
1015*24 (PortIoIn
1016uid 496,0
1017shape (CompositeShape
1018uid 497,0
1019va (VaSet
1020vasetType 1
1021fg "0,0,32768"
1022)
1023optionalChildren [
1024(Pentagon
1025uid 498,0
1026sl 0
1027ro 90
1028xt "90500,73625,92000,74375"
1029)
1030(Line
1031uid 499,0
1032sl 0
1033ro 90
1034xt "90000,74000,90500,74000"
1035pts [
1036"90500,74000"
1037"90000,74000"
1038]
1039)
1040]
1041)
1042stc 0
1043sf 1
1044tg (WTG
1045uid 500,0
1046ps "PortIoTextPlaceStrategy"
1047stg "STSignalDisplayStrategy"
1048f (Text
1049uid 501,0
1050va (VaSet
1051)
1052xt "93000,73500,96300,74500"
1053st "W_INT"
1054blo "93000,74300"
1055tm "WireNameMgr"
1056)
1057)
1058)
1059*25 (PortIoOut
1060uid 502,0
1061shape (CompositeShape
1062uid 503,0
1063va (VaSet
1064vasetType 1
1065fg "0,0,32768"
1066)
1067optionalChildren [
1068(Pentagon
1069uid 504,0
1070sl 0
1071ro 270
1072xt "90500,71625,92000,72375"
1073)
1074(Line
1075uid 505,0
1076sl 0
1077ro 270
1078xt "90000,72000,90500,72000"
1079pts [
1080"90000,72000"
1081"90500,72000"
1082]
1083)
1084]
1085)
1086stc 0
1087sf 1
1088tg (WTG
1089uid 506,0
1090ps "PortIoTextPlaceStrategy"
1091stg "STSignalDisplayStrategy"
1092f (Text
1093uid 507,0
1094va (VaSet
1095)
1096xt "93000,71500,95900,72500"
1097st "W_RD"
1098blo "93000,72300"
1099tm "WireNameMgr"
1100)
1101)
1102)
1103*26 (PortIoOut
1104uid 508,0
1105shape (CompositeShape
1106uid 509,0
1107va (VaSet
1108vasetType 1
1109fg "0,0,32768"
1110)
1111optionalChildren [
1112(Pentagon
1113uid 510,0
1114sl 0
1115ro 270
1116xt "90500,72625,92000,73375"
1117)
1118(Line
1119uid 511,0
1120sl 0
1121ro 270
1122xt "90000,73000,90500,73000"
1123pts [
1124"90000,73000"
1125"90500,73000"
1126]
1127)
1128]
1129)
1130stc 0
1131sf 1
1132tg (WTG
1133uid 512,0
1134ps "PortIoTextPlaceStrategy"
1135stg "STSignalDisplayStrategy"
1136f (Text
1137uid 513,0
1138va (VaSet
1139)
1140xt "93000,72500,96200,73500"
1141st "W_WR"
1142blo "93000,73300"
1143tm "WireNameMgr"
1144)
1145)
1146)
1147*27 (Net
1148uid 1465,0
1149decl (Decl
1150n "adc_data_array"
1151t "adc_data_array_type"
1152o 72
1153suid 29,0
1154)
1155declText (MLText
1156uid 1466,0
1157va (VaSet
1158font "Courier New,8,0"
1159)
1160xt "39000,48800,66000,49600"
1161st "SIGNAL adc_data_array        : adc_data_array_type
1162"
1163)
1164)
1165*28 (Net
1166uid 2407,0
1167decl (Decl
1168n "RSRLOAD"
1169t "std_logic"
1170o 43
1171suid 57,0
1172i "'0'"
1173)
1174declText (MLText
1175uid 2408,0
1176va (VaSet
1177font "Courier New,8,0"
1178)
1179xt "39000,35800,71000,36600"
1180st "RSRLOAD               : std_logic                     := '0'
1181"
1182)
1183)
1184*29 (PortIoOut
1185uid 2415,0
1186shape (CompositeShape
1187uid 2416,0
1188va (VaSet
1189vasetType 1
1190fg "0,0,32768"
1191)
1192optionalChildren [
1193(Pentagon
1194uid 2417,0
1195sl 0
1196ro 90
1197xt "19000,110625,20500,111375"
1198)
1199(Line
1200uid 2418,0
1201sl 0
1202ro 90
1203xt "20500,111000,21000,111000"
1204pts [
1205"21000,111000"
1206"20500,111000"
1207]
1208)
1209]
1210)
1211stc 0
1212sf 1
1213tg (WTG
1214uid 2419,0
1215ps "PortIoTextPlaceStrategy"
1216stg "STSignalDisplayStrategy"
1217f (Text
1218uid 2420,0
1219va (VaSet
1220)
1221xt "13800,110500,18000,111500"
1222st "RSRLOAD"
1223ju 2
1224blo "18000,111300"
1225tm "WireNameMgr"
1226)
1227)
1228)
1229*30 (Net
1230uid 3025,0
1231decl (Decl
1232n "DAC_CS"
1233t "std_logic"
1234o 26
1235suid 66,0
1236)
1237declText (MLText
1238uid 3026,0
1239va (VaSet
1240font "Courier New,8,0"
1241)
1242xt "39000,21400,57000,22200"
1243st "DAC_CS                : std_logic
1244"
1245)
1246)
1247*31 (PortIoOut
1248uid 3153,0
1249shape (CompositeShape
1250uid 3154,0
1251va (VaSet
1252vasetType 1
1253fg "0,0,32768"
1254)
1255optionalChildren [
1256(Pentagon
1257uid 3155,0
1258sl 0
1259ro 90
1260xt "-3000,70625,-1500,71375"
1261)
1262(Line
1263uid 3156,0
1264sl 0
1265ro 90
1266xt "-1500,71000,-1000,71000"
1267pts [
1268"-1000,71000"
1269"-1500,71000"
1270]
1271)
1272]
1273)
1274stc 0
1275sf 1
1276tg (WTG
1277uid 3157,0
1278ps "PortIoTextPlaceStrategy"
1279stg "STSignalDisplayStrategy"
1280f (Text
1281uid 3158,0
1282va (VaSet
1283)
1284xt "-6900,70500,-4000,71500"
1285st "A_CLK"
1286ju 2
1287blo "-4000,71300"
1288tm "WireNameMgr"
1289)
1290)
1291)
1292*32 (Net
1293uid 3216,0
1294decl (Decl
1295n "X_50M"
1296t "STD_LOGIC"
1297preAdd 0
1298posAdd 0
1299o 17
1300suid 67,0
1301)
1302declText (MLText
1303uid 3217,0
1304va (VaSet
1305font "Courier New,8,0"
1306)
1307xt "39000,17400,57000,18200"
1308st "X_50M                 : STD_LOGIC
1309"
1310)
1311)
1312*33 (Net
1313uid 3226,0
1314decl (Decl
1315n "TRG"
1316t "STD_LOGIC"
1317o 15
1318suid 68,0
1319)
1320declText (MLText
1321uid 3227,0
1322va (VaSet
1323font "Courier New,8,0"
1324)
1325xt "39000,15800,57000,16600"
1326st "TRG                   : STD_LOGIC
1327"
1328)
1329)
1330*34 (HdlText
1331uid 3248,0
1332optionalChildren [
1333*35 (EmbeddedText
1334uid 3254,0
1335commentText (CommentText
1336uid 3255,0
1337ps "CenterOffsetStrategy"
1338shape (Rectangle
1339uid 3256,0
1340va (VaSet
1341vasetType 1
1342fg "65535,65535,65535"
1343lineColor "0,0,32768"
1344lineWidth 2
1345)
1346xt "-14000,63000,12000,69000"
1347)
1348oxt "0,0,18000,5000"
1349text (MLText
1350uid 3257,0
1351va (VaSet
1352)
1353xt "-13800,63200,-9000,69200"
1354st "
1355A_CLK <= (
1356ADC_CLK,
1357ADC_CLK,
1358ADC_CLK,
1359ADC_CLK
1360);
1361
1362"
1363tm "HdlTextMgr"
1364wrapOption 3
1365visibleHeight 6000
1366visibleWidth 26000
1367)
1368)
1369)
1370]
1371shape (Rectangle
1372uid 3249,0
1373va (VaSet
1374vasetType 1
1375fg "65535,65535,37120"
1376lineColor "0,0,32768"
1377lineWidth 2
1378)
1379xt "5000,70000,13000,73000"
1380)
1381oxt "0,0,8000,10000"
1382ttg (MlTextGroup
1383uid 3250,0
1384ps "CenterOffsetStrategy"
1385stg "VerticalLayoutStrategy"
1386textVec [
1387*36 (Text
1388uid 3251,0
1389va (VaSet
1390font "Arial,8,1"
1391)
1392xt "6150,70000,10350,71000"
1393st "ADC_CLK"
1394blo "6150,70800"
1395tm "HdlTextNameMgr"
1396)
1397*37 (Text
1398uid 3252,0
1399va (VaSet
1400font "Arial,8,1"
1401)
1402xt "6150,71000,6950,72000"
1403st "2"
1404blo "6150,71800"
1405tm "HdlTextNumberMgr"
1406)
1407]
1408)
1409viewicon (ZoomableIcon
1410uid 3253,0
1411sl 0
1412va (VaSet
1413vasetType 1
1414fg "49152,49152,49152"
1415)
1416xt "5250,71250,6750,72750"
1417iconName "TextFile.png"
1418iconMaskName "TextFile.msk"
1419ftype 21
1420)
1421viewiconposition 0
1422)
1423*38 (Net
1424uid 3266,0
1425decl (Decl
1426n "A_CLK"
1427t "std_logic_vector"
1428b "(3 downto 0)"
1429o 21
1430suid 71,0
1431)
1432declText (MLText
1433uid 3267,0
1434va (VaSet
1435font "Courier New,8,0"
1436)
1437xt "39000,20600,67000,21400"
1438st "A_CLK                 : std_logic_vector(3 downto 0)
1439"
1440)
1441)
1442*39 (PortIoOut
1443uid 3284,0
1444shape (CompositeShape
1445uid 3285,0
1446va (VaSet
1447vasetType 1
1448fg "0,0,32768"
1449)
1450optionalChildren [
1451(Pentagon
1452uid 3286,0
1453sl 0
1454ro 90
1455xt "19000,89625,20500,90375"
1456)
1457(Line
1458uid 3287,0
1459sl 0
1460ro 90
1461xt "20500,90000,21000,90000"
1462pts [
1463"21000,90000"
1464"20500,90000"
1465]
1466)
1467]
1468)
1469stc 0
1470sf 1
1471tg (WTG
1472uid 3288,0
1473ps "PortIoTextPlaceStrategy"
1474stg "STSignalDisplayStrategy"
1475f (Text
1476uid 3289,0
1477va (VaSet
1478)
1479xt "14300,89500,18000,90500"
1480st "OE_ADC"
1481ju 2
1482blo "18000,90300"
1483tm "WireNameMgr"
1484)
1485)
1486)
1487*40 (Net
1488uid 3290,0
1489decl (Decl
1490n "OE_ADC"
1491t "STD_LOGIC"
1492preAdd 0
1493posAdd 0
1494o 35
1495suid 73,0
1496)
1497declText (MLText
1498uid 3291,0
1499va (VaSet
1500font "Courier New,8,0"
1501)
1502xt "39000,29400,57000,30200"
1503st "OE_ADC                : STD_LOGIC
1504"
1505)
1506)
1507*41 (PortIoIn
1508uid 3292,0
1509shape (CompositeShape
1510uid 3293,0
1511va (VaSet
1512vasetType 1
1513fg "0,0,32768"
1514)
1515optionalChildren [
1516(Pentagon
1517uid 3294,0
1518sl 0
1519ro 270
1520xt "19000,88625,20500,89375"
1521)
1522(Line
1523uid 3295,0
1524sl 0
1525ro 270
1526xt "20500,89000,21000,89000"
1527pts [
1528"20500,89000"
1529"21000,89000"
1530]
1531)
1532]
1533)
1534stc 0
1535sf 1
1536tg (WTG
1537uid 3296,0
1538ps "PortIoTextPlaceStrategy"
1539stg "STSignalDisplayStrategy"
1540f (Text
1541uid 3297,0
1542va (VaSet
1543)
1544xt "14900,88500,18000,89500"
1545st "A_OTR"
1546ju 2
1547blo "18000,89300"
1548tm "WireNameMgr"
1549)
1550)
1551)
1552*42 (Net
1553uid 3298,0
1554decl (Decl
1555n "A_OTR"
1556t "std_logic_vector"
1557b "(3 DOWNTO 0)"
1558o 5
1559suid 74,0
1560)
1561declText (MLText
1562uid 3299,0
1563va (VaSet
1564font "Courier New,8,0"
1565)
1566xt "39000,7000,67000,7800"
1567st "A_OTR                 : std_logic_vector(3 DOWNTO 0)
1568"
1569)
1570)
1571*43 (HdlText
1572uid 3300,0
1573optionalChildren [
1574*44 (EmbeddedText
1575uid 3306,0
1576commentText (CommentText
1577uid 3307,0
1578ps "CenterOffsetStrategy"
1579shape (Rectangle
1580uid 3308,0
1581va (VaSet
1582vasetType 1
1583fg "65535,65535,65535"
1584lineColor "0,0,32768"
1585lineWidth 2
1586)
1587xt "19000,99000,38000,101000"
1588)
1589oxt "0,0,18000,5000"
1590text (MLText
1591uid 3309,0
1592va (VaSet
1593)
1594xt "19200,99200,35900,101200"
1595st "
1596adc_data_array <= ( A0_D, A1_D, A2_D, A3_D );
1597
1598"
1599tm "HdlTextMgr"
1600wrapOption 3
1601visibleHeight 2000
1602visibleWidth 19000
1603)
1604)
1605)
1606]
1607shape (Rectangle
1608uid 3301,0
1609va (VaSet
1610vasetType 1
1611fg "65535,65535,37120"
1612lineColor "0,0,32768"
1613lineWidth 2
1614)
1615xt "24000,94000,30000,99000"
1616)
1617oxt "0,0,8000,10000"
1618ttg (MlTextGroup
1619uid 3302,0
1620ps "CenterOffsetStrategy"
1621stg "VerticalLayoutStrategy"
1622textVec [
1623*45 (Text
1624uid 3303,0
1625va (VaSet
1626font "Arial,8,1"
1627)
1628xt "27150,95000,31750,96000"
1629st "ADC_DATA"
1630blo "27150,95800"
1631tm "HdlTextNameMgr"
1632)
1633*46 (Text
1634uid 3304,0
1635va (VaSet
1636font "Arial,8,1"
1637)
1638xt "27150,96000,27950,97000"
1639st "3"
1640blo "27150,96800"
1641tm "HdlTextNumberMgr"
1642)
1643]
1644)
1645viewicon (ZoomableIcon
1646uid 3305,0
1647sl 0
1648va (VaSet
1649vasetType 1
1650fg "49152,49152,49152"
1651)
1652xt "24250,97250,25750,98750"
1653iconName "TextFile.png"
1654iconMaskName "TextFile.msk"
1655ftype 21
1656)
1657viewiconposition 0
1658)
1659*47 (PortIoIn
1660uid 3310,0
1661shape (CompositeShape
1662uid 3311,0
1663va (VaSet
1664vasetType 1
1665fg "0,0,32768"
1666)
1667optionalChildren [
1668(Pentagon
1669uid 3312,0
1670sl 0
1671ro 270
1672xt "19000,94625,20500,95375"
1673)
1674(Line
1675uid 3313,0
1676sl 0
1677ro 270
1678xt "20500,95000,21000,95000"
1679pts [
1680"20500,95000"
1681"21000,95000"
1682]
1683)
1684]
1685)
1686stc 0
1687sf 1
1688tg (WTG
1689uid 3314,0
1690ps "PortIoTextPlaceStrategy"
1691stg "STSignalDisplayStrategy"
1692f (Text
1693uid 3315,0
1694va (VaSet
1695)
1696xt "15400,94500,18000,95500"
1697st "A0_D"
1698ju 2
1699blo "18000,95300"
1700tm "WireNameMgr"
1701)
1702)
1703)
1704*48 (PortIoIn
1705uid 3332,0
1706shape (CompositeShape
1707uid 3333,0
1708va (VaSet
1709vasetType 1
1710fg "0,0,32768"
1711)
1712optionalChildren [
1713(Pentagon
1714uid 3334,0
1715sl 0
1716ro 270
1717xt "19000,95625,20500,96375"
1718)
1719(Line
1720uid 3335,0
1721sl 0
1722ro 270
1723xt "20500,96000,21000,96000"
1724pts [
1725"20500,96000"
1726"21000,96000"
1727]
1728)
1729]
1730)
1731stc 0
1732sf 1
1733tg (WTG
1734uid 3336,0
1735ps "PortIoTextPlaceStrategy"
1736stg "STSignalDisplayStrategy"
1737f (Text
1738uid 3337,0
1739va (VaSet
1740)
1741xt "15500,95500,18000,96500"
1742st "A1_D"
1743ju 2
1744blo "18000,96300"
1745tm "WireNameMgr"
1746)
1747)
1748)
1749*49 (PortIoIn
1750uid 3338,0
1751shape (CompositeShape
1752uid 3339,0
1753va (VaSet
1754vasetType 1
1755fg "0,0,32768"
1756)
1757optionalChildren [
1758(Pentagon
1759uid 3340,0
1760sl 0
1761ro 270
1762xt "19000,96625,20500,97375"
1763)
1764(Line
1765uid 3341,0
1766sl 0
1767ro 270
1768xt "20500,97000,21000,97000"
1769pts [
1770"20500,97000"
1771"21000,97000"
1772]
1773)
1774]
1775)
1776stc 0
1777sf 1
1778tg (WTG
1779uid 3342,0
1780ps "PortIoTextPlaceStrategy"
1781stg "STSignalDisplayStrategy"
1782f (Text
1783uid 3343,0
1784va (VaSet
1785)
1786xt "15400,96500,18000,97500"
1787st "A2_D"
1788ju 2
1789blo "18000,97300"
1790tm "WireNameMgr"
1791)
1792)
1793)
1794*50 (PortIoIn
1795uid 3344,0
1796shape (CompositeShape
1797uid 3345,0
1798va (VaSet
1799vasetType 1
1800fg "0,0,32768"
1801)
1802optionalChildren [
1803(Pentagon
1804uid 3346,0
1805sl 0
1806ro 270
1807xt "19000,97625,20500,98375"
1808)
1809(Line
1810uid 3347,0
1811sl 0
1812ro 270
1813xt "20500,98000,21000,98000"
1814pts [
1815"20500,98000"
1816"21000,98000"
1817]
1818)
1819]
1820)
1821stc 0
1822sf 1
1823tg (WTG
1824uid 3348,0
1825ps "PortIoTextPlaceStrategy"
1826stg "STSignalDisplayStrategy"
1827f (Text
1828uid 3349,0
1829va (VaSet
1830)
1831xt "15400,97500,18000,98500"
1832st "A3_D"
1833ju 2
1834blo "18000,98300"
1835tm "WireNameMgr"
1836)
1837)
1838)
1839*51 (Net
1840uid 3374,0
1841decl (Decl
1842n "A0_D"
1843t "std_logic_vector"
1844b "(11 DOWNTO 0)"
1845o 1
1846suid 79,0
1847)
1848declText (MLText
1849uid 3375,0
1850va (VaSet
1851font "Courier New,8,0"
1852)
1853xt "39000,3800,67500,4600"
1854st "A0_D                  : std_logic_vector(11 DOWNTO 0)
1855"
1856)
1857)
1858*52 (Net
1859uid 3376,0
1860decl (Decl
1861n "A1_D"
1862t "std_logic_vector"
1863b "(11 DOWNTO 0)"
1864o 2
1865suid 80,0
1866)
1867declText (MLText
1868uid 3377,0
1869va (VaSet
1870font "Courier New,8,0"
1871)
1872xt "39000,4600,67500,5400"
1873st "A1_D                  : std_logic_vector(11 DOWNTO 0)
1874"
1875)
1876)
1877*53 (Net
1878uid 3378,0
1879decl (Decl
1880n "A2_D"
1881t "std_logic_vector"
1882b "(11 DOWNTO 0)"
1883o 3
1884suid 81,0
1885)
1886declText (MLText
1887uid 3379,0
1888va (VaSet
1889font "Courier New,8,0"
1890)
1891xt "39000,5400,67500,6200"
1892st "A2_D                  : std_logic_vector(11 DOWNTO 0)
1893"
1894)
1895)
1896*54 (Net
1897uid 3380,0
1898decl (Decl
1899n "A3_D"
1900t "std_logic_vector"
1901b "(11 DOWNTO 0)"
1902o 4
1903suid 82,0
1904)
1905declText (MLText
1906uid 3381,0
1907va (VaSet
1908font "Courier New,8,0"
1909)
1910xt "39000,6200,67500,7000"
1911st "A3_D                  : std_logic_vector(11 DOWNTO 0)
1912"
1913)
1914)
1915*55 (PortIoIn
1916uid 3476,0
1917shape (CompositeShape
1918uid 3477,0
1919va (VaSet
1920vasetType 1
1921fg "0,0,32768"
1922)
1923optionalChildren [
1924(Pentagon
1925uid 3478,0
1926sl 0
1927ro 270
1928xt "19000,104625,20500,105375"
1929)
1930(Line
1931uid 3479,0
1932sl 0
1933ro 270
1934xt "20500,105000,21000,105000"
1935pts [
1936"20500,105000"
1937"21000,105000"
1938]
1939)
1940]
1941)
1942stc 0
1943sf 1
1944tg (WTG
1945uid 3480,0
1946ps "PortIoTextPlaceStrategy"
1947stg "STSignalDisplayStrategy"
1948f (Text
1949uid 3481,0
1950va (VaSet
1951)
1952xt "13200,104500,18000,105500"
1953st "D0_SROUT"
1954ju 2
1955blo "18000,105300"
1956tm "WireNameMgr"
1957)
1958)
1959)
1960*56 (PortIoIn
1961uid 3482,0
1962shape (CompositeShape
1963uid 3483,0
1964va (VaSet
1965vasetType 1
1966fg "0,0,32768"
1967)
1968optionalChildren [
1969(Pentagon
1970uid 3484,0
1971sl 0
1972ro 270
1973xt "19000,105625,20500,106375"
1974)
1975(Line
1976uid 3485,0
1977sl 0
1978ro 270
1979xt "20500,106000,21000,106000"
1980pts [
1981"20500,106000"
1982"21000,106000"
1983]
1984)
1985]
1986)
1987stc 0
1988sf 1
1989tg (WTG
1990uid 3486,0
1991ps "PortIoTextPlaceStrategy"
1992stg "STSignalDisplayStrategy"
1993f (Text
1994uid 3487,0
1995va (VaSet
1996)
1997xt "13300,105500,18000,106500"
1998st "D1_SROUT"
1999ju 2
2000blo "18000,106300"
2001tm "WireNameMgr"
2002)
2003)
2004)
2005*57 (PortIoIn
2006uid 3488,0
2007shape (CompositeShape
2008uid 3489,0
2009va (VaSet
2010vasetType 1
2011fg "0,0,32768"
2012)
2013optionalChildren [
2014(Pentagon
2015uid 3490,0
2016sl 0
2017ro 270
2018xt "19000,106625,20500,107375"
2019)
2020(Line
2021uid 3491,0
2022sl 0
2023ro 270
2024xt "20500,107000,21000,107000"
2025pts [
2026"20500,107000"
2027"21000,107000"
2028]
2029)
2030]
2031)
2032stc 0
2033sf 1
2034tg (WTG
2035uid 3492,0
2036ps "PortIoTextPlaceStrategy"
2037stg "STSignalDisplayStrategy"
2038f (Text
2039uid 3493,0
2040va (VaSet
2041)
2042xt "13200,106500,18000,107500"
2043st "D2_SROUT"
2044ju 2
2045blo "18000,107300"
2046tm "WireNameMgr"
2047)
2048)
2049)
2050*58 (PortIoIn
2051uid 3494,0
2052shape (CompositeShape
2053uid 3495,0
2054va (VaSet
2055vasetType 1
2056fg "0,0,32768"
2057)
2058optionalChildren [
2059(Pentagon
2060uid 3496,0
2061sl 0
2062ro 270
2063xt "19000,107625,20500,108375"
2064)
2065(Line
2066uid 3497,0
2067sl 0
2068ro 270
2069xt "20500,108000,21000,108000"
2070pts [
2071"20500,108000"
2072"21000,108000"
2073]
2074)
2075]
2076)
2077stc 0
2078sf 1
2079tg (WTG
2080uid 3498,0
2081ps "PortIoTextPlaceStrategy"
2082stg "STSignalDisplayStrategy"
2083f (Text
2084uid 3499,0
2085va (VaSet
2086)
2087xt "13200,107500,18000,108500"
2088st "D3_SROUT"
2089ju 2
2090blo "18000,108300"
2091tm "WireNameMgr"
2092)
2093)
2094)
2095*59 (Net
2096uid 3500,0
2097decl (Decl
2098n "D0_SROUT"
2099t "std_logic"
2100o 6
2101suid 91,0
2102)
2103declText (MLText
2104uid 3501,0
2105va (VaSet
2106font "Courier New,8,0"
2107)
2108xt "39000,7800,57000,8600"
2109st "D0_SROUT              : std_logic
2110"
2111)
2112)
2113*60 (Net
2114uid 3502,0
2115decl (Decl
2116n "D1_SROUT"
2117t "std_logic"
2118o 7
2119suid 92,0
2120)
2121declText (MLText
2122uid 3503,0
2123va (VaSet
2124font "Courier New,8,0"
2125)
2126xt "39000,8600,57000,9400"
2127st "D1_SROUT              : std_logic
2128"
2129)
2130)
2131*61 (Net
2132uid 3504,0
2133decl (Decl
2134n "D2_SROUT"
2135t "std_logic"
2136o 8
2137suid 93,0
2138)
2139declText (MLText
2140uid 3505,0
2141va (VaSet
2142font "Courier New,8,0"
2143)
2144xt "39000,9400,57000,10200"
2145st "D2_SROUT              : std_logic
2146"
2147)
2148)
2149*62 (Net
2150uid 3506,0
2151decl (Decl
2152n "D3_SROUT"
2153t "std_logic"
2154o 9
2155suid 94,0
2156)
2157declText (MLText
2158uid 3507,0
2159va (VaSet
2160font "Courier New,8,0"
2161)
2162xt "39000,10200,57000,11000"
2163st "D3_SROUT              : std_logic
2164"
2165)
2166)
2167*63 (PortIoOut
2168uid 3508,0
2169shape (CompositeShape
2170uid 3509,0
2171va (VaSet
2172vasetType 1
2173fg "0,0,32768"
2174)
2175optionalChildren [
2176(Pentagon
2177uid 3510,0
2178sl 0
2179ro 90
2180xt "19000,108625,20500,109375"
2181)
2182(Line
2183uid 3511,0
2184sl 0
2185ro 90
2186xt "20500,109000,21000,109000"
2187pts [
2188"21000,109000"
2189"20500,109000"
2190]
2191)
2192]
2193)
2194stc 0
2195sf 1
2196tg (WTG
2197uid 3512,0
2198ps "PortIoTextPlaceStrategy"
2199stg "STSignalDisplayStrategy"
2200f (Text
2201uid 3513,0
2202va (VaSet
2203)
2204xt "15900,108500,18000,109500"
2205st "D_A"
2206ju 2
2207blo "18000,109300"
2208tm "WireNameMgr"
2209)
2210)
2211)
2212*64 (Net
2213uid 3514,0
2214decl (Decl
2215n "D_A"
2216t "std_logic_vector"
2217b "(3 DOWNTO 0)"
2218o 29
2219suid 95,0
2220i "(others => '0')"
2221)
2222declText (MLText
2223uid 3515,0
2224va (VaSet
2225font "Courier New,8,0"
2226)
2227xt "39000,24600,77000,25400"
2228st "D_A                   : std_logic_vector(3 DOWNTO 0)  := (others => '0')
2229"
2230)
2231)
2232*65 (PortIoOut
2233uid 3516,0
2234shape (CompositeShape
2235uid 3517,0
2236va (VaSet
2237vasetType 1
2238fg "0,0,32768"
2239)
2240optionalChildren [
2241(Pentagon
2242uid 3518,0
2243sl 0
2244ro 90
2245xt "19000,109625,20500,110375"
2246)
2247(Line
2248uid 3519,0
2249sl 0
2250ro 90
2251xt "20500,110000,21000,110000"
2252pts [
2253"21000,110000"
2254"20500,110000"
2255]
2256)
2257]
2258)
2259stc 0
2260sf 1
2261tg (WTG
2262uid 3520,0
2263ps "PortIoTextPlaceStrategy"
2264stg "STSignalDisplayStrategy"
2265f (Text
2266uid 3521,0
2267va (VaSet
2268)
2269xt "14200,109500,18000,110500"
2270st "DWRITE"
2271ju 2
2272blo "18000,110300"
2273tm "WireNameMgr"
2274)
2275)
2276)
2277*66 (Net
2278uid 3522,0
2279decl (Decl
2280n "DWRITE"
2281t "std_logic"
2282o 28
2283suid 96,0
2284i "'0'"
2285)
2286declText (MLText
2287uid 3523,0
2288va (VaSet
2289font "Courier New,8,0"
2290)
2291xt "39000,23800,71000,24600"
2292st "DWRITE                : std_logic                     := '0'
2293"
2294)
2295)
2296*67 (PortIoOut
2297uid 3536,0
2298shape (CompositeShape
2299uid 3537,0
2300va (VaSet
2301vasetType 1
2302fg "0,0,32768"
2303)
2304optionalChildren [
2305(Pentagon
2306uid 3538,0
2307sl 0
2308ro 270
2309xt "90500,86625,92000,87375"
2310)
2311(Line
2312uid 3539,0
2313sl 0
2314ro 270
2315xt "90000,87000,90500,87000"
2316pts [
2317"90000,87000"
2318"90500,87000"
2319]
2320)
2321]
2322)
2323stc 0
2324sf 1
2325tg (WTG
2326uid 3540,0
2327ps "PortIoTextPlaceStrategy"
2328stg "STSignalDisplayStrategy"
2329f (Text
2330uid 3541,0
2331va (VaSet
2332)
2333xt "93000,86500,96700,87500"
2334st "DAC_CS"
2335blo "93000,87300"
2336tm "WireNameMgr"
2337)
2338)
2339)
2340*68 (PortIoOut
2341uid 3624,0
2342shape (CompositeShape
2343uid 3625,0
2344va (VaSet
2345vasetType 1
2346fg "0,0,32768"
2347)
2348optionalChildren [
2349(Pentagon
2350uid 3626,0
2351sl 0
2352ro 270
2353xt "90500,97625,92000,98375"
2354)
2355(Line
2356uid 3627,0
2357sl 0
2358ro 270
2359xt "90000,98000,90500,98000"
2360pts [
2361"90000,98000"
2362"90500,98000"
2363]
2364)
2365]
2366)
2367stc 0
2368sf 1
2369tg (WTG
2370uid 3628,0
2371ps "PortIoTextPlaceStrategy"
2372stg "STSignalDisplayStrategy"
2373f (Text
2374uid 3629,0
2375va (VaSet
2376)
2377xt "92750,97500,95650,98500"
2378st "S_CLK"
2379blo "92750,98300"
2380tm "WireNameMgr"
2381)
2382)
2383)
2384*69 (Net
2385uid 3630,0
2386decl (Decl
2387n "S_CLK"
2388t "std_logic"
2389o 45
2390suid 105,0
2391)
2392declText (MLText
2393uid 3631,0
2394va (VaSet
2395font "Courier New,8,0"
2396)
2397xt "39000,37400,57000,38200"
2398st "S_CLK                 : std_logic
2399"
2400)
2401)
2402*70 (Net
2403uid 3632,0
2404decl (Decl
2405n "W_A"
2406t "std_logic_vector"
2407b "(9 DOWNTO 0)"
2408o 51
2409suid 106,0
2410)
2411declText (MLText
2412uid 3633,0
2413va (VaSet
2414font "Courier New,8,0"
2415)
2416xt "39000,39800,67000,40600"
2417st "W_A                   : std_logic_vector(9 DOWNTO 0)
2418"
2419)
2420)
2421*71 (Net
2422uid 3634,0
2423decl (Decl
2424n "W_D"
2425t "std_logic_vector"
2426b "(15 DOWNTO 0)"
2427o 57
2428suid 107,0
2429)
2430declText (MLText
2431uid 3635,0
2432va (VaSet
2433font "Courier New,8,0"
2434)
2435xt "39000,44600,67500,45400"
2436st "W_D                   : std_logic_vector(15 DOWNTO 0)
2437"
2438)
2439)
2440*72 (Net
2441uid 3636,0
2442decl (Decl
2443n "W_RES"
2444t "std_logic"
2445o 54
2446suid 108,0
2447i "'1'"
2448)
2449declText (MLText
2450uid 3637,0
2451va (VaSet
2452font "Courier New,8,0"
2453)
2454xt "39000,42200,71000,43000"
2455st "W_RES                 : std_logic                     := '1'
2456"
2457)
2458)
2459*73 (Net
2460uid 3638,0
2461decl (Decl
2462n "W_RD"
2463t "std_logic"
2464o 53
2465suid 109,0
2466i "'1'"
2467)
2468declText (MLText
2469uid 3639,0
2470va (VaSet
2471font "Courier New,8,0"
2472)
2473xt "39000,41400,71000,42200"
2474st "W_RD                  : std_logic                     := '1'
2475"
2476)
2477)
2478*74 (Net
2479uid 3640,0
2480decl (Decl
2481n "W_WR"
2482t "std_logic"
2483o 55
2484suid 110,0
2485i "'1'"
2486)
2487declText (MLText
2488uid 3641,0
2489va (VaSet
2490font "Courier New,8,0"
2491)
2492xt "39000,43000,71000,43800"
2493st "W_WR                  : std_logic                     := '1'
2494"
2495)
2496)
2497*75 (Net
2498uid 3642,0
2499decl (Decl
2500n "W_INT"
2501t "std_logic"
2502o 16
2503suid 111,0
2504)
2505declText (MLText
2506uid 3643,0
2507va (VaSet
2508font "Courier New,8,0"
2509)
2510xt "39000,16600,57000,17400"
2511st "W_INT                 : std_logic
2512"
2513)
2514)
2515*76 (Net
2516uid 3644,0
2517decl (Decl
2518n "W_CS"
2519t "std_logic"
2520o 52
2521suid 112,0
2522i "'1'"
2523)
2524declText (MLText
2525uid 3645,0
2526va (VaSet
2527font "Courier New,8,0"
2528)
2529xt "39000,40600,71000,41400"
2530st "W_CS                  : std_logic                     := '1'
2531"
2532)
2533)
2534*77 (PortIoInOut
2535uid 3674,0
2536shape (CompositeShape
2537uid 3675,0
2538va (VaSet
2539vasetType 1
2540fg "0,0,32768"
2541)
2542optionalChildren [
2543(Hexagon
2544uid 3676,0
2545sl 0
2546xt "90500,98625,92000,99375"
2547)
2548(Line
2549uid 3677,0
2550sl 0
2551xt "90000,99000,90500,99000"
2552pts [
2553"90000,99000"
2554"90500,99000"
2555]
2556)
2557]
2558)
2559stc 0
2560sf 1
2561tg (WTG
2562uid 3678,0
2563ps "PortIoTextPlaceStrategy"
2564stg "STSignalDisplayStrategy"
2565f (Text
2566uid 3679,0
2567va (VaSet
2568)
2569xt "93000,98500,95700,99500"
2570st "MISO"
2571blo "93000,99300"
2572tm "WireNameMgr"
2573)
2574)
2575)
2576*78 (Net
2577uid 3680,0
2578decl (Decl
2579n "MOSI"
2580t "std_logic"
2581o 34
2582suid 113,0
2583i "'0'"
2584)
2585declText (MLText
2586uid 3681,0
2587va (VaSet
2588font "Courier New,8,0"
2589)
2590xt "39000,28600,71000,29400"
2591st "MOSI                  : std_logic                     := '0'
2592"
2593)
2594)
2595*79 (PortIoOut
2596uid 3688,0
2597shape (CompositeShape
2598uid 3689,0
2599va (VaSet
2600vasetType 1
2601fg "0,0,32768"
2602)
2603optionalChildren [
2604(Pentagon
2605uid 3690,0
2606sl 0
2607ro 270
2608xt "90500,99625,92000,100375"
2609)
2610(Line
2611uid 3691,0
2612sl 0
2613ro 270
2614xt "90000,100000,90500,100000"
2615pts [
2616"90000,100000"
2617"90500,100000"
2618]
2619)
2620]
2621)
2622stc 0
2623sf 1
2624tg (WTG
2625uid 3692,0
2626ps "PortIoTextPlaceStrategy"
2627stg "STSignalDisplayStrategy"
2628f (Text
2629uid 3693,0
2630va (VaSet
2631)
2632xt "93000,99500,95700,100500"
2633st "MOSI"
2634blo "93000,100300"
2635tm "WireNameMgr"
2636)
2637)
2638)
2639*80 (Net
2640uid 3694,0
2641decl (Decl
2642n "MISO"
2643t "std_logic"
2644preAdd 0
2645posAdd 0
2646o 56
2647suid 114,0
2648)
2649declText (MLText
2650uid 3695,0
2651va (VaSet
2652font "Courier New,8,0"
2653)
2654xt "39000,43800,57000,44600"
2655st "MISO                  : std_logic
2656"
2657)
2658)
2659*81 (PortIoOut
2660uid 3716,0
2661shape (CompositeShape
2662uid 3717,0
2663va (VaSet
2664vasetType 1
2665fg "0,0,32768"
2666)
2667optionalChildren [
2668(Pentagon
2669uid 3718,0
2670sl 0
2671ro 270
2672xt "176500,127625,178000,128375"
2673)
2674(Line
2675uid 3719,0
2676sl 0
2677ro 270
2678xt "176000,128000,176500,128000"
2679pts [
2680"176000,128000"
2681"176500,128000"
2682]
2683)
2684]
2685)
2686stc 0
2687sf 1
2688tg (WTG
2689uid 3720,0
2690ps "PortIoTextPlaceStrategy"
2691stg "STSignalDisplayStrategy"
2692f (Text
2693uid 3721,0
2694va (VaSet
2695)
2696xt "179000,127500,185100,128500"
2697st "RS485_C_DE"
2698blo "179000,128300"
2699tm "WireNameMgr"
2700)
2701)
2702)
2703*82 (PortIoOut
2704uid 3722,0
2705shape (CompositeShape
2706uid 3723,0
2707va (VaSet
2708vasetType 1
2709fg "0,0,32768"
2710)
2711optionalChildren [
2712(Pentagon
2713uid 3724,0
2714sl 0
2715ro 270
2716xt "176500,128625,178000,129375"
2717)
2718(Line
2719uid 3725,0
2720sl 0
2721ro 270
2722xt "176000,129000,176500,129000"
2723pts [
2724"176000,129000"
2725"176500,129000"
2726]
2727)
2728]
2729)
2730stc 0
2731sf 1
2732tg (WTG
2733uid 3726,0
2734ps "PortIoTextPlaceStrategy"
2735stg "STSignalDisplayStrategy"
2736f (Text
2737uid 3727,0
2738va (VaSet
2739)
2740xt "179000,128500,185200,129500"
2741st "RS485_C_DO"
2742blo "179000,129300"
2743tm "WireNameMgr"
2744)
2745)
2746)
2747*83 (PortIoOut
2748uid 3728,0
2749shape (CompositeShape
2750uid 3729,0
2751va (VaSet
2752vasetType 1
2753fg "0,0,32768"
2754)
2755optionalChildren [
2756(Pentagon
2757uid 3730,0
2758sl 0
2759ro 270
2760xt "85500,147625,87000,148375"
2761)
2762(Line
2763uid 3731,0
2764sl 0
2765ro 270
2766xt "85000,148000,85500,148000"
2767pts [
2768"85000,148000"
2769"85500,148000"
2770]
2771)
2772]
2773)
2774stc 0
2775sf 1
2776tg (WTG
2777uid 3732,0
2778ps "PortIoTextPlaceStrategy"
2779stg "STSignalDisplayStrategy"
2780f (Text
2781uid 3733,0
2782va (VaSet
2783)
2784xt "88000,147500,94000,148500"
2785st "RS485_E_RE"
2786blo "88000,148300"
2787tm "WireNameMgr"
2788)
2789)
2790)
2791*84 (PortIoOut
2792uid 3734,0
2793shape (CompositeShape
2794uid 3735,0
2795va (VaSet
2796vasetType 1
2797fg "0,0,32768"
2798)
2799optionalChildren [
2800(Pentagon
2801uid 3736,0
2802sl 0
2803ro 270
2804xt "85500,146625,87000,147375"
2805)
2806(Line
2807uid 3737,0
2808sl 0
2809ro 270
2810xt "85000,147000,85500,147000"
2811pts [
2812"85000,147000"
2813"85500,147000"
2814]
2815)
2816]
2817)
2818stc 0
2819sf 1
2820tg (WTG
2821uid 3738,0
2822ps "PortIoTextPlaceStrategy"
2823stg "STSignalDisplayStrategy"
2824f (Text
2825uid 3739,0
2826va (VaSet
2827)
2828xt "88000,146500,94100,147500"
2829st "RS485_E_DE"
2830blo "88000,147300"
2831tm "WireNameMgr"
2832)
2833)
2834)
2835*85 (PortIoOut
2836uid 3740,0
2837shape (CompositeShape
2838uid 3741,0
2839va (VaSet
2840vasetType 1
2841fg "0,0,32768"
2842)
2843optionalChildren [
2844(Pentagon
2845uid 3742,0
2846sl 0
2847ro 270
2848xt "82500,120625,84000,121375"
2849)
2850(Line
2851uid 3743,0
2852sl 0
2853ro 270
2854xt "82000,121000,82500,121000"
2855pts [
2856"82000,121000"
2857"82500,121000"
2858]
2859)
2860]
2861)
2862stc 0
2863sf 1
2864tg (WTG
2865uid 3744,0
2866ps "PortIoTextPlaceStrategy"
2867stg "STSignalDisplayStrategy"
2868f (Text
2869uid 3745,0
2870va (VaSet
2871)
2872xt "85000,120500,89100,121500"
2873st "DENABLE"
2874blo "85000,121300"
2875tm "WireNameMgr"
2876)
2877)
2878)
2879*86 (PortIoOut
2880uid 3752,0
2881shape (CompositeShape
2882uid 3753,0
2883va (VaSet
2884vasetType 1
2885fg "0,0,32768"
2886)
2887optionalChildren [
2888(Pentagon
2889uid 3754,0
2890sl 0
2891ro 270
2892xt "176500,135625,178000,136375"
2893)
2894(Line
2895uid 3755,0
2896sl 0
2897ro 270
2898xt "176000,136000,176500,136000"
2899pts [
2900"176000,136000"
2901"176500,136000"
2902]
2903)
2904]
2905)
2906stc 0
2907sf 1
2908tg (WTG
2909uid 3756,0
2910ps "PortIoTextPlaceStrategy"
2911stg "STSignalDisplayStrategy"
2912f (Text
2913uid 3757,0
2914va (VaSet
2915)
2916xt "179000,135500,182000,136500"
2917st "EE_CS"
2918blo "179000,136300"
2919tm "WireNameMgr"
2920)
2921)
2922)
2923*87 (Net
2924uid 3866,0
2925decl (Decl
2926n "RS485_C_RE"
2927t "std_logic"
2928o 39
2929suid 127,0
2930)
2931declText (MLText
2932uid 3867,0
2933va (VaSet
2934font "Courier New,8,0"
2935)
2936xt "39000,32600,57000,33400"
2937st "RS485_C_RE            : std_logic
2938"
2939)
2940)
2941*88 (Net
2942uid 3868,0
2943decl (Decl
2944n "RS485_C_DE"
2945t "std_logic"
2946o 37
2947suid 128,0
2948)
2949declText (MLText
2950uid 3869,0
2951va (VaSet
2952font "Courier New,8,0"
2953)
2954xt "39000,31000,57000,31800"
2955st "RS485_C_DE            : std_logic
2956"
2957)
2958)
2959*89 (Net
2960uid 3870,0
2961decl (Decl
2962n "RS485_E_RE"
2963t "std_logic"
2964o 42
2965suid 129,0
2966)
2967declText (MLText
2968uid 3871,0
2969va (VaSet
2970font "Courier New,8,0"
2971)
2972xt "39000,35000,57000,35800"
2973st "RS485_E_RE            : std_logic
2974"
2975)
2976)
2977*90 (Net
2978uid 3872,0
2979decl (Decl
2980n "RS485_E_DE"
2981t "std_logic"
2982o 40
2983suid 130,0
2984)
2985declText (MLText
2986uid 3873,0
2987va (VaSet
2988font "Courier New,8,0"
2989)
2990xt "39000,33400,57000,34200"
2991st "RS485_E_DE            : std_logic
2992"
2993)
2994)
2995*91 (Net
2996uid 3874,0
2997decl (Decl
2998n "DENABLE"
2999t "std_logic"
3000o 27
3001suid 131,0
3002i "'0'"
3003)
3004declText (MLText
3005uid 3875,0
3006va (VaSet
3007font "Courier New,8,0"
3008)
3009xt "39000,22200,71000,23000"
3010st "DENABLE               : std_logic                     := '0'
3011"
3012)
3013)
3014*92 (Net
3015uid 3878,0
3016decl (Decl
3017n "EE_CS"
3018t "std_logic"
3019o 32
3020suid 133,0
3021)
3022declText (MLText
3023uid 3879,0
3024va (VaSet
3025font "Courier New,8,0"
3026)
3027xt "39000,27000,57000,27800"
3028st "EE_CS                 : std_logic
3029"
3030)
3031)
3032*93 (PortIoOut
3033uid 4916,0
3034shape (CompositeShape
3035uid 4917,0
3036va (VaSet
3037vasetType 1
3038fg "0,0,32768"
3039)
3040optionalChildren [
3041(Pentagon
3042uid 4918,0
3043sl 0
3044ro 270
3045xt "176500,103625,178000,104375"
3046)
3047(Line
3048uid 4919,0
3049sl 0
3050ro 270
3051xt "176000,104000,176500,104000"
3052pts [
3053"176000,104000"
3054"176500,104000"
3055]
3056)
3057]
3058)
3059stc 0
3060sf 1
3061tg (WTG
3062uid 4920,0
3063ps "PortIoTextPlaceStrategy"
3064stg "STSignalDisplayStrategy"
3065f (Text
3066uid 4921,0
3067va (VaSet
3068)
3069xt "179000,103500,181000,104500"
3070st "D_T"
3071blo "179000,104300"
3072tm "WireNameMgr"
3073)
3074)
3075)
3076*94 (Net
3077uid 5320,0
3078decl (Decl
3079n "D_T"
3080t "std_logic_vector"
3081b "(7 DOWNTO 0)"
3082o 30
3083suid 141,0
3084i "(OTHERS => '0')"
3085)
3086declText (MLText
3087uid 5321,0
3088va (VaSet
3089font "Courier New,8,0"
3090)
3091xt "39000,25400,77000,26200"
3092st "D_T                   : std_logic_vector(7 DOWNTO 0)  := (OTHERS => '0')
3093"
3094)
3095)
3096*95 (PortIoOut
3097uid 6874,0
3098shape (CompositeShape
3099uid 6875,0
3100va (VaSet
3101vasetType 1
3102fg "0,0,32768"
3103)
3104optionalChildren [
3105(Pentagon
3106uid 6876,0
3107sl 0
3108ro 270
3109xt "176500,124625,178000,125375"
3110)
3111(Line
3112uid 6877,0
3113sl 0
3114ro 270
3115xt "176000,125000,176500,125000"
3116pts [
3117"176000,125000"
3118"176500,125000"
3119]
3120)
3121]
3122)
3123stc 0
3124sf 1
3125tg (WTG
3126uid 6878,0
3127ps "PortIoTextPlaceStrategy"
3128stg "STSignalDisplayStrategy"
3129f (Text
3130uid 6879,0
3131va (VaSet
3132)
3133xt "179000,124500,181500,125500"
3134st "D_T2"
3135blo "179000,125300"
3136tm "WireNameMgr"
3137)
3138)
3139)
3140*96 (Net
3141uid 6886,0
3142decl (Decl
3143n "D_T2"
3144t "std_logic_vector"
3145b "(1 DOWNTO 0)"
3146o 31
3147suid 154,0
3148i "(others => '0')"
3149)
3150declText (MLText
3151uid 6887,0
3152va (VaSet
3153font "Courier New,8,0"
3154)
3155xt "39000,26200,77000,27000"
3156st "D_T2                  : std_logic_vector(1 DOWNTO 0)  := (others => '0')
3157"
3158)
3159)
3160*97 (PortIoOut
3161uid 7138,0
3162shape (CompositeShape
3163uid 7139,0
3164va (VaSet
3165vasetType 1
3166fg "0,0,32768"
3167)
3168optionalChildren [
3169(Pentagon
3170uid 7140,0
3171sl 0
3172ro 270
3173xt "176500,105625,178000,106375"
3174)
3175(Line
3176uid 7141,0
3177sl 0
3178ro 270
3179xt "176000,106000,176500,106000"
3180pts [
3181"176000,106000"
3182"176500,106000"
3183]
3184)
3185]
3186)
3187stc 0
3188sf 1
3189tg (WTG
3190uid 7142,0
3191ps "PortIoTextPlaceStrategy"
3192stg "STSignalDisplayStrategy"
3193f (Text
3194uid 7143,0
3195va (VaSet
3196)
3197xt "179000,105500,181400,106500"
3198st "A1_T"
3199blo "179000,106300"
3200tm "WireNameMgr"
3201)
3202)
3203)
3204*98 (Net
3205uid 7150,0
3206decl (Decl
3207n "A1_T"
3208t "std_logic_vector"
3209b "(7 DOWNTO 0)"
3210o 19
3211suid 155,0
3212i "(OTHERS => '0')"
3213)
3214declText (MLText
3215uid 7151,0
3216va (VaSet
3217font "Courier New,8,0"
3218)
3219xt "39000,19000,77000,19800"
3220st "A1_T                  : std_logic_vector(7 DOWNTO 0)  := (OTHERS => '0')
3221"
3222)
3223)
3224*99 (Net
3225uid 9500,0
3226decl (Decl
3227n "CLK_50"
3228t "std_logic"
3229o 63
3230suid 163,0
3231)
3232declText (MLText
3233uid 9501,0
3234va (VaSet
3235font "Courier New,8,0"
3236)
3237xt "39000,47200,61000,48000"
3238st "SIGNAL CLK_50                : std_logic
3239"
3240)
3241)
3242*100 (PortIoOut
3243uid 10296,0
3244shape (CompositeShape
3245uid 10297,0
3246va (VaSet
3247vasetType 1
3248fg "0,0,32768"
3249)
3250optionalChildren [
3251(Pentagon
3252uid 10298,0
3253sl 0
3254ro 270
3255xt "176500,110625,178000,111375"
3256)
3257(Line
3258uid 10299,0
3259sl 0
3260ro 270
3261xt "176000,111000,176500,111000"
3262pts [
3263"176000,111000"
3264"176500,111000"
3265]
3266)
3267]
3268)
3269stc 0
3270sf 1
3271tg (WTG
3272uid 10300,0
3273ps "PortIoTextPlaceStrategy"
3274stg "STSignalDisplayStrategy"
3275f (Text
3276uid 10301,0
3277va (VaSet
3278)
3279xt "179000,110500,181500,111500"
3280st "A0_T"
3281blo "179000,111300"
3282tm "WireNameMgr"
3283)
3284)
3285)
3286*101 (Net
3287uid 10308,0
3288decl (Decl
3289n "A0_T"
3290t "std_logic_vector"
3291b "(7 DOWNTO 0)"
3292o 18
3293suid 166,0
3294i "(others => '0')"
3295)
3296declText (MLText
3297uid 10309,0
3298va (VaSet
3299font "Courier New,8,0"
3300)
3301xt "39000,18200,77000,19000"
3302st "A0_T                  : std_logic_vector(7 DOWNTO 0)  := (others => '0')
3303"
3304)
3305)
3306*102 (HdlText
3307uid 10310,0
3308optionalChildren [
3309*103 (EmbeddedText
3310uid 10316,0
3311commentText (CommentText
3312uid 10317,0
3313ps "CenterOffsetStrategy"
3314shape (Rectangle
3315uid 10318,0
3316va (VaSet
3317vasetType 1
3318fg "65535,65535,65535"
3319lineColor "0,0,32768"
3320lineWidth 2
3321)
3322xt "154000,66000,186000,102000"
3323)
3324oxt "0,0,18000,5000"
3325text (MLText
3326uid 10319,0
3327va (VaSet
3328)
3329xt "154200,66200,178100,97200"
3330st "
3331-- testpins D_T2 are used as MAX3485 outputs.
3332
3333--D_T <= (others => '0');
3334D_T <= w5300_state;
3335D_T2(0) <= debug_data_valid;
3336D_T2(1) <= debug_data_ram_empty;
3337--D_T2 <= ( others => '0' );
3338
3339-- A0_T(7 downto 0) <= (others => '0');
3340--A1_T(7 downto 0) <= (others => '0');
3341
3342A1_T <= counter_result ( 7 downto 0);
3343--D_T(3 downto 0) <=  counter_result ( 11 downto 8);
3344--D_T(4) <= alarm_refclk_too_low;
3345--D_T(5) <= alarm_refclk_too_high;
3346--D_T(6) <= '0';
3347--D_T(7) <= '0';
3348
3349-- led output is driven by w5300 modul
3350-- for debugging only.
3351A0_T <= led;
3352
3353-- additional MAX3485 is switched to shutdown mode
3354RS485_C_RE <= '1';  --inverted logic
3355RS485_C_DE <= '0';   
3356RS485_C_DO <= '0';
3357-- MAX3485 receiver out pit is fed out... should be HIGH-Z
3358
3359
3360-- EEPROM is not used on FAD. CS is always high.
3361EE_CS <= '1';
3362"
3363tm "HdlTextMgr"
3364wrapOption 3
3365visibleHeight 36000
3366visibleWidth 32000
3367)
3368)
3369)
3370]
3371shape (Rectangle
3372uid 10311,0
3373va (VaSet
3374vasetType 1
3375fg "65535,65535,37120"
3376lineColor "0,0,32768"
3377lineWidth 2
3378)
3379xt "165000,104000,171000,138000"
3380)
3381oxt "0,0,8000,10000"
3382ttg (MlTextGroup
3383uid 10312,0
3384ps "CenterOffsetStrategy"
3385stg "VerticalLayoutStrategy"
3386textVec [
3387*104 (Text
3388uid 10313,0
3389va (VaSet
3390font "Arial,8,1"
3391)
3392xt "168150,107000,169850,108000"
3393st "eb3"
3394blo "168150,107800"
3395tm "HdlTextNameMgr"
3396)
3397*105 (Text
3398uid 10314,0
3399va (VaSet
3400font "Arial,8,1"
3401)
3402xt "168150,108000,168950,109000"
3403st "9"
3404blo "168150,108800"
3405tm "HdlTextNumberMgr"
3406)
3407]
3408)
3409viewicon (ZoomableIcon
3410uid 10315,0
3411sl 0
3412va (VaSet
3413vasetType 1
3414fg "49152,49152,49152"
3415)
3416xt "165250,136250,166750,137750"
3417iconName "TextFile.png"
3418iconMaskName "TextFile.msk"
3419ftype 21
3420)
3421viewiconposition 0
3422)
3423*106 (PortIoIn
3424uid 11090,0
3425shape (CompositeShape
3426uid 11091,0
3427va (VaSet
3428vasetType 1
3429fg "0,0,32768"
3430)
3431optionalChildren [
3432(Pentagon
3433uid 11092,0
3434sl 0
3435ro 270
3436xt "161000,128625,162500,129375"
3437)
3438(Line
3439uid 11093,0
3440sl 0
3441ro 270
3442xt "162500,129000,163000,129000"
3443pts [
3444"162500,129000"
3445"163000,129000"
3446]
3447)
3448]
3449)
3450stc 0
3451sf 1
3452tg (WTG
3453uid 11094,0
3454ps "PortIoTextPlaceStrategy"
3455stg "STSignalDisplayStrategy"
3456f (Text
3457uid 11095,0
3458va (VaSet
3459)
3460xt "154000,128500,160000,129500"
3461st "RS485_C_DI"
3462ju 2
3463blo "160000,129300"
3464tm "WireNameMgr"
3465)
3466)
3467)
3468*107 (Net
3469uid 11102,0
3470decl (Decl
3471n "RS485_C_DI"
3472t "std_logic"
3473o 13
3474suid 197,0
3475)
3476declText (MLText
3477uid 11103,0
3478va (VaSet
3479font "Courier New,8,0"
3480)
3481xt "39000,14200,57000,15000"
3482st "RS485_C_DI            : std_logic
3483"
3484)
3485)
3486*108 (PortIoOut
3487uid 11104,0
3488shape (CompositeShape
3489uid 11105,0
3490va (VaSet
3491vasetType 1
3492fg "0,0,32768"
3493)
3494optionalChildren [
3495(Pentagon
3496uid 11106,0
3497sl 0
3498ro 270
3499xt "176500,129625,178000,130375"
3500)
3501(Line
3502uid 11107,0
3503sl 0
3504ro 270
3505xt "176000,130000,176500,130000"
3506pts [
3507"176000,130000"
3508"176500,130000"
3509]
3510)
3511]
3512)
3513stc 0
3514sf 1
3515tg (WTG
3516uid 11108,0
3517ps "PortIoTextPlaceStrategy"
3518stg "STSignalDisplayStrategy"
3519f (Text
3520uid 11109,0
3521va (VaSet
3522)
3523xt "179000,129500,185000,130500"
3524st "RS485_C_RE"
3525blo "179000,130300"
3526tm "WireNameMgr"
3527)
3528)
3529)
3530*109 (Net
3531uid 11116,0
3532decl (Decl
3533n "RS485_C_DO"
3534t "std_logic"
3535o 38
3536suid 198,0
3537)
3538declText (MLText
3539uid 11117,0
3540va (VaSet
3541font "Courier New,8,0"
3542)
3543xt "39000,31800,57000,32600"
3544st "RS485_C_DO            : std_logic
3545"
3546)
3547)
3548*110 (PortIoIn
3549uid 11508,0
3550shape (CompositeShape
3551uid 11509,0
3552va (VaSet
3553vasetType 1
3554fg "0,0,32768"
3555)
3556optionalChildren [
3557(Pentagon
3558uid 11510,0
3559sl 0
3560ro 90
3561xt "85500,149625,87000,150375"
3562)
3563(Line
3564uid 11511,0
3565sl 0
3566ro 90
3567xt "85000,150000,85500,150000"
3568pts [
3569"85500,150000"
3570"85000,150000"
3571]
3572)
3573]
3574)
3575stc 0
3576sf 1
3577tg (WTG
3578uid 11512,0
3579ps "PortIoTextPlaceStrategy"
3580stg "STSignalDisplayStrategy"
3581f (Text
3582uid 11513,0
3583va (VaSet
3584)
3585xt "88000,149500,94000,150500"
3586st "RS485_E_DI"
3587blo "88000,150300"
3588tm "WireNameMgr"
3589)
3590)
3591)
3592*111 (Net
3593uid 11520,0
3594decl (Decl
3595n "RS485_E_DI"
3596t "std_logic"
3597o 14
3598suid 200,0
3599)
3600declText (MLText
3601uid 11521,0
3602va (VaSet
3603font "Courier New,8,0"
3604)
3605xt "39000,15000,57000,15800"
3606st "RS485_E_DI            : std_logic
3607"
3608)
3609)
3610*112 (Net
3611uid 11534,0
3612decl (Decl
3613n "RS485_E_DO"
3614t "std_logic"
3615o 41
3616suid 201,0
3617)
3618declText (MLText
3619uid 11535,0
3620va (VaSet
3621font "Courier New,8,0"
3622)
3623xt "39000,34200,57000,35000"
3624st "RS485_E_DO            : std_logic
3625"
3626)
3627)
3628*113 (PortIoOut
3629uid 12326,0
3630shape (CompositeShape
3631uid 12327,0
3632va (VaSet
3633vasetType 1
3634fg "0,0,32768"
3635)
3636optionalChildren [
3637(Pentagon
3638uid 12328,0
3639sl 0
3640ro 270
3641xt "87500,139625,89000,140375"
3642)
3643(Line
3644uid 12329,0
3645sl 0
3646ro 270
3647xt "87000,140000,87500,140000"
3648pts [
3649"87000,140000"
3650"87500,140000"
3651]
3652)
3653]
3654)
3655stc 0
3656sf 1
3657tg (WTG
3658uid 12330,0
3659ps "PortIoTextPlaceStrategy"
3660stg "STSignalDisplayStrategy"
3661f (Text
3662uid 12331,0
3663va (VaSet
3664)
3665xt "89000,139500,91500,140500"
3666st "SRIN"
3667blo "89000,140300"
3668tm "WireNameMgr"
3669)
3670)
3671)
3672*114 (Net
3673uid 12334,0
3674decl (Decl
3675n "SRIN"
3676t "std_logic"
3677o 44
3678suid 203,0
3679i "'0'"
3680)
3681declText (MLText
3682uid 12335,0
3683va (VaSet
3684font "Courier New,8,0"
3685)
3686xt "39000,36600,71000,37400"
3687st "SRIN                  : std_logic                     := '0'
3688"
3689)
3690)
3691*115 (PortIoOut
3692uid 12539,0
3693shape (CompositeShape
3694uid 12540,0
3695va (VaSet
3696vasetType 1
3697fg "0,0,32768"
3698)
3699optionalChildren [
3700(Pentagon
3701uid 12541,0
3702sl 0
3703ro 270
3704xt "87500,140625,89000,141375"
3705)
3706(Line
3707uid 12542,0
3708sl 0
3709ro 270
3710xt "87000,141000,87500,141000"
3711pts [
3712"87000,141000"
3713"87500,141000"
3714]
3715)
3716]
3717)
3718stc 0
3719sf 1
3720tg (WTG
3721uid 12543,0
3722ps "PortIoTextPlaceStrategy"
3723stg "STSignalDisplayStrategy"
3724f (Text
3725uid 12544,0
3726va (VaSet
3727)
3728xt "90000,140500,95200,141500"
3729st "AMBER_LED"
3730blo "90000,141300"
3731tm "WireNameMgr"
3732)
3733)
3734)
3735*116 (PortIoOut
3736uid 12553,0
3737shape (CompositeShape
3738uid 12554,0
3739va (VaSet
3740vasetType 1
3741fg "0,0,32768"
3742)
3743optionalChildren [
3744(Pentagon
3745uid 12555,0
3746sl 0
3747ro 270
3748xt "87500,141625,89000,142375"
3749)
3750(Line
3751uid 12556,0
3752sl 0
3753ro 270
3754xt "87000,142000,87500,142000"
3755pts [
3756"87000,142000"
3757"87500,142000"
3758]
3759)
3760]
3761)
3762stc 0
3763sf 1
3764tg (WTG
3765uid 12557,0
3766ps "PortIoTextPlaceStrategy"
3767stg "STSignalDisplayStrategy"
3768f (Text
3769uid 12558,0
3770va (VaSet
3771)
3772xt "90000,141500,95000,142500"
3773st "GREEN_LED"
3774blo "90000,142300"
3775tm "WireNameMgr"
3776)
3777)
3778)
3779*117 (PortIoOut
3780uid 12567,0
3781shape (CompositeShape
3782uid 12568,0
3783va (VaSet
3784vasetType 1
3785fg "0,0,32768"
3786)
3787optionalChildren [
3788(Pentagon
3789uid 12569,0
3790sl 0
3791ro 270
3792xt "87500,142625,89000,143375"
3793)
3794(Line
3795uid 12570,0
3796sl 0
3797ro 270
3798xt "87000,143000,87500,143000"
3799pts [
3800"87000,143000"
3801"87500,143000"
3802]
3803)
3804]
3805)
3806stc 0
3807sf 1
3808tg (WTG
3809uid 12571,0
3810ps "PortIoTextPlaceStrategy"
3811stg "STSignalDisplayStrategy"
3812f (Text
3813uid 12572,0
3814va (VaSet
3815)
3816xt "90000,142500,94000,143500"
3817st "RED_LED"
3818blo "90000,143300"
3819tm "WireNameMgr"
3820)
3821)
3822)
3823*118 (Net
3824uid 12762,0
3825decl (Decl
3826n "AMBER_LED"
3827t "std_logic"
3828o 20
3829suid 207,0
3830)
3831declText (MLText
3832uid 12763,0
3833va (VaSet
3834font "Courier New,8,0"
3835)
3836xt "39000,19800,57000,20600"
3837st "AMBER_LED             : std_logic
3838"
3839)
3840)
3841*119 (Net
3842uid 12764,0
3843decl (Decl
3844n "GREEN_LED"
3845t "std_logic"
3846o 33
3847suid 208,0
3848)
3849declText (MLText
3850uid 12765,0
3851va (VaSet
3852font "Courier New,8,0"
3853)
3854xt "39000,27800,57000,28600"
3855st "GREEN_LED             : std_logic
3856"
3857)
3858)
3859*120 (Net
3860uid 12766,0
3861decl (Decl
3862n "RED_LED"
3863t "std_logic"
3864o 36
3865suid 209,0
3866)
3867declText (MLText
3868uid 12767,0
3869va (VaSet
3870font "Courier New,8,0"
3871)
3872xt "39000,30200,57000,31000"
3873st "RED_LED               : std_logic
3874"
3875)
3876)
3877*121 (PortIoIn
3878uid 13516,0
3879shape (CompositeShape
3880uid 13517,0
3881va (VaSet
3882vasetType 1
3883fg "0,0,32768"
3884)
3885optionalChildren [
3886(Pentagon
3887uid 13518,0
3888sl 0
3889ro 270
3890xt "20000,80625,21500,81375"
3891)
3892(Line
3893uid 13519,0
3894sl 0
3895ro 270
3896xt "21500,81000,22000,81000"
3897pts [
3898"21500,81000"
3899"22000,81000"
3900]
3901)
3902]
3903)
3904stc 0
3905sf 1
3906tg (WTG
3907uid 13520,0
3908ps "PortIoTextPlaceStrategy"
3909stg "STSignalDisplayStrategy"
3910f (Text
3911uid 13521,0
3912va (VaSet
3913)
3914xt "16700,80500,19000,81500"
3915st "LINE"
3916ju 2
3917blo "19000,81300"
3918tm "WireNameMgr"
3919)
3920)
3921)
3922*122 (Net
3923uid 13528,0
3924decl (Decl
3925n "LINE"
3926t "std_logic_vector"
3927b "( 5 DOWNTO 0 )"
3928o 11
3929suid 210,0
3930)
3931declText (MLText
3932uid 13529,0
3933va (VaSet
3934font "Courier New,8,0"
3935)
3936xt "39000,12600,68000,13400"
3937st "LINE                  : std_logic_vector( 5 DOWNTO 0 )
3938"
3939)
3940)
3941*123 (PortIoIn
3942uid 13628,0
3943shape (CompositeShape
3944uid 13629,0
3945va (VaSet
3946vasetType 1
3947fg "0,0,32768"
3948)
3949optionalChildren [
3950(Pentagon
3951uid 13630,0
3952sl 0
3953ro 270
3954xt "47000,132625,48500,133375"
3955)
3956(Line
3957uid 13631,0
3958sl 0
3959ro 270
3960xt "48500,133000,49000,133000"
3961pts [
3962"48500,133000"
3963"49000,133000"
3964]
3965)
3966]
3967)
3968stc 0
3969sf 1
3970tg (WTG
3971uid 13632,0
3972ps "PortIoTextPlaceStrategy"
3973stg "STSignalDisplayStrategy"
3974f (Text
3975uid 13633,0
3976va (VaSet
3977)
3978xt "42700,132500,46000,133500"
3979st "REFCLK"
3980ju 2
3981blo "46000,133300"
3982tm "WireNameMgr"
3983)
3984)
3985)
3986*124 (Net
3987uid 13640,0
3988decl (Decl
3989n "REFCLK"
3990t "std_logic"
3991o 12
3992suid 211,0
3993)
3994declText (MLText
3995uid 13641,0
3996va (VaSet
3997font "Courier New,8,0"
3998)
3999xt "39000,13400,57000,14200"
4000st "REFCLK                : std_logic
4001"
4002)
4003)
4004*125 (PortIoIn
4005uid 14322,0
4006shape (CompositeShape
4007uid 14323,0
4008va (VaSet
4009vasetType 1
4010fg "0,0,32768"
4011)
4012optionalChildren [
4013(Pentagon
4014uid 14324,0
4015sl 0
4016ro 270
4017xt "47000,131625,48500,132375"
4018)
4019(Line
4020uid 14325,0
4021sl 0
4022ro 270
4023xt "48500,132000,49000,132000"
4024pts [
4025"48500,132000"
4026"49000,132000"
4027]
4028)
4029]
4030)
4031stc 0
4032sf 1
4033tg (WTG
4034uid 14326,0
4035ps "PortIoTextPlaceStrategy"
4036stg "STSignalDisplayStrategy"
4037f (Text
4038uid 14327,0
4039va (VaSet
4040)
4041xt "42900,131500,46000,132500"
4042st "D_T_in"
4043ju 2
4044blo "46000,132300"
4045tm "WireNameMgr"
4046)
4047)
4048)
4049*126 (Net
4050uid 14334,0
4051decl (Decl
4052n "D_T_in"
4053t "std_logic_vector"
4054b "(1 DOWNTO 0)"
4055o 10
4056suid 213,0
4057)
4058declText (MLText
4059uid 14335,0
4060va (VaSet
4061font "Courier New,8,0"
4062)
4063xt "39000,11800,67000,12600"
4064st "D_T_in                : std_logic_vector(1 DOWNTO 0)
4065"
4066)
4067)
4068*127 (Net
4069uid 15173,0
4070decl (Decl
4071n "led"
4072t "std_logic_vector"
4073b "(7 DOWNTO 0)"
4074posAdd 0
4075o 77
4076suid 215,0
4077i "(OTHERS => '0')"
4078)
4079declText (MLText
4080uid 15174,0
4081va (VaSet
4082font "Courier New,8,0"
4083)
4084xt "39000,55200,80500,56000"
4085st "SIGNAL led                   : std_logic_vector(7 DOWNTO 0)  := (OTHERS => '0')
4086"
4087)
4088)
4089*128 (PortIoOut
4090uid 15557,0
4091shape (CompositeShape
4092uid 15558,0
4093va (VaSet
4094vasetType 1
4095fg "0,0,32768"
4096)
4097optionalChildren [
4098(Pentagon
4099uid 15559,0
4100sl 0
4101ro 270
4102xt "85500,148625,87000,149375"
4103)
4104(Line
4105uid 15560,0
4106sl 0
4107ro 270
4108xt "85000,149000,85500,149000"
4109pts [
4110"85000,149000"
4111"85500,149000"
4112]
4113)
4114]
4115)
4116stc 0
4117sf 1
4118tg (WTG
4119uid 15561,0
4120ps "PortIoTextPlaceStrategy"
4121stg "STSignalDisplayStrategy"
4122f (Text
4123uid 15562,0
4124va (VaSet
4125)
4126xt "88000,148500,94200,149500"
4127st "RS485_E_DO"
4128blo "88000,149300"
4129tm "WireNameMgr"
4130)
4131)
4132)
4133*129 (PortIoIn
4134uid 15706,0
4135shape (CompositeShape
4136uid 15707,0
4137va (VaSet
4138vasetType 1
4139fg "0,0,32768"
4140)
4141optionalChildren [
4142(Pentagon
4143uid 15708,0
4144sl 0
4145ro 270
4146xt "47000,136625,48500,137375"
4147)
4148(Line
4149uid 15709,0
4150sl 0
4151ro 270
4152xt "48500,137000,49000,137000"
4153pts [
4154"48500,137000"
4155"49000,137000"
4156]
4157)
4158]
4159)
4160stc 0
4161sf 1
4162tg (WTG
4163uid 15710,0
4164ps "PortIoTextPlaceStrategy"
4165stg "STSignalDisplayStrategy"
4166f (Text
4167uid 15711,0
4168va (VaSet
4169)
4170xt "41900,136500,46000,137500"
4171st "D_PLLLCK"
4172ju 2
4173blo "46000,137300"
4174tm "WireNameMgr"
4175)
4176)
4177)
4178*130 (Net
4179uid 15718,0
4180decl (Decl
4181n "D_PLLLCK"
4182t "std_logic_vector"
4183b "(3 DOWNTO 0)"
4184o 81
4185suid 216,0
4186)
4187declText (MLText
4188uid 15719,0
4189va (VaSet
4190font "Courier New,8,0"
4191)
4192xt "39000,11000,67000,11800"
4193st "D_PLLLCK              : std_logic_vector(3 DOWNTO 0)
4194"
4195)
4196)
4197*131 (PortIoOut
4198uid 15845,0
4199shape (CompositeShape
4200uid 15846,0
4201va (VaSet
4202vasetType 1
4203fg "0,0,32768"
4204)
4205optionalChildren [
4206(Pentagon
4207uid 15847,0
4208sl 0
4209ro 270
4210xt "90500,88625,92000,89375"
4211)
4212(Line
4213uid 15848,0
4214sl 0
4215ro 270
4216xt "90000,89000,90500,89000"
4217pts [
4218"90000,89000"
4219"90500,89000"
4220]
4221)
4222]
4223)
4224stc 0
4225sf 1
4226tg (WTG
4227uid 15849,0
4228ps "PortIoTextPlaceStrategy"
4229stg "STSignalDisplayStrategy"
4230f (Text
4231uid 15850,0
4232va (VaSet
4233)
4234xt "93000,88500,95000,89500"
4235st "TCS"
4236blo "93000,89300"
4237tm "WireNameMgr"
4238)
4239)
4240)
4241*132 (Net
4242uid 15857,0
4243decl (Decl
4244n "TCS"
4245t "std_logic_vector"
4246b "(3 DOWNTO 0)"
4247o 70
4248suid 217,0
4249)
4250declText (MLText
4251uid 15858,0
4252va (VaSet
4253font "Courier New,8,0"
4254)
4255xt "39000,38200,67000,39000"
4256st "TCS                   : std_logic_vector(3 DOWNTO 0)
4257"
4258)
4259)
4260*133 (PortIoOut
4261uid 16057,0
4262shape (CompositeShape
4263uid 16058,0
4264va (VaSet
4265vasetType 1
4266fg "0,0,32768"
4267)
4268optionalChildren [
4269(Pentagon
4270uid 16059,0
4271sl 0
4272ro 90
4273xt "19000,112625,20500,113375"
4274)
4275(Line
4276uid 16060,0
4277sl 0
4278ro 90
4279xt "20500,113000,21000,113000"
4280pts [
4281"21000,113000"
4282"20500,113000"
4283]
4284)
4285]
4286)
4287stc 0
4288sf 1
4289tg (WTG
4290uid 16061,0
4291ps "PortIoTextPlaceStrategy"
4292stg "STSignalDisplayStrategy"
4293f (Text
4294uid 16062,0
4295va (VaSet
4296)
4297xt "14500,112500,18000,113500"
4298st "DSRCLK"
4299ju 2
4300blo "18000,113300"
4301tm "WireNameMgr"
4302)
4303)
4304)
4305*134 (Net
4306uid 16069,0
4307decl (Decl
4308n "DSRCLK"
4309t "std_logic_vector"
4310b "(3 DOWNTO 0)"
4311o 60
4312suid 222,0
4313i "(others => '0')"
4314)
4315declText (MLText
4316uid 16070,0
4317va (VaSet
4318font "Courier New,8,0"
4319)
4320xt "39000,23000,77000,23800"
4321st "DSRCLK                : std_logic_vector(3 DOWNTO 0)  := (others => '0')
4322"
4323)
4324)
4325*135 (Net
4326uid 16245,0
4327decl (Decl
4328n "SRCLK"
4329t "std_logic"
4330o 61
4331suid 225,0
4332i "'0'"
4333)
4334declText (MLText
4335uid 16246,0
4336va (VaSet
4337font "Courier New,8,0"
4338)
4339xt "39000,48000,74500,48800"
4340st "SIGNAL SRCLK                 : std_logic                     := '0'
4341"
4342)
4343)
4344*136 (HdlText
4345uid 16336,0
4346optionalChildren [
4347*137 (EmbeddedText
4348uid 16342,0
4349commentText (CommentText
4350uid 16343,0
4351ps "CenterOffsetStrategy"
4352shape (Rectangle
4353uid 16344,0
4354va (VaSet
4355vasetType 1
4356fg "65535,65535,65535"
4357lineColor "0,0,32768"
4358lineWidth 2
4359)
4360xt "23000,116000,42000,118000"
4361)
4362oxt "0,0,18000,5000"
4363text (MLText
4364uid 16345,0
4365va (VaSet
4366)
4367xt "23200,116200,40600,117200"
4368st "
4369DSRCLK <= ( SRCLK, SRCLK,SRCLK,SRCLK);
4370"
4371tm "HdlTextMgr"
4372wrapOption 3
4373visibleHeight 2000
4374visibleWidth 19000
4375)
4376)
4377)
4378]
4379shape (Rectangle
4380uid 16337,0
4381va (VaSet
4382vasetType 1
4383fg "65535,65535,37120"
4384lineColor "0,0,32768"
4385lineWidth 2
4386)
4387xt "30000,112000,34000,116000"
4388)
4389oxt "0,0,8000,10000"
4390ttg (MlTextGroup
4391uid 16338,0
4392ps "CenterOffsetStrategy"
4393stg "VerticalLayoutStrategy"
4394textVec [
4395*138 (Text
4396uid 16339,0
4397va (VaSet
4398font "Arial,8,1"
4399)
4400xt "30150,112000,33350,113000"
4401st "SRCLK"
4402blo "30150,112800"
4403tm "HdlTextNameMgr"
4404)
4405*139 (Text
4406uid 16340,0
4407va (VaSet
4408font "Arial,8,1"
4409)
4410xt "30150,113000,30950,114000"
4411st "1"
4412blo "30150,113800"
4413tm "HdlTextNumberMgr"
4414)
4415]
4416)
4417viewicon (ZoomableIcon
4418uid 16341,0
4419sl 0
4420va (VaSet
4421vasetType 1
4422fg "49152,49152,49152"
4423)
4424xt "30250,114250,31750,115750"
4425iconName "TextFile.png"
4426iconMaskName "TextFile.msk"
4427ftype 21
4428)
4429viewiconposition 0
4430)
4431*140 (Net
4432uid 16536,0
4433decl (Decl
4434n "alarm_refclk_too_high"
4435t "std_logic"
4436o 62
4437suid 226,0
4438i "'0'"
4439)
4440declText (MLText
4441uid 16537,0
4442va (VaSet
4443font "Courier New,8,0"
4444)
4445xt "39000,49600,74500,50400"
4446st "SIGNAL alarm_refclk_too_high : std_logic                     := '0'
4447"
4448)
4449)
4450*141 (Net
4451uid 16544,0
4452decl (Decl
4453n "alarm_refclk_too_low"
4454t "std_logic"
4455o 63
4456suid 227,0
4457i "'0'"
4458)
4459declText (MLText
4460uid 16545,0
4461va (VaSet
4462font "Courier New,8,0"
4463)
4464xt "39000,50400,74500,51200"
4465st "SIGNAL alarm_refclk_too_low  : std_logic                     := '0'
4466"
4467)
4468)
4469*142 (Net
4470uid 16574,0
4471decl (Decl
4472n "counter_result"
4473t "std_logic_vector"
4474b "(11 downto 0)"
4475o 64
4476suid 230,0
4477i "(others => '0')"
4478)
4479declText (MLText
4480uid 16575,0
4481va (VaSet
4482font "Courier New,8,0"
4483)
4484xt "39000,52000,80500,52800"
4485st "SIGNAL counter_result        : std_logic_vector(11 downto 0) := (others => '0')
4486"
4487)
4488)
4489*143 (SaComponent
4490uid 17195,0
4491optionalChildren [
4492*144 (CptPort
4493uid 17027,0
4494ps "OnEdgeStrategy"
4495shape (Triangle
4496uid 17028,0
4497ro 90
4498va (VaSet
4499vasetType 1
4500fg "0,65535,0"
4501)
4502xt "80000,70625,80750,71375"
4503)
4504tg (CPTG
4505uid 17029,0
4506ps "CptPortTextPlaceStrategy"
4507stg "RightVerticalLayoutStrategy"
4508f (Text
4509uid 17030,0
4510va (VaSet
4511)
4512xt "74800,70500,79000,71500"
4513st "wiz_reset"
4514ju 2
4515blo "79000,71300"
4516)
4517)
4518thePort (LogicalPort
4519m 1
4520decl (Decl
4521n "wiz_reset"
4522t "std_logic"
4523o 47
4524suid 2,0
4525i "'1'"
4526)
4527)
4528)
4529*145 (CptPort
4530uid 17031,0
4531ps "OnEdgeStrategy"
4532shape (Triangle
4533uid 17032,0
4534ro 90
4535va (VaSet
4536vasetType 1
4537fg "0,65535,0"
4538)
4539xt "80000,119625,80750,120375"
4540)
4541tg (CPTG
4542uid 17033,0
4543ps "CptPortTextPlaceStrategy"
4544stg "RightVerticalLayoutStrategy"
4545f (Text
4546uid 17034,0
4547va (VaSet
4548)
4549xt "74600,119500,79000,120500"
4550st "led : (7:0)"
4551ju 2
4552blo "79000,120300"
4553)
4554)
4555thePort (LogicalPort
4556m 1
4557decl (Decl
4558n "led"
4559t "std_logic_vector"
4560b "(7 DOWNTO 0)"
4561posAdd 0
4562o 37
4563suid 7,0
4564i "(OTHERS => '0')"
4565)
4566)
4567)
4568*146 (CptPort
4569uid 17035,0
4570ps "OnEdgeStrategy"
4571shape (Triangle
4572uid 17036,0
4573ro 90
4574va (VaSet
4575vasetType 1
4576fg "0,65535,0"
4577)
4578xt "51250,77625,52000,78375"
4579)
4580tg (CPTG
4581uid 17037,0
4582ps "CptPortTextPlaceStrategy"
4583stg "VerticalLayoutStrategy"
4584f (Text
4585uid 17038,0
4586va (VaSet
4587)
4588xt "53000,77500,56000,78500"
4589st "trigger"
4590blo "53000,78300"
4591)
4592)
4593thePort (LogicalPort
4594decl (Decl
4595n "trigger"
4596t "std_logic"
4597preAdd 0
4598posAdd 0
4599o 14
4600suid 18,0
4601)
4602)
4603)
4604*147 (CptPort
4605uid 17039,0
4606ps "OnEdgeStrategy"
4607shape (Triangle
4608uid 17040,0
4609ro 270
4610va (VaSet
4611vasetType 1
4612fg "0,65535,0"
4613)
4614xt "51250,89625,52000,90375"
4615)
4616tg (CPTG
4617uid 17041,0
4618ps "CptPortTextPlaceStrategy"
4619stg "VerticalLayoutStrategy"
4620f (Text
4621uid 17042,0
4622va (VaSet
4623)
4624xt "53000,89500,56500,90500"
4625st "adc_oeb"
4626blo "53000,90300"
4627)
4628)
4629thePort (LogicalPort
4630m 1
4631decl (Decl
4632n "adc_oeb"
4633t "std_logic"
4634o 25
4635suid 21,0
4636i "'1'"
4637)
4638)
4639)
4640*148 (CptPort
4641uid 17043,0
4642ps "OnEdgeStrategy"
4643shape (Triangle
4644uid 17044,0
4645ro 90
4646va (VaSet
4647vasetType 1
4648fg "0,65535,0"
4649)
4650xt "51250,80625,52000,81375"
4651)
4652tg (CPTG
4653uid 17045,0
4654ps "CptPortTextPlaceStrategy"
4655stg "VerticalLayoutStrategy"
4656f (Text
4657uid 17046,0
4658va (VaSet
4659)
4660xt "53000,80500,59700,81500"
4661st "board_id : (3:0)"
4662blo "53000,81300"
4663)
4664)
4665thePort (LogicalPort
4666decl (Decl
4667n "board_id"
4668t "std_logic_vector"
4669b "(3 DOWNTO 0)"
4670o 10
4671suid 24,0
4672)
4673)
4674)
4675*149 (CptPort
4676uid 17047,0
4677ps "OnEdgeStrategy"
4678shape (Triangle
4679uid 17048,0
4680ro 90
4681va (VaSet
4682vasetType 1
4683fg "0,65535,0"
4684)
4685xt "51250,81625,52000,82375"
4686)
4687tg (CPTG
4688uid 17049,0
4689ps "CptPortTextPlaceStrategy"
4690stg "VerticalLayoutStrategy"
4691f (Text
4692uid 17050,0
4693va (VaSet
4694)
4695xt "53000,81500,59400,82500"
4696st "crate_id : (1:0)"
4697blo "53000,82300"
4698)
4699)
4700thePort (LogicalPort
4701decl (Decl
4702n "crate_id"
4703t "std_logic_vector"
4704b "(1 DOWNTO 0)"
4705o 11
4706suid 25,0
4707)
4708)
4709)
4710*150 (CptPort
4711uid 17051,0
4712ps "OnEdgeStrategy"
4713shape (Triangle
4714uid 17052,0
4715ro 90
4716va (VaSet
4717vasetType 1
4718fg "0,65535,0"
4719)
4720xt "80000,67625,80750,68375"
4721)
4722tg (CPTG
4723uid 17053,0
4724ps "CptPortTextPlaceStrategy"
4725stg "RightVerticalLayoutStrategy"
4726f (Text
4727uid 17054,0
4728va (VaSet
4729)
4730xt "72100,67500,79000,68500"
4731st "wiz_addr : (9:0)"
4732ju 2
4733blo "79000,68300"
4734)
4735)
4736thePort (LogicalPort
4737m 1
4738decl (Decl
4739n "wiz_addr"
4740t "std_logic_vector"
4741b "(9 DOWNTO 0)"
4742o 44
4743suid 26,0
4744)
4745)
4746)
4747*151 (CptPort
4748uid 17055,0
4749ps "OnEdgeStrategy"
4750shape (Diamond
4751uid 17056,0
4752ro 90
4753va (VaSet
4754vasetType 1
4755fg "0,65535,0"
4756)
4757xt "80000,68625,80750,69375"
4758)
4759tg (CPTG
4760uid 17057,0
4761ps "CptPortTextPlaceStrategy"
4762stg "RightVerticalLayoutStrategy"
4763f (Text
4764uid 17058,0
4765va (VaSet
4766)
4767xt "71800,68500,79000,69500"
4768st "wiz_data : (15:0)"
4769ju 2
4770blo "79000,69300"
4771)
4772)
4773thePort (LogicalPort
4774m 2
4775decl (Decl
4776n "wiz_data"
4777t "std_logic_vector"
4778b "(15 DOWNTO 0)"
4779o 50
4780suid 27,0
4781)
4782)
4783)
4784*152 (CptPort
4785uid 17059,0
4786ps "OnEdgeStrategy"
4787shape (Triangle
4788uid 17060,0
4789ro 90
4790va (VaSet
4791vasetType 1
4792fg "0,65535,0"
4793)
4794xt "80000,74625,80750,75375"
4795)
4796tg (CPTG
4797uid 17061,0
4798ps "CptPortTextPlaceStrategy"
4799stg "RightVerticalLayoutStrategy"
4800f (Text
4801uid 17062,0
4802va (VaSet
4803)
4804xt "76000,74500,79000,75500"
4805st "wiz_cs"
4806ju 2
4807blo "79000,75300"
4808)
4809)
4810thePort (LogicalPort
4811m 1
4812decl (Decl
4813n "wiz_cs"
4814t "std_logic"
4815o 45
4816suid 28,0
4817i "'1'"
4818)
4819)
4820)
4821*153 (CptPort
4822uid 17063,0
4823ps "OnEdgeStrategy"
4824shape (Triangle
4825uid 17064,0
4826ro 90
4827va (VaSet
4828vasetType 1
4829fg "0,65535,0"
4830)
4831xt "80000,72625,80750,73375"
4832)
4833tg (CPTG
4834uid 17065,0
4835ps "CptPortTextPlaceStrategy"
4836stg "RightVerticalLayoutStrategy"
4837f (Text
4838uid 17066,0
4839va (VaSet
4840)
4841xt "75800,72500,79000,73500"
4842st "wiz_wr"
4843ju 2
4844blo "79000,73300"
4845)
4846)
4847thePort (LogicalPort
4848m 1
4849decl (Decl
4850n "wiz_wr"
4851t "std_logic"
4852o 48
4853suid 29,0
4854i "'1'"
4855)
4856)
4857)
4858*154 (CptPort
4859uid 17067,0
4860ps "OnEdgeStrategy"
4861shape (Triangle
4862uid 17068,0
4863ro 90
4864va (VaSet
4865vasetType 1
4866fg "0,65535,0"
4867)
4868xt "80000,71625,80750,72375"
4869)
4870tg (CPTG
4871uid 17069,0
4872ps "CptPortTextPlaceStrategy"
4873stg "RightVerticalLayoutStrategy"
4874f (Text
4875uid 17070,0
4876va (VaSet
4877)
4878xt "75900,71500,79000,72500"
4879st "wiz_rd"
4880ju 2
4881blo "79000,72300"
4882)
4883)
4884thePort (LogicalPort
4885m 1
4886decl (Decl
4887n "wiz_rd"
4888t "std_logic"
4889o 46
4890suid 30,0
4891i "'1'"
4892)
4893)
4894)
4895*155 (CptPort
4896uid 17071,0
4897ps "OnEdgeStrategy"
4898shape (Triangle
4899uid 17072,0
4900ro 270
4901va (VaSet
4902vasetType 1
4903fg "0,65535,0"
4904)
4905xt "80000,73625,80750,74375"
4906)
4907tg (CPTG
4908uid 17073,0
4909ps "CptPortTextPlaceStrategy"
4910stg "RightVerticalLayoutStrategy"
4911f (Text
4912uid 17074,0
4913va (VaSet
4914)
4915xt "75800,73500,79000,74500"
4916st "wiz_int"
4917ju 2
4918blo "79000,74300"
4919)
4920)
4921thePort (LogicalPort
4922decl (Decl
4923n "wiz_int"
4924t "std_logic"
4925o 15
4926suid 31,0
4927)
4928)
4929)
4930*156 (CptPort
4931uid 17075,0
4932ps "OnEdgeStrategy"
4933shape (Triangle
4934uid 17076,0
4935ro 270
4936va (VaSet
4937vasetType 1
4938fg "0,65535,0"
4939)
4940xt "51250,73625,52000,74375"
4941)
4942tg (CPTG
4943uid 17077,0
4944ps "CptPortTextPlaceStrategy"
4945stg "VerticalLayoutStrategy"
4946f (Text
4947uid 17078,0
4948va (VaSet
4949)
4950xt "53000,73500,57800,74500"
4951st "CLK_25_PS"
4952blo "53000,74300"
4953)
4954)
4955thePort (LogicalPort
4956m 1
4957decl (Decl
4958n "CLK_25_PS"
4959t "std_logic"
4960o 17
4961suid 35,0
4962)
4963)
4964)
4965*157 (CptPort
4966uid 17079,0
4967ps "OnEdgeStrategy"
4968shape (Triangle
4969uid 17080,0
4970ro 90
4971va (VaSet
4972vasetType 1
4973fg "0,65535,0"
4974)
4975xt "80000,115625,80750,116375"
4976)
4977tg (CPTG
4978uid 17081,0
4979ps "CptPortTextPlaceStrategy"
4980stg "RightVerticalLayoutStrategy"
4981f (Text
4982uid 17082,0
4983va (VaSet
4984)
4985xt "75700,115500,79000,116500"
4986st "CLK_50"
4987ju 2
4988blo "79000,116300"
4989)
4990)
4991thePort (LogicalPort
4992m 1
4993decl (Decl
4994n "CLK_50"
4995t "std_logic"
4996preAdd 0
4997posAdd 0
4998o 18
4999suid 37,0
5000)
5001)
5002)
5003*158 (CptPort
5004uid 17083,0
5005ps "OnEdgeStrategy"
5006shape (Triangle
5007uid 17084,0
5008ro 90
5009va (VaSet
5010vasetType 1
5011fg "0,65535,0"
5012)
5013xt "51250,67625,52000,68375"
5014)
5015tg (CPTG
5016uid 17085,0
5017ps "CptPortTextPlaceStrategy"
5018stg "VerticalLayoutStrategy"
5019f (Text
5020uid 17086,0
5021va (VaSet
5022)
5023xt "53000,67500,54900,68500"
5024st "CLK"
5025blo "53000,68300"
5026)
5027)
5028thePort (LogicalPort
5029decl (Decl
5030n "CLK"
5031t "std_logic"
5032o 1
5033suid 38,0
5034)
5035)
5036)
5037*159 (CptPort
5038uid 17087,0
5039ps "OnEdgeStrategy"
5040shape (Triangle
5041uid 17088,0
5042ro 90
5043va (VaSet
5044vasetType 1
5045fg "0,65535,0"
5046)
5047xt "51250,88625,52000,89375"
5048)
5049tg (CPTG
5050uid 17089,0
5051ps "CptPortTextPlaceStrategy"
5052stg "VerticalLayoutStrategy"
5053f (Text
5054uid 17090,0
5055va (VaSet
5056)
5057xt "53000,88500,62300,89500"
5058st "adc_otr_array : (3:0)"
5059blo "53000,89300"
5060)
5061)
5062thePort (LogicalPort
5063decl (Decl
5064n "adc_otr_array"
5065t "std_logic_vector"
5066b "(3 DOWNTO 0)"
5067o 9
5068suid 40,0
5069)
5070)
5071)
5072*160 (CptPort
5073uid 17091,0
5074ps "OnEdgeStrategy"
5075shape (Triangle
5076uid 17092,0
5077ro 90
5078va (VaSet
5079vasetType 1
5080fg "0,65535,0"
5081)
5082xt "51250,94625,52000,95375"
5083)
5084tg (CPTG
5085uid 17093,0
5086ps "CptPortTextPlaceStrategy"
5087stg "VerticalLayoutStrategy"
5088f (Text
5089uid 17094,0
5090va (VaSet
5091)
5092xt "53000,94500,59900,95500"
5093st "adc_data_array"
5094blo "53000,95300"
5095)
5096)
5097thePort (LogicalPort
5098decl (Decl
5099n "adc_data_array"
5100t "adc_data_array_type"
5101o 8
5102suid 41,0
5103)
5104)
5105)
5106*161 (CptPort
5107uid 17095,0
5108ps "OnEdgeStrategy"
5109shape (Triangle
5110uid 17096,0
5111ro 270
5112va (VaSet
5113vasetType 1
5114fg "0,65535,0"
5115)
5116xt "51250,108625,52000,109375"
5117)
5118tg (CPTG
5119uid 17097,0
5120ps "CptPortTextPlaceStrategy"
5121stg "VerticalLayoutStrategy"
5122f (Text
5123uid 17098,0
5124va (VaSet
5125)
5126xt "53000,108500,62500,109500"
5127st "drs_channel_id : (3:0)"
5128blo "53000,109300"
5129)
5130)
5131thePort (LogicalPort
5132m 1
5133decl (Decl
5134n "drs_channel_id"
5135t "std_logic_vector"
5136b "(3 downto 0)"
5137o 34
5138suid 48,0
5139i "(others => '0')"
5140)
5141)
5142)
5143*162 (CptPort
5144uid 17099,0
5145ps "OnEdgeStrategy"
5146shape (Triangle
5147uid 17100,0
5148ro 270
5149va (VaSet
5150vasetType 1
5151fg "0,65535,0"
5152)
5153xt "51250,109625,52000,110375"
5154)
5155tg (CPTG
5156uid 17101,0
5157ps "CptPortTextPlaceStrategy"
5158stg "VerticalLayoutStrategy"
5159f (Text
5160uid 17102,0
5161va (VaSet
5162)
5163xt "53000,109500,58200,110500"
5164st "drs_dwrite"
5165blo "53000,110300"
5166)
5167)
5168thePort (LogicalPort
5169m 1
5170decl (Decl
5171n "drs_dwrite"
5172t "std_logic"
5173o 35
5174suid 49,0
5175i "'1'"
5176)
5177)
5178)
5179*163 (CptPort
5180uid 17103,0
5181ps "OnEdgeStrategy"
5182shape (Triangle
5183uid 17104,0
5184ro 90
5185va (VaSet
5186vasetType 1
5187fg "0,65535,0"
5188)
5189xt "51250,104625,52000,105375"
5190)
5191tg (CPTG
5192uid 17105,0
5193ps "CptPortTextPlaceStrategy"
5194stg "VerticalLayoutStrategy"
5195f (Text
5196uid 17106,0
5197va (VaSet
5198)
5199xt "53000,104500,58800,105500"
5200st "SROUT_in_0"
5201blo "53000,105300"
5202)
5203)
5204thePort (LogicalPort
5205decl (Decl
5206n "SROUT_in_0"
5207t "std_logic"
5208o 4
5209suid 52,0
5210)
5211)
5212)
5213*164 (CptPort
5214uid 17107,0
5215ps "OnEdgeStrategy"
5216shape (Triangle
5217uid 17108,0
5218ro 90
5219va (VaSet
5220vasetType 1
5221fg "0,65535,0"
5222)
5223xt "51250,105625,52000,106375"
5224)
5225tg (CPTG
5226uid 17109,0
5227ps "CptPortTextPlaceStrategy"
5228stg "VerticalLayoutStrategy"
5229f (Text
5230uid 17110,0
5231va (VaSet
5232)
5233xt "53000,105500,58700,106500"
5234st "SROUT_in_1"
5235blo "53000,106300"
5236)
5237)
5238thePort (LogicalPort
5239decl (Decl
5240n "SROUT_in_1"
5241t "std_logic"
5242o 5
5243suid 53,0
5244)
5245)
5246)
5247*165 (CptPort
5248uid 17111,0
5249ps "OnEdgeStrategy"
5250shape (Triangle
5251uid 17112,0
5252ro 90
5253va (VaSet
5254vasetType 1
5255fg "0,65535,0"
5256)
5257xt "51250,106625,52000,107375"
5258)
5259tg (CPTG
5260uid 17113,0
5261ps "CptPortTextPlaceStrategy"
5262stg "VerticalLayoutStrategy"
5263f (Text
5264uid 17114,0
5265va (VaSet
5266)
5267xt "53000,106500,58800,107500"
5268st "SROUT_in_2"
5269blo "53000,107300"
5270)
5271)
5272thePort (LogicalPort
5273decl (Decl
5274n "SROUT_in_2"
5275t "std_logic"
5276o 6
5277suid 54,0
5278)
5279)
5280)
5281*166 (CptPort
5282uid 17115,0
5283ps "OnEdgeStrategy"
5284shape (Triangle
5285uid 17116,0
5286ro 90
5287va (VaSet
5288vasetType 1
5289fg "0,65535,0"
5290)
5291xt "51250,107625,52000,108375"
5292)
5293tg (CPTG
5294uid 17117,0
5295ps "CptPortTextPlaceStrategy"
5296stg "VerticalLayoutStrategy"
5297f (Text
5298uid 17118,0
5299va (VaSet
5300)
5301xt "53000,107500,58800,108500"
5302st "SROUT_in_3"
5303blo "53000,108300"
5304)
5305)
5306thePort (LogicalPort
5307decl (Decl
5308n "SROUT_in_3"
5309t "std_logic"
5310o 7
5311suid 55,0
5312)
5313)
5314)
5315*167 (CptPort
5316uid 17119,0
5317ps "OnEdgeStrategy"
5318shape (Triangle
5319uid 17120,0
5320ro 270
5321va (VaSet
5322vasetType 1
5323fg "0,65535,0"
5324)
5325xt "51250,110625,52000,111375"
5326)
5327tg (CPTG
5328uid 17121,0
5329ps "CptPortTextPlaceStrategy"
5330stg "VerticalLayoutStrategy"
5331f (Text
5332uid 17122,0
5333va (VaSet
5334)
5335xt "53000,110500,57200,111500"
5336st "RSRLOAD"
5337blo "53000,111300"
5338)
5339)
5340thePort (LogicalPort
5341m 1
5342decl (Decl
5343n "RSRLOAD"
5344t "std_logic"
5345o 22
5346suid 56,0
5347i "'0'"
5348)
5349)
5350)
5351*168 (CptPort
5352uid 17123,0
5353ps "OnEdgeStrategy"
5354shape (Triangle
5355uid 17124,0
5356ro 270
5357va (VaSet
5358vasetType 1
5359fg "0,65535,0"
5360)
5361xt "51250,112625,52000,113375"
5362)
5363tg (CPTG
5364uid 17125,0
5365ps "CptPortTextPlaceStrategy"
5366stg "VerticalLayoutStrategy"
5367f (Text
5368uid 17126,0
5369va (VaSet
5370)
5371xt "53000,112500,55900,113500"
5372st "SRCLK"
5373blo "53000,113300"
5374)
5375)
5376thePort (LogicalPort
5377m 1
5378decl (Decl
5379n "SRCLK"
5380t "std_logic"
5381o 23
5382suid 57,0
5383i "'0'"
5384)
5385)
5386)
5387*169 (CptPort
5388uid 17127,0
5389ps "OnEdgeStrategy"
5390shape (Triangle
5391uid 17128,0
5392ro 90
5393va (VaSet
5394vasetType 1
5395fg "0,65535,0"
5396)
5397xt "80000,97625,80750,98375"
5398)
5399tg (CPTG
5400uid 17129,0
5401ps "CptPortTextPlaceStrategy"
5402stg "RightVerticalLayoutStrategy"
5403f (Text
5404uid 17130,0
5405va (VaSet
5406)
5407xt "77100,97500,79000,98500"
5408st "sclk"
5409ju 2
5410blo "79000,98300"
5411)
5412)
5413thePort (LogicalPort
5414m 1
5415decl (Decl
5416n "sclk"
5417t "std_logic"
5418o 40
5419suid 62,0
5420)
5421)
5422)
5423*170 (CptPort
5424uid 17131,0
5425ps "OnEdgeStrategy"
5426shape (Diamond
5427uid 17132,0
5428ro 90
5429va (VaSet
5430vasetType 1
5431fg "0,65535,0"
5432)
5433xt "80000,98625,80750,99375"
5434)
5435tg (CPTG
5436uid 17133,0
5437ps "CptPortTextPlaceStrategy"
5438stg "RightVerticalLayoutStrategy"
5439f (Text
5440uid 17134,0
5441va (VaSet
5442)
5443xt "77600,98500,79000,99500"
5444st "sio"
5445ju 2
5446blo "79000,99300"
5447)
5448)
5449thePort (LogicalPort
5450m 2
5451decl (Decl
5452n "sio"
5453t "std_logic"
5454preAdd 0
5455posAdd 0
5456o 49
5457suid 63,0
5458)
5459)
5460)
5461*171 (CptPort
5462uid 17135,0
5463ps "OnEdgeStrategy"
5464shape (Triangle
5465uid 17136,0
5466ro 90
5467va (VaSet
5468vasetType 1
5469fg "0,65535,0"
5470)
5471xt "80000,86625,80750,87375"
5472)
5473tg (CPTG
5474uid 17137,0
5475ps "CptPortTextPlaceStrategy"
5476stg "RightVerticalLayoutStrategy"
5477f (Text
5478uid 17138,0
5479va (VaSet
5480)
5481xt "76000,86500,79000,87500"
5482st "dac_cs"
5483ju 2
5484blo "79000,87300"
5485)
5486)
5487thePort (LogicalPort
5488m 1
5489decl (Decl
5490n "dac_cs"
5491t "std_logic"
5492o 30
5493suid 64,0
5494)
5495)
5496)
5497*172 (CptPort
5498uid 17139,0
5499ps "OnEdgeStrategy"
5500shape (Triangle
5501uid 17140,0
5502ro 90
5503va (VaSet
5504vasetType 1
5505fg "0,65535,0"
5506)
5507xt "80000,88625,80750,89375"
5508)
5509tg (CPTG
5510uid 17141,0
5511ps "CptPortTextPlaceStrategy"
5512stg "RightVerticalLayoutStrategy"
5513f (Text
5514uid 17142,0
5515va (VaSet
5516)
5517xt "72000,88500,79000,89500"
5518st "sensor_cs : (3:0)"
5519ju 2
5520blo "79000,89300"
5521)
5522)
5523thePort (LogicalPort
5524m 1
5525decl (Decl
5526n "sensor_cs"
5527t "std_logic_vector"
5528b "(3 DOWNTO 0)"
5529o 41
5530suid 65,0
5531)
5532)
5533)
5534*173 (CptPort
5535uid 17143,0
5536ps "OnEdgeStrategy"
5537shape (Triangle
5538uid 17144,0
5539ro 90
5540va (VaSet
5541vasetType 1
5542fg "0,65535,0"
5543)
5544xt "80000,99625,80750,100375"
5545)
5546tg (CPTG
5547uid 17145,0
5548ps "CptPortTextPlaceStrategy"
5549stg "RightVerticalLayoutStrategy"
5550f (Text
5551uid 17146,0
5552va (VaSet
5553)
5554xt "77000,99500,79000,100500"
5555st "mosi"
5556ju 2
5557blo "79000,100300"
5558)
5559)
5560thePort (LogicalPort
5561m 1
5562decl (Decl
5563n "mosi"
5564t "std_logic"
5565o 38
5566suid 66,0
5567i "'0'"
5568)
5569)
5570)
5571*174 (CptPort
5572uid 17147,0
5573ps "OnEdgeStrategy"
5574shape (Triangle
5575uid 17148,0
5576ro 90
5577va (VaSet
5578vasetType 1
5579fg "0,65535,0"
5580)
5581xt "80000,120625,80750,121375"
5582)
5583tg (CPTG
5584uid 17149,0
5585ps "CptPortTextPlaceStrategy"
5586stg "RightVerticalLayoutStrategy"
5587f (Text
5588uid 17150,0
5589va (VaSet
5590)
5591xt "75800,120500,79000,121500"
5592st "denable"
5593ju 2
5594blo "79000,121300"
5595)
5596)
5597thePort (LogicalPort
5598m 1
5599decl (Decl
5600n "denable"
5601t "std_logic"
5602eolc "-- default domino wave off"
5603posAdd 0
5604o 33
5605suid 67,0
5606i "'0'"
5607)
5608)
5609)
5610*175 (CptPort
5611uid 17151,0
5612ps "OnEdgeStrategy"
5613shape (Triangle
5614uid 17152,0
5615ro 90
5616va (VaSet
5617vasetType 1
5618fg "0,65535,0"
5619)
5620xt "80000,139625,80750,140375"
5621)
5622tg (CPTG
5623uid 17153,0
5624ps "CptPortTextPlaceStrategy"
5625stg "RightVerticalLayoutStrategy"
5626f (Text
5627uid 17154,0
5628va (VaSet
5629)
5630xt "74800,139500,79000,140500"
5631st "SRIN_out"
5632ju 2
5633blo "79000,140300"
5634)
5635)
5636thePort (LogicalPort
5637m 1
5638decl (Decl
5639n "SRIN_out"
5640t "std_logic"
5641o 24
5642suid 85,0
5643i "'0'"
5644)
5645)
5646)
5647*176 (CptPort
5648uid 17155,0
5649ps "OnEdgeStrategy"
5650shape (Triangle
5651uid 17156,0
5652ro 90
5653va (VaSet
5654vasetType 1
5655fg "0,65535,0"
5656)
5657xt "80000,141625,80750,142375"
5658)
5659tg (CPTG
5660uid 17157,0
5661ps "CptPortTextPlaceStrategy"
5662stg "RightVerticalLayoutStrategy"
5663f (Text
5664uid 17158,0
5665va (VaSet
5666)
5667xt "76600,141500,79000,142500"
5668st "green"
5669ju 2
5670blo "79000,142300"
5671)
5672)
5673thePort (LogicalPort
5674m 1
5675decl (Decl
5676n "green"
5677t "std_logic"
5678o 36
5679suid 86,0
5680)
5681)
5682)
5683*177 (CptPort
5684uid 17159,0
5685ps "OnEdgeStrategy"
5686shape (Triangle
5687uid 17160,0
5688ro 90
5689va (VaSet
5690vasetType 1
5691fg "0,65535,0"
5692)
5693xt "80000,140625,80750,141375"
5694)
5695tg (CPTG
5696uid 17161,0
5697ps "CptPortTextPlaceStrategy"
5698stg "RightVerticalLayoutStrategy"
5699f (Text
5700uid 17162,0
5701va (VaSet
5702)
5703xt "76300,140500,79000,141500"
5704st "amber"
5705ju 2
5706blo "79000,141300"
5707)
5708)
5709thePort (LogicalPort
5710m 1
5711decl (Decl
5712n "amber"
5713t "std_logic"
5714o 28
5715suid 87,0
5716)
5717)
5718)
5719*178 (CptPort
5720uid 17163,0
5721ps "OnEdgeStrategy"
5722shape (Triangle
5723uid 17164,0
5724ro 90
5725va (VaSet
5726vasetType 1
5727fg "0,65535,0"
5728)
5729xt "80000,142625,80750,143375"
5730)
5731tg (CPTG
5732uid 17165,0
5733ps "CptPortTextPlaceStrategy"
5734stg "RightVerticalLayoutStrategy"
5735f (Text
5736uid 17166,0
5737va (VaSet
5738)
5739xt "77300,142500,79000,143500"
5740st "red"
5741ju 2
5742blo "79000,143300"
5743)
5744)
5745thePort (LogicalPort
5746m 1
5747decl (Decl
5748n "red"
5749t "std_logic"
5750o 39
5751suid 88,0
5752)
5753)
5754)
5755*179 (CptPort
5756uid 17167,0
5757ps "OnEdgeStrategy"
5758shape (Triangle
5759uid 17168,0
5760ro 90
5761va (VaSet
5762vasetType 1
5763fg "0,65535,0"
5764)
5765xt "51250,131625,52000,132375"
5766)
5767tg (CPTG
5768uid 17169,0
5769ps "CptPortTextPlaceStrategy"
5770stg "VerticalLayoutStrategy"
5771f (Text
5772uid 17170,0
5773va (VaSet
5774)
5775xt "53000,131500,58500,132500"
5776st "D_T_in : (1:0)"
5777blo "53000,132300"
5778)
5779)
5780thePort (LogicalPort
5781decl (Decl
5782n "D_T_in"
5783t "std_logic_vector"
5784b "(1 DOWNTO 0)"
5785o 2
5786suid 91,0
5787)
5788)
5789)
5790*180 (CptPort
5791uid 17171,0
5792ps "OnEdgeStrategy"
5793shape (Triangle
5794uid 17172,0
5795ro 90
5796va (VaSet
5797vasetType 1
5798fg "0,65535,0"
5799)
5800xt "51250,132625,52000,133375"
5801)
5802tg (CPTG
5803uid 17173,0
5804ps "CptPortTextPlaceStrategy"
5805stg "VerticalLayoutStrategy"
5806f (Text
5807uid 17174,0
5808va (VaSet
5809)
5810xt "53000,132500,59100,133500"
5811st "drs_refclk_in"
5812blo "53000,133300"
5813)
5814)
5815thePort (LogicalPort
5816decl (Decl
5817n "drs_refclk_in"
5818t "std_logic"
5819eolc "-- used to check if DRS REFCLK exsists, if not DENABLE inhibit"
5820o 12
5821suid 92,0
5822)
5823)
5824)
5825*181 (CptPort
5826uid 17175,0
5827ps "OnEdgeStrategy"
5828shape (Triangle
5829uid 17176,0
5830ro 90
5831va (VaSet
5832vasetType 1
5833fg "0,65535,0"
5834)
5835xt "51250,136625,52000,137375"
5836)
5837tg (CPTG
5838uid 17177,0
5839ps "CptPortTextPlaceStrategy"
5840stg "VerticalLayoutStrategy"
5841f (Text
5842uid 17178,0
5843va (VaSet
5844)
5845xt "53000,136500,59700,137500"
5846st "plllock_in : (3:0)"
5847blo "53000,137300"
5848)
5849)
5850thePort (LogicalPort
5851decl (Decl
5852n "plllock_in"
5853t "std_logic_vector"
5854b "(3 DOWNTO 0)"
5855eolc "-- high level, if dominowave is running and DRS PLL locked"
5856o 13
5857suid 93,0
5858)
5859)
5860)
5861*182 (CptPort
5862uid 17179,0
5863ps "OnEdgeStrategy"
5864shape (Triangle
5865uid 17180,0
5866ro 90
5867va (VaSet
5868vasetType 1
5869fg "0,65535,0"
5870)
5871xt "80000,131625,80750,132375"
5872)
5873tg (CPTG
5874uid 17181,0
5875ps "CptPortTextPlaceStrategy"
5876stg "RightVerticalLayoutStrategy"
5877f (Text
5878uid 17182,0
5879va (VaSet
5880)
5881xt "69400,131500,79000,132500"
5882st "counter_result : (11:0)"
5883ju 2
5884blo "79000,132300"
5885)
5886)
5887thePort (LogicalPort
5888m 1
5889decl (Decl
5890n "counter_result"
5891t "std_logic_vector"
5892b "(11 DOWNTO 0)"
5893o 29
5894suid 94,0
5895)
5896)
5897)
5898*183 (CptPort
5899uid 17183,0
5900ps "OnEdgeStrategy"
5901shape (Triangle
5902uid 17184,0
5903ro 90
5904va (VaSet
5905vasetType 1
5906fg "0,65535,0"
5907)
5908xt "80000,129625,80750,130375"
5909)
5910tg (CPTG
5911uid 17185,0
5912ps "CptPortTextPlaceStrategy"
5913stg "RightVerticalLayoutStrategy"
5914f (Text
5915uid 17186,0
5916va (VaSet
5917)
5918xt "69000,129500,79000,130500"
5919st "alarm_refclk_too_high"
5920ju 2
5921blo "79000,130300"
5922)
5923)
5924thePort (LogicalPort
5925m 1
5926decl (Decl
5927n "alarm_refclk_too_high"
5928t "std_logic"
5929o 26
5930suid 95,0
5931)
5932)
5933)
5934*184 (CptPort
5935uid 17187,0
5936ps "OnEdgeStrategy"
5937shape (Triangle
5938uid 17188,0
5939ro 90
5940va (VaSet
5941vasetType 1
5942fg "0,65535,0"
5943)
5944xt "80000,130625,80750,131375"
5945)
5946tg (CPTG
5947uid 17189,0
5948ps "CptPortTextPlaceStrategy"
5949stg "RightVerticalLayoutStrategy"
5950f (Text
5951uid 17190,0
5952va (VaSet
5953)
5954xt "69400,130500,79000,131500"
5955st "alarm_refclk_too_low"
5956ju 2
5957blo "79000,131300"
5958)
5959)
5960thePort (LogicalPort
5961m 1
5962decl (Decl
5963n "alarm_refclk_too_low"
5964t "std_logic"
5965posAdd 0
5966o 27
5967suid 96,0
5968)
5969)
5970)
5971*185 (CptPort
5972uid 17191,0
5973ps "OnEdgeStrategy"
5974shape (Triangle
5975uid 17192,0
5976ro 270
5977va (VaSet
5978vasetType 1
5979fg "0,65535,0"
5980)
5981xt "51250,70625,52000,71375"
5982)
5983tg (CPTG
5984uid 17193,0
5985ps "CptPortTextPlaceStrategy"
5986stg "VerticalLayoutStrategy"
5987f (Text
5988uid 17194,0
5989va (VaSet
5990)
5991xt "53000,70500,57000,71500"
5992st "ADC_CLK"
5993blo "53000,71300"
5994)
5995)
5996thePort (LogicalPort
5997lang 2
5998m 1
5999decl (Decl
6000n "ADC_CLK"
6001t "std_logic"
6002o 16
6003suid 97,0
6004)
6005)
6006)
6007*186 (CptPort
6008uid 17620,0
6009ps "OnEdgeStrategy"
6010shape (Triangle
6011uid 17621,0
6012ro 90
6013va (VaSet
6014vasetType 1
6015fg "0,65535,0"
6016)
6017xt "80000,143625,80750,144375"
6018)
6019tg (CPTG
6020uid 17622,0
6021ps "CptPortTextPlaceStrategy"
6022stg "RightVerticalLayoutStrategy"
6023f (Text
6024uid 17623,0
6025va (VaSet
6026)
6027xt "73400,143500,79000,144500"
6028st "trigger_veto"
6029ju 2
6030blo "79000,144300"
6031)
6032)
6033thePort (LogicalPort
6034m 1
6035decl (Decl
6036n "trigger_veto"
6037t "std_logic"
6038o 42
6039suid 98,0
6040i "'1'"
6041)
6042)
6043)
6044*187 (CptPort
6045uid 17711,0
6046ps "OnEdgeStrategy"
6047shape (Triangle
6048uid 17712,0
6049ro 270
6050va (VaSet
6051vasetType 1
6052fg "0,65535,0"
6053)
6054xt "80000,149625,80750,150375"
6055)
6056tg (CPTG
6057uid 17713,0
6058ps "CptPortTextPlaceStrategy"
6059stg "RightVerticalLayoutStrategy"
6060f (Text
6061uid 17714,0
6062va (VaSet
6063)
6064xt "70900,149500,79000,150500"
6065st "FTM_RS485_rx_d"
6066ju 2
6067blo "79000,150300"
6068)
6069)
6070thePort (LogicalPort
6071decl (Decl
6072n "FTM_RS485_rx_d"
6073t "std_logic"
6074o 3
6075suid 99,0
6076)
6077)
6078)
6079*188 (CptPort
6080uid 17715,0
6081ps "OnEdgeStrategy"
6082shape (Triangle
6083uid 17716,0
6084ro 90
6085va (VaSet
6086vasetType 1
6087fg "0,65535,0"
6088)
6089xt "80000,147625,80750,148375"
6090)
6091tg (CPTG
6092uid 17717,0
6093ps "CptPortTextPlaceStrategy"
6094stg "RightVerticalLayoutStrategy"
6095f (Text
6096uid 17718,0
6097va (VaSet
6098)
6099xt "70600,147500,79000,148500"
6100st "FTM_RS485_rx_en"
6101ju 2
6102blo "79000,148300"
6103)
6104)
6105thePort (LogicalPort
6106m 1
6107decl (Decl
6108n "FTM_RS485_rx_en"
6109t "std_logic"
6110o 19
6111suid 101,0
6112)
6113)
6114)
6115*189 (CptPort
6116uid 17719,0
6117ps "OnEdgeStrategy"
6118shape (Triangle
6119uid 17720,0
6120ro 90
6121va (VaSet
6122vasetType 1
6123fg "0,65535,0"
6124)
6125xt "80000,148625,80750,149375"
6126)
6127tg (CPTG
6128uid 17721,0
6129ps "CptPortTextPlaceStrategy"
6130stg "RightVerticalLayoutStrategy"
6131f (Text
6132uid 17722,0
6133va (VaSet
6134)
6135xt "70900,148500,79000,149500"
6136st "FTM_RS485_tx_d"
6137ju 2
6138blo "79000,149300"
6139)
6140)
6141thePort (LogicalPort
6142m 1
6143decl (Decl
6144n "FTM_RS485_tx_d"
6145t "std_logic"
6146o 20
6147suid 100,0
6148)
6149)
6150)
6151*190 (CptPort
6152uid 17723,0
6153ps "OnEdgeStrategy"
6154shape (Triangle
6155uid 17724,0
6156ro 90
6157va (VaSet
6158vasetType 1
6159fg "0,65535,0"
6160)
6161xt "80000,146625,80750,147375"
6162)
6163tg (CPTG
6164uid 17725,0
6165ps "CptPortTextPlaceStrategy"
6166stg "RightVerticalLayoutStrategy"
6167f (Text
6168uid 17726,0
6169va (VaSet
6170)
6171xt "70600,146500,79000,147500"
6172st "FTM_RS485_tx_en"
6173ju 2
6174blo "79000,147300"
6175)
6176)
6177thePort (LogicalPort
6178m 1
6179decl (Decl
6180n "FTM_RS485_tx_en"
6181t "std_logic"
6182o 21
6183suid 102,0
6184)
6185)
6186)
6187*191 (CptPort
6188uid 17842,0
6189ps "OnEdgeStrategy"
6190shape (Triangle
6191uid 17843,0
6192ro 90
6193va (VaSet
6194vasetType 1
6195fg "0,65535,0"
6196)
6197xt "80000,105625,80750,106375"
6198)
6199tg (CPTG
6200uid 17844,0
6201ps "CptPortTextPlaceStrategy"
6202stg "RightVerticalLayoutStrategy"
6203f (Text
6204uid 17845,0
6205va (VaSet
6206)
6207xt "70600,105500,79000,106500"
6208st "w5300_state : (7:0)"
6209ju 2
6210blo "79000,106300"
6211)
6212)
6213thePort (LogicalPort
6214m 1
6215decl (Decl
6216n "w5300_state"
6217t "std_logic_vector"
6218b "(7 DOWNTO 0)"
6219eolc "-- state is encoded here ... useful for debugging."
6220posAdd 0
6221o 43
6222suid 103,0
6223)
6224)
6225)
6226*192 (CptPort
6227uid 18058,0
6228ps "OnEdgeStrategy"
6229shape (Triangle
6230uid 18059,0
6231ro 90
6232va (VaSet
6233vasetType 1
6234fg "0,65535,0"
6235)
6236xt "80000,106625,80750,107375"
6237)
6238tg (CPTG
6239uid 18060,0
6240ps "CptPortTextPlaceStrategy"
6241stg "RightVerticalLayoutStrategy"
6242f (Text
6243uid 18061,0
6244va (VaSet
6245)
6246xt "68600,106500,79000,107500"
6247st "debug_data_ram_empty"
6248ju 2
6249blo "79000,107300"
6250)
6251)
6252thePort (LogicalPort
6253m 1
6254decl (Decl
6255n "debug_data_ram_empty"
6256t "std_logic"
6257o 31
6258suid 104,0
6259)
6260)
6261)
6262*193 (CptPort
6263uid 18062,0
6264ps "OnEdgeStrategy"
6265shape (Triangle
6266uid 18063,0
6267ro 90
6268va (VaSet
6269vasetType 1
6270fg "0,65535,0"
6271)
6272xt "80000,107625,80750,108375"
6273)
6274tg (CPTG
6275uid 18064,0
6276ps "CptPortTextPlaceStrategy"
6277stg "RightVerticalLayoutStrategy"
6278f (Text
6279uid 18065,0
6280va (VaSet
6281)
6282xt "71500,107500,79000,108500"
6283st "debug_data_valid"
6284ju 2
6285blo "79000,108300"
6286)
6287)
6288thePort (LogicalPort
6289m 1
6290decl (Decl
6291n "debug_data_valid"
6292t "std_logic"
6293o 32
6294suid 105,0
6295)
6296)
6297)
6298]
6299shape (Rectangle
6300uid 17196,0
6301va (VaSet
6302vasetType 1
6303fg "0,65535,0"
6304lineColor "0,32896,0"
6305lineWidth 2
6306)
6307xt "52000,66000,80000,153000"
6308)
6309oxt "15000,-8000,43000,70000"
6310ttg (MlTextGroup
6311uid 17197,0
6312ps "CenterOffsetStrategy"
6313stg "VerticalLayoutStrategy"
6314textVec [
6315*194 (Text
6316uid 17198,0
6317va (VaSet
6318font "Arial,8,1"
6319)
6320xt "55200,141000,61400,142000"
6321st "FACT_FAD_lib"
6322blo "55200,141800"
6323tm "BdLibraryNameMgr"
6324)
6325*195 (Text
6326uid 17199,0
6327va (VaSet
6328font "Arial,8,1"
6329)
6330xt "55200,142000,59400,143000"
6331st "FAD_main"
6332blo "55200,142800"
6333tm "CptNameMgr"
6334)
6335*196 (Text
6336uid 17200,0
6337va (VaSet
6338font "Arial,8,1"
6339)
6340xt "55200,143000,61000,144000"
6341st "I_board_main"
6342blo "55200,143800"
6343tm "InstanceNameMgr"
6344)
6345]
6346)
6347ga (GenericAssociation
6348uid 17201,0
6349ps "EdgeToEdgeStrategy"
6350matrix (Matrix
6351uid 17202,0
6352text (MLText
6353uid 17203,0
6354va (VaSet
6355font "Courier New,8,0"
6356)
6357xt "52000,65200,81500,66000"
6358st "RAMADDRWIDTH64b = LOG2_OF_RAM_SIZE_64B    ( integer )  "
6359)
6360header ""
6361)
6362elements [
6363(GiElement
6364name "RAMADDRWIDTH64b"
6365type "integer"
6366value "LOG2_OF_RAM_SIZE_64B"
6367)
6368]
6369)
6370viewicon (ZoomableIcon
6371uid 17204,0
6372sl 0
6373va (VaSet
6374vasetType 1
6375fg "49152,49152,49152"
6376)
6377xt "52250,151250,53750,152750"
6378iconName "BlockDiagram.png"
6379iconMaskName "BlockDiagram.msk"
6380ftype 1
6381)
6382viewiconposition 0
6383portVis (PortSigDisplay
6384)
6385archFileType "UNKNOWN"
6386)
6387*197 (Net
6388uid 17294,0
6389lang 2
6390decl (Decl
6391n "ADC_CLK"
6392t "std_logic"
6393o 61
6394suid 231,0
6395)
6396declText (MLText
6397uid 17295,0
6398va (VaSet
6399font "Courier New,8,0"
6400)
6401xt "39000,46400,61000,47200"
6402st "SIGNAL ADC_CLK               : std_logic
6403"
6404)
6405)
6406*198 (PortIoOut
6407uid 17401,0
6408shape (CompositeShape
6409uid 17402,0
6410va (VaSet
6411vasetType 1
6412fg "0,0,32768"
6413)
6414optionalChildren [
6415(Pentagon
6416uid 17403,0
6417sl 0
6418ro 270
6419xt "87500,143625,89000,144375"
6420)
6421(Line
6422uid 17404,0
6423sl 0
6424ro 270
6425xt "87000,144000,87500,144000"
6426pts [
6427"87000,144000"
6428"87500,144000"
6429]
6430)
6431]
6432)
6433stc 0
6434sf 1
6435tg (WTG
6436uid 17405,0
6437ps "PortIoTextPlaceStrategy"
6438stg "STSignalDisplayStrategy"
6439f (Text
6440uid 17406,0
6441va (VaSet
6442)
6443xt "90000,143500,92900,144500"
6444st "TRG_V"
6445blo "90000,144300"
6446tm "WireNameMgr"
6447)
6448)
6449)
6450*199 (Net
6451uid 17413,0
6452lang 2
6453decl (Decl
6454n "TRG_V"
6455t "std_logic"
6456o 62
6457suid 232,0
6458i "'0'"
6459)
6460declText (MLText
6461uid 17414,0
6462va (VaSet
6463font "Courier New,8,0"
6464)
6465xt "39000,39000,71000,39800"
6466st "TRG_V                 : std_logic                     := '0'
6467"
6468)
6469)
6470*200 (Net
6471uid 17846,0
6472decl (Decl
6473n "w5300_state"
6474t "std_logic_vector"
6475b "(7 DOWNTO 0)"
6476eolc "-- state is encoded here ... useful for debugging."
6477posAdd 0
6478o 63
6479suid 233,0
6480)
6481declText (MLText
6482uid 17847,0
6483va (VaSet
6484font "Courier New,8,0"
6485)
6486xt "39000,56000,96000,56800"
6487st "SIGNAL w5300_state           : std_logic_vector(7 DOWNTO 0) -- state is encoded here ... useful for debugging.
6488"
6489)
6490)
6491*201 (Net
6492uid 18066,0
6493decl (Decl
6494n "debug_data_ram_empty"
6495t "std_logic"
6496o 64
6497suid 234,0
6498)
6499declText (MLText
6500uid 18067,0
6501va (VaSet
6502font "Courier New,8,0"
6503)
6504xt "39000,53600,61000,54400"
6505st "SIGNAL debug_data_ram_empty  : std_logic
6506"
6507)
6508)
6509*202 (Net
6510uid 18074,0
6511decl (Decl
6512n "debug_data_valid"
6513t "std_logic"
6514o 65
6515suid 235,0
6516)
6517declText (MLText
6518uid 18075,0
6519va (VaSet
6520font "Courier New,8,0"
6521)
6522xt "39000,54400,61000,55200"
6523st "SIGNAL debug_data_valid      : std_logic
6524"
6525)
6526)
6527*203 (Wire
6528uid 245,0
6529shape (OrthoPolyLine
6530uid 246,0
6531va (VaSet
6532vasetType 3
6533)
6534xt "21000,68000,51250,68000"
6535pts [
6536"51250,68000"
6537"21000,68000"
6538]
6539)
6540start &158
6541end &13
6542sat 32
6543eat 32
6544stc 0
6545st 0
6546sf 1
6547si 0
6548tg (WTG
6549uid 249,0
6550ps "ConnStartEndStrategy"
6551stg "STSignalDisplayStrategy"
6552f (Text
6553uid 250,0
6554va (VaSet
6555isHidden 1
6556)
6557xt "53250,67000,56050,68000"
6558st "X_50M"
6559blo "53250,67800"
6560tm "WireNameMgr"
6561)
6562)
6563on &32
6564)
6565*204 (Wire
6566uid 277,0
6567shape (OrthoPolyLine
6568uid 278,0
6569va (VaSet
6570vasetType 3
6571lineWidth 2
6572)
6573xt "32000,81000,51250,81000"
6574pts [
6575"51250,81000"
6576"32000,81000"
6577]
6578)
6579start &148
6580end &14
6581sat 32
6582eat 2
6583sty 1
6584st 0
6585sf 1
6586si 0
6587tg (WTG
6588uid 281,0
6589ps "ConnStartEndStrategy"
6590stg "STSignalDisplayStrategy"
6591f (Text
6592uid 282,0
6593va (VaSet
6594)
6595xt "44000,80000,49900,81000"
6596st "board_id : (3:0)"
6597blo "44000,80800"
6598tm "WireNameMgr"
6599)
6600)
6601on &18
6602)
6603*205 (Wire
6604uid 285,0
6605shape (OrthoPolyLine
6606uid 286,0
6607va (VaSet
6608vasetType 3
6609lineWidth 2
6610)
6611xt "32000,82000,51250,82000"
6612pts [
6613"51250,82000"
6614"32000,82000"
6615]
6616)
6617start &149
6618end &14
6619sat 32
6620eat 2
6621sty 1
6622st 0
6623sf 1
6624si 0
6625tg (WTG
6626uid 289,0
6627ps "ConnStartEndStrategy"
6628stg "STSignalDisplayStrategy"
6629f (Text
6630uid 290,0
6631va (VaSet
6632)
6633xt "44000,81000,49700,82000"
6634st "crate_id : (1:0)"
6635blo "44000,81800"
6636tm "WireNameMgr"
6637)
6638)
6639on &19
6640)
6641*206 (Wire
6642uid 362,0
6643shape (OrthoPolyLine
6644uid 363,0
6645va (VaSet
6646vasetType 3
6647)
6648xt "21000,90000,51250,90000"
6649pts [
6650"21000,90000"
6651"51250,90000"
6652]
6653)
6654start &39
6655end &147
6656sat 32
6657eat 32
6658stc 0
6659st 0
6660sf 1
6661si 0
6662tg (WTG
6663uid 364,0
6664ps "ConnStartEndStrategy"
6665stg "STSignalDisplayStrategy"
6666f (Text
6667uid 365,0
6668va (VaSet
6669isHidden 1
6670)
6671xt "22000,89000,25600,90000"
6672st "OE_ADC"
6673blo "22000,89800"
6674tm "WireNameMgr"
6675)
6676)
6677on &40
6678)
6679*207 (Wire
6680uid 418,0
6681shape (OrthoPolyLine
6682uid 419,0
6683va (VaSet
6684vasetType 3
6685)
6686xt "80750,71000,90000,71000"
6687pts [
6688"80750,71000"
6689"90000,71000"
6690]
6691)
6692start &144
6693end &20
6694sat 32
6695eat 32
6696stc 0
6697st 0
6698sf 1
6699si 0
6700tg (WTG
6701uid 422,0
6702ps "ConnStartEndStrategy"
6703stg "STSignalDisplayStrategy"
6704f (Text
6705uid 423,0
6706va (VaSet
6707isHidden 1
6708)
6709xt "82000,70000,85100,71000"
6710st "W_RES"
6711blo "82000,70800"
6712tm "WireNameMgr"
6713)
6714)
6715on &72
6716)
6717*208 (Wire
6718uid 426,0
6719shape (OrthoPolyLine
6720uid 427,0
6721va (VaSet
6722vasetType 3
6723lineWidth 2
6724)
6725xt "80750,68000,90000,68000"
6726pts [
6727"80750,68000"
6728"90000,68000"
6729]
6730)
6731start &150
6732end &21
6733sat 32
6734eat 32
6735sty 1
6736stc 0
6737st 0
6738sf 1
6739si 0
6740tg (WTG
6741uid 430,0
6742ps "ConnStartEndStrategy"
6743stg "STSignalDisplayStrategy"
6744f (Text
6745uid 431,0
6746va (VaSet
6747isHidden 1
6748)
6749xt "82000,67000,84000,68000"
6750st "W_A"
6751blo "82000,67800"
6752tm "WireNameMgr"
6753)
6754)
6755on &70
6756)
6757*209 (Wire
6758uid 434,0
6759shape (OrthoPolyLine
6760uid 435,0
6761va (VaSet
6762vasetType 3
6763)
6764xt "80750,75000,90000,75000"
6765pts [
6766"80750,75000"
6767"90000,75000"
6768]
6769)
6770start &152
6771end &22
6772sat 32
6773eat 32
6774stc 0
6775st 0
6776sf 1
6777si 0
6778tg (WTG
6779uid 438,0
6780ps "ConnStartEndStrategy"
6781stg "STSignalDisplayStrategy"
6782f (Text
6783uid 439,0
6784va (VaSet
6785isHidden 1
6786)
6787xt "82000,74000,84600,75000"
6788st "W_CS"
6789blo "82000,74800"
6790tm "WireNameMgr"
6791)
6792)
6793on &76
6794)
6795*210 (Wire
6796uid 442,0
6797shape (OrthoPolyLine
6798uid 443,0
6799va (VaSet
6800vasetType 3
6801lineWidth 2
6802)
6803xt "80750,69000,90000,69000"
6804pts [
6805"80750,69000"
6806"90000,69000"
6807]
6808)
6809start &151
6810end &23
6811sat 32
6812eat 32
6813sty 1
6814stc 0
6815st 0
6816sf 1
6817si 0
6818tg (WTG
6819uid 446,0
6820ps "ConnStartEndStrategy"
6821stg "STSignalDisplayStrategy"
6822f (Text
6823uid 447,0
6824va (VaSet
6825isHidden 1
6826)
6827xt "82000,68000,84100,69000"
6828st "W_D"
6829blo "82000,68800"
6830tm "WireNameMgr"
6831)
6832)
6833on &71
6834)
6835*211 (Wire
6836uid 450,0
6837shape (OrthoPolyLine
6838uid 451,0
6839va (VaSet
6840vasetType 3
6841)
6842xt "80750,74000,90000,74000"
6843pts [
6844"90000,74000"
6845"80750,74000"
6846]
6847)
6848start &24
6849end &155
6850sat 32
6851eat 32
6852stc 0
6853st 0
6854sf 1
6855si 0
6856tg (WTG
6857uid 454,0
6858ps "ConnStartEndStrategy"
6859stg "STSignalDisplayStrategy"
6860f (Text
6861uid 455,0
6862va (VaSet
6863isHidden 1
6864)
6865xt "82000,73000,84800,74000"
6866st "W_INT"
6867blo "82000,73800"
6868tm "WireNameMgr"
6869)
6870)
6871on &75
6872)
6873*212 (Wire
6874uid 458,0
6875shape (OrthoPolyLine
6876uid 459,0
6877va (VaSet
6878vasetType 3
6879)
6880xt "80750,72000,90000,72000"
6881pts [
6882"80750,72000"
6883"90000,72000"
6884]
6885)
6886start &154
6887end &25
6888sat 32
6889eat 32
6890stc 0
6891st 0
6892sf 1
6893si 0
6894tg (WTG
6895uid 462,0
6896ps "ConnStartEndStrategy"
6897stg "STSignalDisplayStrategy"
6898f (Text
6899uid 463,0
6900va (VaSet
6901isHidden 1
6902)
6903xt "82000,71000,84700,72000"
6904st "W_RD"
6905blo "82000,71800"
6906tm "WireNameMgr"
6907)
6908)
6909on &73
6910)
6911*213 (Wire
6912uid 466,0
6913shape (OrthoPolyLine
6914uid 467,0
6915va (VaSet
6916vasetType 3
6917)
6918xt "80750,73000,90000,73000"
6919pts [
6920"80750,73000"
6921"90000,73000"
6922]
6923)
6924start &153
6925end &26
6926sat 32
6927eat 32
6928stc 0
6929st 0
6930sf 1
6931si 0
6932tg (WTG
6933uid 470,0
6934ps "ConnStartEndStrategy"
6935stg "STSignalDisplayStrategy"
6936f (Text
6937uid 471,0
6938va (VaSet
6939isHidden 1
6940)
6941xt "82000,72000,84800,73000"
6942st "W_WR"
6943blo "82000,72800"
6944tm "WireNameMgr"
6945)
6946)
6947on &74
6948)
6949*214 (Wire
6950uid 1467,0
6951shape (OrthoPolyLine
6952uid 1468,0
6953va (VaSet
6954vasetType 3
6955)
6956xt "30000,95000,51250,95000"
6957pts [
6958"30000,95000"
6959"41000,95000"
6960"51250,95000"
6961]
6962)
6963start &43
6964end &160
6965sat 2
6966eat 32
6967st 0
6968sf 1
6969si 0
6970tg (WTG
6971uid 1471,0
6972ps "ConnStartEndStrategy"
6973stg "STSignalDisplayStrategy"
6974f (Text
6975uid 1472,0
6976va (VaSet
6977)
6978xt "32000,94000,37900,95000"
6979st "adc_data_array"
6980blo "32000,94800"
6981tm "WireNameMgr"
6982)
6983)
6984on &27
6985)
6986*215 (Wire
6987uid 1730,0
6988shape (OrthoPolyLine
6989uid 1731,0
6990va (VaSet
6991vasetType 3
6992lineWidth 2
6993)
6994xt "21000,89000,51250,89000"
6995pts [
6996"21000,89000"
6997"51250,89000"
6998]
6999)
7000start &41
7001end &159
7002sat 32
7003eat 32
7004sty 1
7005stc 0
7006st 0
7007sf 1
7008si 0
7009tg (WTG
7010uid 1734,0
7011ps "ConnStartEndStrategy"
7012stg "STSignalDisplayStrategy"
7013f (Text
7014uid 1735,0
7015va (VaSet
7016isHidden 1
7017)
7018xt "22000,88000,25000,89000"
7019st "A_OTR"
7020blo "22000,88800"
7021tm "WireNameMgr"
7022)
7023)
7024on &42
7025)
7026*216 (Wire
7027uid 1833,0
7028shape (OrthoPolyLine
7029uid 1834,0
7030va (VaSet
7031vasetType 3
7032lineWidth 2
7033)
7034xt "21000,109000,51250,109000"
7035pts [
7036"51250,109000"
7037"21000,109000"
7038]
7039)
7040start &161
7041end &63
7042sat 32
7043eat 32
7044sty 1
7045stc 0
7046st 0
7047sf 1
7048si 0
7049tg (WTG
7050uid 1837,0
7051ps "ConnStartEndStrategy"
7052stg "STSignalDisplayStrategy"
7053f (Text
7054uid 1838,0
7055va (VaSet
7056isHidden 1
7057)
7058xt "22000,108000,23900,109000"
7059st "D_A"
7060blo "22000,108800"
7061tm "WireNameMgr"
7062)
7063)
7064on &64
7065)
7066*217 (Wire
7067uid 1841,0
7068shape (OrthoPolyLine
7069uid 1842,0
7070va (VaSet
7071vasetType 3
7072)
7073xt "21000,110000,51250,110000"
7074pts [
7075"51250,110000"
7076"21000,110000"
7077]
7078)
7079start &162
7080end &65
7081sat 32
7082eat 32
7083stc 0
7084st 0
7085sf 1
7086si 0
7087tg (WTG
7088uid 1845,0
7089ps "ConnStartEndStrategy"
7090stg "STSignalDisplayStrategy"
7091f (Text
7092uid 1846,0
7093va (VaSet
7094isHidden 1
7095)
7096xt "22000,109000,25500,110000"
7097st "DWRITE"
7098blo "22000,109800"
7099tm "WireNameMgr"
7100)
7101)
7102on &66
7103)
7104*218 (Wire
7105uid 1865,0
7106shape (OrthoPolyLine
7107uid 1866,0
7108va (VaSet
7109vasetType 3
7110)
7111xt "21000,105000,51250,105000"
7112pts [
7113"21000,105000"
7114"51250,105000"
7115]
7116)
7117start &55
7118end &163
7119sat 32
7120eat 32
7121stc 0
7122st 0
7123sf 1
7124si 0
7125tg (WTG
7126uid 1869,0
7127ps "ConnStartEndStrategy"
7128stg "STSignalDisplayStrategy"
7129f (Text
7130uid 1870,0
7131va (VaSet
7132isHidden 1
7133)
7134xt "22000,104000,26600,105000"
7135st "D0_SROUT"
7136blo "22000,104800"
7137tm "WireNameMgr"
7138)
7139)
7140on &59
7141)
7142*219 (Wire
7143uid 1873,0
7144shape (OrthoPolyLine
7145uid 1874,0
7146va (VaSet
7147vasetType 3
7148)
7149xt "21000,106000,51250,106000"
7150pts [
7151"21000,106000"
7152"51250,106000"
7153]
7154)
7155start &56
7156end &164
7157sat 32
7158eat 32
7159stc 0
7160st 0
7161sf 1
7162si 0
7163tg (WTG
7164uid 1877,0
7165ps "ConnStartEndStrategy"
7166stg "STSignalDisplayStrategy"
7167f (Text
7168uid 1878,0
7169va (VaSet
7170isHidden 1
7171)
7172xt "22000,105000,26600,106000"
7173st "D1_SROUT"
7174blo "22000,105800"
7175tm "WireNameMgr"
7176)
7177)
7178on &60
7179)
7180*220 (Wire
7181uid 1881,0
7182shape (OrthoPolyLine
7183uid 1882,0
7184va (VaSet
7185vasetType 3
7186)
7187xt "21000,107000,51250,107000"
7188pts [
7189"21000,107000"
7190"51250,107000"
7191]
7192)
7193start &57
7194end &165
7195sat 32
7196eat 32
7197stc 0
7198st 0
7199sf 1
7200si 0
7201tg (WTG
7202uid 1885,0
7203ps "ConnStartEndStrategy"
7204stg "STSignalDisplayStrategy"
7205f (Text
7206uid 1886,0
7207va (VaSet
7208isHidden 1
7209)
7210xt "22000,106000,26600,107000"
7211st "D2_SROUT"
7212blo "22000,106800"
7213tm "WireNameMgr"
7214)
7215)
7216on &61
7217)
7218*221 (Wire
7219uid 1889,0
7220shape (OrthoPolyLine
7221uid 1890,0
7222va (VaSet
7223vasetType 3
7224)
7225xt "21000,108000,51250,108000"
7226pts [
7227"21000,108000"
7228"51250,108000"
7229]
7230)
7231start &58
7232end &166
7233sat 32
7234eat 32
7235stc 0
7236st 0
7237sf 1
7238si 0
7239tg (WTG
7240uid 1893,0
7241ps "ConnStartEndStrategy"
7242stg "STSignalDisplayStrategy"
7243f (Text
7244uid 1894,0
7245va (VaSet
7246isHidden 1
7247)
7248xt "22000,107000,26600,108000"
7249st "D3_SROUT"
7250blo "22000,107800"
7251tm "WireNameMgr"
7252)
7253)
7254on &62
7255)
7256*222 (Wire
7257uid 2409,0
7258shape (OrthoPolyLine
7259uid 2410,0
7260va (VaSet
7261vasetType 3
7262)
7263xt "21000,111000,51250,111000"
7264pts [
7265"51250,111000"
7266"21000,111000"
7267]
7268)
7269start &167
7270end &29
7271sat 32
7272eat 32
7273stc 0
7274st 0
7275sf 1
7276si 0
7277tg (WTG
7278uid 2413,0
7279ps "ConnStartEndStrategy"
7280stg "STSignalDisplayStrategy"
7281f (Text
7282uid 2414,0
7283va (VaSet
7284isHidden 1
7285)
7286xt "22000,110000,26200,111000"
7287st "RSRLOAD"
7288blo "22000,110800"
7289tm "WireNameMgr"
7290)
7291)
7292on &28
7293)
7294*223 (Wire
7295uid 3009,0
7296shape (OrthoPolyLine
7297uid 3010,0
7298va (VaSet
7299vasetType 3
7300)
7301xt "80750,98000,90000,98000"
7302pts [
7303"80750,98000"
7304"90000,98000"
7305]
7306)
7307start &169
7308end &68
7309sat 32
7310eat 32
7311stc 0
7312st 0
7313sf 1
7314si 0
7315tg (WTG
7316uid 3011,0
7317ps "ConnStartEndStrategy"
7318stg "STSignalDisplayStrategy"
7319f (Text
7320uid 3012,0
7321va (VaSet
7322isHidden 1
7323)
7324xt "82000,97000,84800,98000"
7325st "S_CLK"
7326blo "82000,97800"
7327tm "WireNameMgr"
7328)
7329)
7330on &69
7331)
7332*224 (Wire
7333uid 3015,0
7334shape (OrthoPolyLine
7335uid 3016,0
7336va (VaSet
7337vasetType 3
7338)
7339xt "80750,99000,90000,99000"
7340pts [
7341"80750,99000"
7342"90000,99000"
7343]
7344)
7345start &170
7346end &77
7347sat 32
7348eat 32
7349stc 0
7350st 0
7351sf 1
7352si 0
7353tg (WTG
7354uid 3017,0
7355ps "ConnStartEndStrategy"
7356stg "STSignalDisplayStrategy"
7357f (Text
7358uid 3018,0
7359va (VaSet
7360isHidden 1
7361)
7362xt "82750,98000,85150,99000"
7363st "MISO"
7364blo "82750,98800"
7365tm "WireNameMgr"
7366)
7367)
7368on &80
7369)
7370*225 (Wire
7371uid 3027,0
7372shape (OrthoPolyLine
7373uid 3028,0
7374va (VaSet
7375vasetType 3
7376)
7377xt "80750,87000,90000,87000"
7378pts [
7379"80750,87000"
7380"90000,87000"
7381]
7382)
7383start &171
7384end &67
7385sat 32
7386eat 32
7387stc 0
7388st 0
7389sf 1
7390si 0
7391tg (WTG
7392uid 3031,0
7393ps "ConnStartEndStrategy"
7394stg "STSignalDisplayStrategy"
7395f (Text
7396uid 3032,0
7397va (VaSet
7398isHidden 1
7399)
7400xt "82000,86000,85600,87000"
7401st "DAC_CS"
7402blo "82000,86800"
7403tm "WireNameMgr"
7404)
7405)
7406on &30
7407)
7408*226 (Wire
7409uid 3218,0
7410shape (OrthoPolyLine
7411uid 3219,0
7412va (VaSet
7413vasetType 3
7414)
7415xt "22000,78000,51250,78000"
7416pts [
7417"22000,78000"
7418"51250,78000"
7419]
7420)
7421start &12
7422end &146
7423sat 32
7424eat 32
7425stc 0
7426st 0
7427sf 1
7428si 0
7429tg (WTG
7430uid 3220,0
7431ps "ConnStartEndStrategy"
7432stg "STSignalDisplayStrategy"
7433f (Text
7434uid 3221,0
7435va (VaSet
7436isHidden 1
7437)
7438xt "33000,77000,35100,78000"
7439st "TRG"
7440blo "33000,77800"
7441tm "WireNameMgr"
7442)
7443)
7444on &33
7445)
7446*227 (Wire
7447uid 3260,0
7448shape (OrthoPolyLine
7449uid 3261,0
7450va (VaSet
7451vasetType 3
7452lineWidth 2
7453)
7454xt "-1000,71000,5000,71000"
7455pts [
7456"-1000,71000"
7457"5000,71000"
7458]
7459)
7460start &31
7461end &34
7462sat 32
7463eat 2
7464sty 1
7465stc 0
7466st 0
7467sf 1
7468si 0
7469tg (WTG
7470uid 3264,0
7471ps "ConnStartEndStrategy"
7472stg "STSignalDisplayStrategy"
7473f (Text
7474uid 3265,0
7475va (VaSet
7476isHidden 1
7477)
7478xt "-23000,70000,-20200,71000"
7479st "A_CLK"
7480blo "-23000,70800"
7481tm "WireNameMgr"
7482)
7483)
7484on &38
7485)
7486*228 (Wire
7487uid 3318,0
7488shape (OrthoPolyLine
7489uid 3319,0
7490va (VaSet
7491vasetType 3
7492lineWidth 2
7493)
7494xt "21000,95000,24000,95000"
7495pts [
7496"21000,95000"
7497"24000,95000"
7498]
7499)
7500start &47
7501end &43
7502sat 32
7503eat 1
7504sty 1
7505stc 0
7506st 0
7507sf 1
7508si 0
7509tg (WTG
7510uid 3322,0
7511ps "ConnStartEndStrategy"
7512stg "STSignalDisplayStrategy"
7513f (Text
7514uid 3323,0
7515va (VaSet
7516isHidden 1
7517)
7518xt "23000,94000,25300,95000"
7519st "A0_D"
7520blo "23000,94800"
7521tm "WireNameMgr"
7522)
7523)
7524on &51
7525)
7526*229 (Wire
7527uid 3352,0
7528shape (OrthoPolyLine
7529uid 3353,0
7530va (VaSet
7531vasetType 3
7532lineWidth 2
7533)
7534xt "21000,96000,24000,96000"
7535pts [
7536"21000,96000"
7537"24000,96000"
7538]
7539)
7540start &48
7541end &43
7542sat 32
7543eat 1
7544sty 1
7545stc 0
7546st 0
7547sf 1
7548si 0
7549tg (WTG
7550uid 3356,0
7551ps "ConnStartEndStrategy"
7552stg "STSignalDisplayStrategy"
7553f (Text
7554uid 3357,0
7555va (VaSet
7556isHidden 1
7557)
7558xt "23000,95000,25300,96000"
7559st "A1_D"
7560blo "23000,95800"
7561tm "WireNameMgr"
7562)
7563)
7564on &52
7565)
7566*230 (Wire
7567uid 3360,0
7568shape (OrthoPolyLine
7569uid 3361,0
7570va (VaSet
7571vasetType 3
7572lineWidth 2
7573)
7574xt "21000,97000,24000,97000"
7575pts [
7576"21000,97000"
7577"24000,97000"
7578]
7579)
7580start &49
7581end &43
7582sat 32
7583eat 1
7584sty 1
7585stc 0
7586st 0
7587sf 1
7588si 0
7589tg (WTG
7590uid 3364,0
7591ps "ConnStartEndStrategy"
7592stg "STSignalDisplayStrategy"
7593f (Text
7594uid 3365,0
7595va (VaSet
7596isHidden 1
7597)
7598xt "23000,96000,25300,97000"
7599st "A2_D"
7600blo "23000,96800"
7601tm "WireNameMgr"
7602)
7603)
7604on &53
7605)
7606*231 (Wire
7607uid 3368,0
7608shape (OrthoPolyLine
7609uid 3369,0
7610va (VaSet
7611vasetType 3
7612lineWidth 2
7613)
7614xt "21000,98000,24000,98000"
7615pts [
7616"21000,98000"
7617"24000,98000"
7618]
7619)
7620start &50
7621end &43
7622sat 32
7623eat 1
7624sty 1
7625stc 0
7626st 0
7627sf 1
7628si 0
7629tg (WTG
7630uid 3372,0
7631ps "ConnStartEndStrategy"
7632stg "STSignalDisplayStrategy"
7633f (Text
7634uid 3373,0
7635va (VaSet
7636isHidden 1
7637)
7638xt "23000,97000,25300,98000"
7639st "A3_D"
7640blo "23000,97800"
7641tm "WireNameMgr"
7642)
7643)
7644on &54
7645)
7646*232 (Wire
7647uid 3682,0
7648shape (OrthoPolyLine
7649uid 3683,0
7650va (VaSet
7651vasetType 3
7652)
7653xt "80750,100000,90000,100000"
7654pts [
7655"80750,100000"
7656"90000,100000"
7657]
7658)
7659start &173
7660end &79
7661sat 32
7662eat 32
7663stc 0
7664st 0
7665sf 1
7666si 0
7667tg (WTG
7668uid 3686,0
7669ps "ConnStartEndStrategy"
7670stg "STSignalDisplayStrategy"
7671f (Text
7672uid 3687,0
7673va (VaSet
7674isHidden 1
7675)
7676xt "82000,99000,84400,100000"
7677st "MOSI"
7678blo "82000,99800"
7679tm "WireNameMgr"
7680)
7681)
7682on &78
7683)
7684*233 (Wire
7685uid 3834,0
7686shape (OrthoPolyLine
7687uid 3835,0
7688va (VaSet
7689vasetType 3
7690)
7691xt "171000,136000,176000,136000"
7692pts [
7693"176000,136000"
7694"171000,136000"
7695]
7696)
7697start &86
7698end &102
7699sat 32
7700eat 2
7701stc 0
7702st 0
7703sf 1
7704si 0
7705tg (WTG
7706uid 3838,0
7707ps "ConnStartEndStrategy"
7708stg "STSignalDisplayStrategy"
7709f (Text
7710uid 3839,0
7711va (VaSet
7712isHidden 1
7713)
7714xt "171000,135000,173900,136000"
7715st "EE_CS"
7716blo "171000,135800"
7717tm "WireNameMgr"
7718)
7719)
7720on &92
7721)
7722*234 (Wire
7723uid 4942,0
7724shape (OrthoPolyLine
7725uid 4943,0
7726va (VaSet
7727vasetType 3
7728lineWidth 2
7729)
7730xt "171000,104000,176000,104000"
7731pts [
7732"171000,104000"
7733"176000,104000"
7734]
7735)
7736start &102
7737end &93
7738sat 2
7739eat 32
7740sty 1
7741stc 0
7742st 0
7743sf 1
7744si 0
7745tg (WTG
7746uid 4948,0
7747ps "ConnStartEndStrategy"
7748stg "STSignalDisplayStrategy"
7749f (Text
7750uid 4949,0
7751va (VaSet
7752isHidden 1
7753)
7754xt "172750,101000,174650,102000"
7755st "D_T"
7756blo "172750,101800"
7757tm "WireNameMgr"
7758)
7759)
7760on &94
7761)
7762*235 (Wire
7763uid 6431,0
7764shape (OrthoPolyLine
7765uid 6432,0
7766va (VaSet
7767vasetType 3
7768)
7769xt "80750,121000,82000,121000"
7770pts [
7771"80750,121000"
7772"82000,121000"
7773]
7774)
7775start &174
7776end &85
7777sat 32
7778eat 32
7779stc 0
7780st 0
7781sf 1
7782si 0
7783tg (WTG
7784uid 6435,0
7785ps "ConnStartEndStrategy"
7786stg "STSignalDisplayStrategy"
7787f (Text
7788uid 6436,0
7789va (VaSet
7790isHidden 1
7791)
7792xt "92000,120000,96000,121000"
7793st "DENABLE"
7794blo "92000,120800"
7795tm "WireNameMgr"
7796)
7797)
7798on &91
7799)
7800*236 (Wire
7801uid 7144,0
7802shape (OrthoPolyLine
7803uid 7145,0
7804va (VaSet
7805vasetType 3
7806lineWidth 2
7807)
7808xt "171000,106000,176000,106000"
7809pts [
7810"171000,106000"
7811"176000,106000"
7812]
7813)
7814start &102
7815end &97
7816sat 2
7817eat 32
7818sty 1
7819st 0
7820sf 1
7821si 0
7822tg (WTG
7823uid 7148,0
7824ps "ConnStartEndStrategy"
7825stg "STSignalDisplayStrategy"
7826f (Text
7827uid 7149,0
7828va (VaSet
7829isHidden 1
7830)
7831xt "176000,118000,180800,119000"
7832st "A1_T : (7:0)"
7833blo "176000,118800"
7834tm "WireNameMgr"
7835)
7836)
7837on &98
7838)
7839*237 (Wire
7840uid 9502,0
7841shape (OrthoPolyLine
7842uid 9503,0
7843va (VaSet
7844vasetType 3
7845)
7846xt "80750,116000,85000,116000"
7847pts [
7848"80750,116000"
7849"85000,116000"
7850]
7851)
7852start &157
7853sat 32
7854eat 16
7855st 0
7856sf 1
7857si 0
7858tg (WTG
7859uid 9506,0
7860ps "ConnStartEndStrategy"
7861stg "STSignalDisplayStrategy"
7862f (Text
7863uid 9507,0
7864va (VaSet
7865)
7866xt "86000,115000,89100,116000"
7867st "CLK_50"
7868blo "86000,115800"
7869tm "WireNameMgr"
7870)
7871)
7872on &99
7873)
7874*238 (Wire
7875uid 10302,0
7876shape (OrthoPolyLine
7877uid 10303,0
7878va (VaSet
7879vasetType 3
7880lineWidth 2
7881)
7882xt "171000,111000,176000,111000"
7883pts [
7884"171000,111000"
7885"176000,111000"
7886]
7887)
7888start &102
7889end &100
7890sat 2
7891eat 32
7892sty 1
7893st 0
7894sf 1
7895si 0
7896tg (WTG
7897uid 10306,0
7898ps "ConnStartEndStrategy"
7899stg "STSignalDisplayStrategy"
7900f (Text
7901uid 10307,0
7902va (VaSet
7903isHidden 1
7904)
7905xt "172000,130000,176800,131000"
7906st "A0_T : (7:0)"
7907blo "172000,130800"
7908tm "WireNameMgr"
7909)
7910)
7911on &101
7912)
7913*239 (Wire
7914uid 11096,0
7915shape (OrthoPolyLine
7916uid 11097,0
7917va (VaSet
7918vasetType 3
7919)
7920xt "163000,129000,165000,129000"
7921pts [
7922"163000,129000"
7923"165000,129000"
7924]
7925)
7926start &106
7927end &102
7928sat 32
7929eat 1
7930st 0
7931sf 1
7932si 0
7933tg (WTG
7934uid 11100,0
7935ps "ConnStartEndStrategy"
7936stg "STSignalDisplayStrategy"
7937f (Text
7938uid 11101,0
7939va (VaSet
7940isHidden 1
7941)
7942xt "193000,122000,198300,123000"
7943st "RS485_C_DI"
7944blo "193000,122800"
7945tm "WireNameMgr"
7946)
7947)
7948on &107
7949)
7950*240 (Wire
7951uid 11514,0
7952shape (OrthoPolyLine
7953uid 11515,0
7954va (VaSet
7955vasetType 3
7956)
7957xt "80750,150000,85000,150000"
7958pts [
7959"85000,150000"
7960"80750,150000"
7961]
7962)
7963start &110
7964end &187
7965es 0
7966sat 32
7967eat 32
7968st 0
7969sf 1
7970si 0
7971tg (WTG
7972uid 11518,0
7973ps "ConnStartEndStrategy"
7974stg "STSignalDisplayStrategy"
7975f (Text
7976uid 11519,0
7977va (VaSet
7978isHidden 1
7979)
7980xt "86000,149000,91200,150000"
7981st "RS485_E_DI"
7982blo "86000,149800"
7983tm "WireNameMgr"
7984)
7985)
7986on &111
7987)
7988*241 (Wire
7989uid 11528,0
7990shape (OrthoPolyLine
7991uid 11529,0
7992va (VaSet
7993vasetType 3
7994)
7995xt "80750,149000,85000,149000"
7996pts [
7997"80750,149000"
7998"85000,149000"
7999]
8000)
8001start &189
8002end &128
8003ss 0
8004sat 32
8005eat 32
8006st 0
8007sf 1
8008si 0
8009tg (WTG
8010uid 11532,0
8011ps "ConnStartEndStrategy"
8012stg "STSignalDisplayStrategy"
8013f (Text
8014uid 11533,0
8015va (VaSet
8016isHidden 1
8017)
8018xt "107000,148000,112600,149000"
8019st "RS485_E_DO"
8020blo "107000,148800"
8021tm "WireNameMgr"
8022)
8023)
8024on &112
8025)
8026*242 (Wire
8027uid 12320,0
8028shape (OrthoPolyLine
8029uid 12321,0
8030va (VaSet
8031vasetType 3
8032)
8033xt "80750,140000,87000,140000"
8034pts [
8035"80750,140000"
8036"87000,140000"
8037]
8038)
8039start &175
8040end &113
8041sat 32
8042eat 32
8043stc 0
8044st 0
8045sf 1
8046si 0
8047tg (WTG
8048uid 12324,0
8049ps "ConnStartEndStrategy"
8050stg "STSignalDisplayStrategy"
8051f (Text
8052uid 12325,0
8053va (VaSet
8054isHidden 1
8055)
8056xt "82000,139000,84300,140000"
8057st "SRIN"
8058blo "82000,139800"
8059tm "WireNameMgr"
8060)
8061)
8062on &114
8063)
8064*243 (Wire
8065uid 12545,0
8066shape (OrthoPolyLine
8067uid 12546,0
8068va (VaSet
8069vasetType 3
8070)
8071xt "80750,141000,87000,141000"
8072pts [
8073"80750,141000"
8074"87000,141000"
8075]
8076)
8077start &177
8078end &115
8079sat 32
8080eat 32
8081st 0
8082sf 1
8083si 0
8084tg (WTG
8085uid 12549,0
8086ps "ConnStartEndStrategy"
8087stg "STSignalDisplayStrategy"
8088f (Text
8089uid 12550,0
8090va (VaSet
8091isHidden 1
8092)
8093xt "83000,140000,88100,141000"
8094st "AMBER_LED"
8095blo "83000,140800"
8096tm "WireNameMgr"
8097)
8098)
8099on &118
8100)
8101*244 (Wire
8102uid 12559,0
8103shape (OrthoPolyLine
8104uid 12560,0
8105va (VaSet
8106vasetType 3
8107)
8108xt "80750,142000,87000,143000"
8109pts [
8110"80750,143000"
8111"87000,142000"
8112]
8113)
8114start &178
8115end &116
8116sat 32
8117eat 32
8118st 0
8119sf 1
8120si 0
8121tg (WTG
8122uid 12563,0
8123ps "ConnStartEndStrategy"
8124stg "STSignalDisplayStrategy"
8125f (Text
8126uid 12564,0
8127va (VaSet
8128isHidden 1
8129)
8130xt "83000,142000,88100,143000"
8131st "GREEN_LED"
8132blo "83000,142800"
8133tm "WireNameMgr"
8134)
8135)
8136on &119
8137)
8138*245 (Wire
8139uid 12573,0
8140shape (OrthoPolyLine
8141uid 12574,0
8142va (VaSet
8143vasetType 3
8144)
8145xt "80750,142000,87000,143000"
8146pts [
8147"80750,142000"
8148"87000,143000"
8149]
8150)
8151start &176
8152end &117
8153sat 32
8154eat 32
8155st 0
8156sf 1
8157si 0
8158tg (WTG
8159uid 12577,0
8160ps "ConnStartEndStrategy"
8161stg "STSignalDisplayStrategy"
8162f (Text
8163uid 12578,0
8164va (VaSet
8165isHidden 1
8166)
8167xt "83000,141000,87000,142000"
8168st "RED_LED"
8169blo "83000,141800"
8170tm "WireNameMgr"
8171)
8172)
8173on &120
8174)
8175*246 (Wire
8176uid 13522,0
8177shape (OrthoPolyLine
8178uid 13523,0
8179va (VaSet
8180vasetType 3
8181lineWidth 2
8182)
8183xt "22000,81000,28000,81000"
8184pts [
8185"22000,81000"
8186"28000,81000"
8187]
8188)
8189start &121
8190end &14
8191sat 32
8192eat 1
8193sty 1
8194st 0
8195sf 1
8196si 0
8197tg (WTG
8198uid 13526,0
8199ps "ConnStartEndStrategy"
8200stg "STSignalDisplayStrategy"
8201f (Text
8202uid 13527,0
8203va (VaSet
8204)
8205xt "22000,80000,26700,81000"
8206st "LINE : (5:0)"
8207blo "22000,80800"
8208tm "WireNameMgr"
8209)
8210)
8211on &122
8212)
8213*247 (Wire
8214uid 13618,0
8215shape (OrthoPolyLine
8216uid 13619,0
8217va (VaSet
8218vasetType 3
8219lineWidth 2
8220)
8221xt "171000,125000,176000,125000"
8222pts [
8223"171000,125000"
8224"176000,125000"
8225]
8226)
8227start &102
8228end &95
8229sat 2
8230eat 32
8231sty 1
8232st 0
8233sf 1
8234si 0
8235tg (WTG
8236uid 13624,0
8237ps "ConnStartEndStrategy"
8238stg "STSignalDisplayStrategy"
8239f (Text
8240uid 13625,0
8241va (VaSet
8242isHidden 1
8243)
8244xt "173000,130000,177900,131000"
8245st "D_T2 : (1:0)"
8246blo "173000,130800"
8247tm "WireNameMgr"
8248)
8249)
8250on &96
8251)
8252*248 (Wire
8253uid 13634,0
8254shape (OrthoPolyLine
8255uid 13635,0
8256va (VaSet
8257vasetType 3
8258)
8259xt "49000,133000,51250,133000"
8260pts [
8261"49000,133000"
8262"51250,133000"
8263]
8264)
8265start &123
8266end &180
8267sat 32
8268eat 32
8269st 0
8270sf 1
8271si 0
8272tg (WTG
8273uid 13638,0
8274ps "ConnStartEndStrategy"
8275stg "STSignalDisplayStrategy"
8276f (Text
8277uid 13639,0
8278va (VaSet
8279isHidden 1
8280)
8281xt "51000,141000,54500,142000"
8282st "REFCLK"
8283blo "51000,141800"
8284tm "WireNameMgr"
8285)
8286)
8287on &124
8288)
8289*249 (Wire
8290uid 13658,0
8291shape (OrthoPolyLine
8292uid 13659,0
8293va (VaSet
8294vasetType 3
8295)
8296xt "80750,147000,85000,147000"
8297pts [
8298"80750,147000"
8299"85000,147000"
8300]
8301)
8302start &190
8303end &84
8304ss 0
8305sat 32
8306eat 32
8307st 0
8308sf 1
8309si 0
8310tg (WTG
8311uid 13664,0
8312ps "ConnStartEndStrategy"
8313stg "STSignalDisplayStrategy"
8314f (Text
8315uid 13665,0
8316va (VaSet
8317isHidden 1
8318)
8319xt "84000,145000,89500,146000"
8320st "RS485_E_DE"
8321blo "84000,145800"
8322tm "WireNameMgr"
8323)
8324)
8325on &90
8326)
8327*250 (Wire
8328uid 14328,0
8329shape (OrthoPolyLine
8330uid 14329,0
8331va (VaSet
8332vasetType 3
8333lineWidth 2
8334)
8335xt "49000,132000,51250,132000"
8336pts [
8337"49000,132000"
8338"51250,132000"
8339]
8340)
8341start &125
8342end &179
8343sat 32
8344eat 32
8345sty 1
8346st 0
8347sf 1
8348si 0
8349tg (WTG
8350uid 14332,0
8351ps "ConnStartEndStrategy"
8352stg "STSignalDisplayStrategy"
8353f (Text
8354uid 14333,0
8355va (VaSet
8356isHidden 1
8357)
8358xt "52000,138000,57500,139000"
8359st "D_T_in : (1:0)"
8360blo "52000,138800"
8361tm "WireNameMgr"
8362)
8363)
8364on &126
8365)
8366*251 (Wire
8367uid 15175,0
8368shape (OrthoPolyLine
8369uid 15176,0
8370va (VaSet
8371vasetType 3
8372lineWidth 2
8373)
8374xt "80750,120000,87000,120000"
8375pts [
8376"80750,120000"
8377"87000,120000"
8378]
8379)
8380start &145
8381sat 32
8382eat 16
8383sty 1
8384st 0
8385sf 1
8386si 0
8387tg (WTG
8388uid 15179,0
8389ps "ConnStartEndStrategy"
8390stg "STSignalDisplayStrategy"
8391f (Text
8392uid 15180,0
8393va (VaSet
8394)
8395xt "82000,119000,86000,120000"
8396st "led : (7:0)"
8397blo "82000,119800"
8398tm "WireNameMgr"
8399)
8400)
8401on &127
8402)
8403*252 (Wire
8404uid 15517,0
8405shape (OrthoPolyLine
8406uid 15518,0
8407va (VaSet
8408vasetType 3
8409)
8410xt "171000,128000,176000,128000"
8411pts [
8412"171000,128000"
8413"176000,128000"
8414]
8415)
8416start &102
8417end &81
8418sat 2
8419eat 32
8420st 0
8421sf 1
8422si 0
8423tg (WTG
8424uid 15523,0
8425ps "ConnStartEndStrategy"
8426stg "STSignalDisplayStrategy"
8427f (Text
8428uid 15524,0
8429va (VaSet
8430isHidden 1
8431)
8432xt "173000,127000,178600,128000"
8433st "RS485_C_DE"
8434blo "173000,127800"
8435tm "WireNameMgr"
8436)
8437)
8438on &88
8439)
8440*253 (Wire
8441uid 15525,0
8442shape (OrthoPolyLine
8443uid 15526,0
8444va (VaSet
8445vasetType 3
8446)
8447xt "171000,129000,176000,129000"
8448pts [
8449"171000,129000"
8450"176000,129000"
8451]
8452)
8453start &102
8454end &82
8455sat 2
8456eat 32
8457st 0
8458sf 1
8459si 0
8460tg (WTG
8461uid 15531,0
8462ps "ConnStartEndStrategy"
8463stg "STSignalDisplayStrategy"
8464f (Text
8465uid 15532,0
8466va (VaSet
8467isHidden 1
8468)
8469xt "173000,128000,178700,129000"
8470st "RS485_C_DO"
8471blo "173000,128800"
8472tm "WireNameMgr"
8473)
8474)
8475on &109
8476)
8477*254 (Wire
8478uid 15533,0
8479shape (OrthoPolyLine
8480uid 15534,0
8481va (VaSet
8482vasetType 3
8483)
8484xt "171000,130000,176000,130000"
8485pts [
8486"171000,130000"
8487"176000,130000"
8488]
8489)
8490start &102
8491end &108
8492sat 2
8493eat 32
8494st 0
8495sf 1
8496si 0
8497tg (WTG
8498uid 15539,0
8499ps "ConnStartEndStrategy"
8500stg "STSignalDisplayStrategy"
8501f (Text
8502uid 15540,0
8503va (VaSet
8504isHidden 1
8505)
8506xt "173000,129000,178600,130000"
8507st "RS485_C_RE"
8508blo "173000,129800"
8509tm "WireNameMgr"
8510)
8511)
8512on &87
8513)
8514*255 (Wire
8515uid 15541,0
8516shape (OrthoPolyLine
8517uid 15542,0
8518va (VaSet
8519vasetType 3
8520lineWidth 2
8521)
8522xt "157000,111000,165000,111000"
8523pts [
8524"157000,111000"
8525"165000,111000"
8526]
8527)
8528end &102
8529sat 16
8530eat 1
8531sty 1
8532st 0
8533sf 1
8534si 0
8535tg (WTG
8536uid 15547,0
8537ps "ConnStartEndStrategy"
8538stg "STSignalDisplayStrategy"
8539f (Text
8540uid 15548,0
8541va (VaSet
8542)
8543xt "159000,110000,163000,111000"
8544st "led : (7:0)"
8545blo "159000,110800"
8546tm "WireNameMgr"
8547)
8548)
8549on &127
8550)
8551*256 (Wire
8552uid 15563,0
8553shape (OrthoPolyLine
8554uid 15564,0
8555va (VaSet
8556vasetType 3
8557)
8558xt "80750,148000,85000,148000"
8559pts [
8560"80750,148000"
8561"85000,148000"
8562]
8563)
8564start &188
8565end &83
8566ss 0
8567sat 32
8568eat 32
8569st 0
8570sf 1
8571si 0
8572tg (WTG
8573uid 15569,0
8574ps "ConnStartEndStrategy"
8575stg "STSignalDisplayStrategy"
8576f (Text
8577uid 15570,0
8578va (VaSet
8579isHidden 1
8580)
8581xt "83000,147000,88500,148000"
8582st "RS485_E_RE"
8583blo "83000,147800"
8584tm "WireNameMgr"
8585)
8586)
8587on &89
8588)
8589*257 (Wire
8590uid 15712,0
8591shape (OrthoPolyLine
8592uid 15713,0
8593va (VaSet
8594vasetType 3
8595lineWidth 2
8596)
8597xt "49000,137000,51250,137000"
8598pts [
8599"49000,137000"
8600"51250,137000"
8601]
8602)
8603start &129
8604end &181
8605sat 32
8606eat 32
8607sty 1
8608st 0
8609sf 1
8610si 0
8611tg (WTG
8612uid 15716,0
8613ps "ConnStartEndStrategy"
8614stg "STSignalDisplayStrategy"
8615f (Text
8616uid 15717,0
8617va (VaSet
8618isHidden 1
8619)
8620xt "51000,136000,57800,137000"
8621st "D_PLLLCK : (3:0)"
8622blo "51000,136800"
8623tm "WireNameMgr"
8624)
8625)
8626on &130
8627)
8628*258 (Wire
8629uid 15851,0
8630shape (OrthoPolyLine
8631uid 15852,0
8632va (VaSet
8633vasetType 3
8634lineWidth 2
8635)
8636xt "80750,89000,90000,89000"
8637pts [
8638"80750,89000"
8639"90000,89000"
8640]
8641)
8642start &172
8643end &131
8644sat 32
8645eat 32
8646sty 1
8647st 0
8648sf 1
8649si 0
8650tg (WTG
8651uid 15855,0
8652ps "ConnStartEndStrategy"
8653stg "STSignalDisplayStrategy"
8654f (Text
8655uid 15856,0
8656va (VaSet
8657isHidden 1
8658)
8659xt "83000,88000,87600,89000"
8660st "TCS : (3:0)"
8661blo "83000,88800"
8662tm "WireNameMgr"
8663)
8664)
8665on &132
8666)
8667*259 (Wire
8668uid 16063,0
8669shape (OrthoPolyLine
8670uid 16064,0
8671va (VaSet
8672vasetType 3
8673lineWidth 2
8674)
8675xt "21000,113000,30000,113000"
8676pts [
8677"30000,113000"
8678"21000,113000"
8679]
8680)
8681start &136
8682end &133
8683sat 2
8684eat 32
8685sty 1
8686st 0
8687sf 1
8688si 0
8689tg (WTG
8690uid 16067,0
8691ps "ConnStartEndStrategy"
8692stg "STSignalDisplayStrategy"
8693f (Text
8694uid 16068,0
8695va (VaSet
8696isHidden 1
8697)
8698xt "24000,112000,30200,113000"
8699st "DSRCLK : (3:0)"
8700blo "24000,112800"
8701tm "WireNameMgr"
8702)
8703)
8704on &134
8705)
8706*260 (Wire
8707uid 16247,0
8708shape (OrthoPolyLine
8709uid 16248,0
8710va (VaSet
8711vasetType 3
8712)
8713xt "34000,113000,51250,113000"
8714pts [
8715"51250,113000"
8716"34000,113000"
8717]
8718)
8719start &168
8720end &136
8721sat 32
8722eat 1
8723st 0
8724sf 1
8725si 0
8726tg (WTG
8727uid 16251,0
8728ps "ConnStartEndStrategy"
8729stg "STSignalDisplayStrategy"
8730f (Text
8731uid 16252,0
8732va (VaSet
8733)
8734xt "35000,112000,38000,113000"
8735st "SRCLK"
8736blo "35000,112800"
8737tm "WireNameMgr"
8738)
8739)
8740on &135
8741)
8742*261 (Wire
8743uid 16538,0
8744shape (OrthoPolyLine
8745uid 16539,0
8746va (VaSet
8747vasetType 3
8748)
8749xt "80750,130000,92000,130000"
8750pts [
8751"80750,130000"
8752"92000,130000"
8753]
8754)
8755start &183
8756sat 32
8757eat 16
8758st 0
8759sf 1
8760si 0
8761tg (WTG
8762uid 16542,0
8763ps "ConnStartEndStrategy"
8764stg "STSignalDisplayStrategy"
8765f (Text
8766uid 16543,0
8767va (VaSet
8768)
8769xt "82000,129000,90600,130000"
8770st "alarm_refclk_too_high"
8771blo "82000,129800"
8772tm "WireNameMgr"
8773)
8774)
8775on &140
8776)
8777*262 (Wire
8778uid 16546,0
8779shape (OrthoPolyLine
8780uid 16547,0
8781va (VaSet
8782vasetType 3
8783)
8784xt "80750,131000,91000,131000"
8785pts [
8786"80750,131000"
8787"91000,131000"
8788]
8789)
8790start &184
8791sat 32
8792eat 16
8793st 0
8794sf 1
8795si 0
8796tg (WTG
8797uid 16550,0
8798ps "ConnStartEndStrategy"
8799stg "STSignalDisplayStrategy"
8800f (Text
8801uid 16551,0
8802va (VaSet
8803)
8804xt "82000,130000,90200,131000"
8805st "alarm_refclk_too_low"
8806blo "82000,130800"
8807tm "WireNameMgr"
8808)
8809)
8810on &141
8811)
8812*263 (Wire
8813uid 16576,0
8814shape (OrthoPolyLine
8815uid 16577,0
8816va (VaSet
8817vasetType 3
8818lineWidth 2
8819)
8820xt "80750,132000,92000,132000"
8821pts [
8822"80750,132000"
8823"92000,132000"
8824]
8825)
8826start &182
8827sat 32
8828eat 16
8829sty 1
8830st 0
8831sf 1
8832si 0
8833tg (WTG
8834uid 16580,0
8835ps "ConnStartEndStrategy"
8836stg "STSignalDisplayStrategy"
8837f (Text
8838uid 16581,0
8839va (VaSet
8840)
8841xt "82000,131000,90600,132000"
8842st "counter_result : (11:0)"
8843blo "82000,131800"
8844tm "WireNameMgr"
8845)
8846)
8847on &142
8848)
8849*264 (Wire
8850uid 17296,0
8851shape (OrthoPolyLine
8852uid 17297,0
8853va (VaSet
8854vasetType 3
8855)
8856xt "13000,71000,51250,71000"
8857pts [
8858"51250,71000"
8859"13000,71000"
8860]
8861)
8862start &185
8863end &34
8864sat 32
8865eat 1
8866st 0
8867sf 1
8868si 0
8869tg (WTG
8870uid 17300,0
8871ps "ConnStartEndStrategy"
8872stg "STSignalDisplayStrategy"
8873f (Text
8874uid 17301,0
8875va (VaSet
8876)
8877xt "14000,70000,18000,71000"
8878st "ADC_CLK"
8879blo "14000,70800"
8880tm "WireNameMgr"
8881)
8882)
8883on &197
8884)
8885*265 (Wire
8886uid 17407,0
8887shape (OrthoPolyLine
8888uid 17408,0
8889va (VaSet
8890vasetType 3
8891)
8892xt "80750,144000,87000,144000"
8893pts [
8894"80750,144000"
8895"87000,144000"
8896]
8897)
8898start &186
8899end &198
8900sat 32
8901eat 32
8902st 0
8903sf 1
8904si 0
8905tg (WTG
8906uid 17411,0
8907ps "ConnStartEndStrategy"
8908stg "STSignalDisplayStrategy"
8909f (Text
8910uid 17412,0
8911va (VaSet
8912isHidden 1
8913)
8914xt "83000,143000,86000,144000"
8915st "TRG_V"
8916blo "83000,143800"
8917tm "WireNameMgr"
8918)
8919)
8920on &199
8921)
8922*266 (Wire
8923uid 17727,0
8924shape (OrthoPolyLine
8925uid 17728,0
8926va (VaSet
8927vasetType 3
8928)
8929xt "155000,130000,165000,130000"
8930pts [
8931"155000,130000"
8932"165000,130000"
8933]
8934)
8935end &102
8936sat 16
8937eat 1
8938st 0
8939sf 1
8940si 0
8941tg (WTG
8942uid 17733,0
8943ps "ConnStartEndStrategy"
8944stg "STSignalDisplayStrategy"
8945f (Text
8946uid 17734,0
8947va (VaSet
8948)
8949xt "157000,129000,167000,130000"
8950st "alarm_refclk_too_high"
8951blo "157000,129800"
8952tm "WireNameMgr"
8953)
8954)
8955on &140
8956)
8957*267 (Wire
8958uid 17735,0
8959shape (OrthoPolyLine
8960uid 17736,0
8961va (VaSet
8962vasetType 3
8963)
8964xt "155000,131000,165000,131000"
8965pts [
8966"155000,131000"
8967"165000,131000"
8968]
8969)
8970end &102
8971sat 16
8972eat 1
8973st 0
8974sf 1
8975si 0
8976tg (WTG
8977uid 17741,0
8978ps "ConnStartEndStrategy"
8979stg "STSignalDisplayStrategy"
8980f (Text
8981uid 17742,0
8982va (VaSet
8983)
8984xt "157000,130000,166600,131000"
8985st "alarm_refclk_too_low"
8986blo "157000,130800"
8987tm "WireNameMgr"
8988)
8989)
8990on &141
8991)
8992*268 (Wire
8993uid 17743,0
8994shape (OrthoPolyLine
8995uid 17744,0
8996va (VaSet
8997vasetType 3
8998)
8999xt "155000,132000,165000,132000"
9000pts [
9001"155000,132000"
9002"165000,132000"
9003]
9004)
9005end &102
9006sat 16
9007eat 1
9008st 0
9009sf 1
9010si 0
9011tg (WTG
9012uid 17749,0
9013ps "ConnStartEndStrategy"
9014stg "STSignalDisplayStrategy"
9015f (Text
9016uid 17750,0
9017va (VaSet
9018)
9019xt "157000,131000,166600,132000"
9020st "counter_result : (11:0)"
9021blo "157000,131800"
9022tm "WireNameMgr"
9023)
9024)
9025on &142
9026)
9027*269 (Wire
9028uid 17848,0
9029shape (OrthoPolyLine
9030uid 17849,0
9031va (VaSet
9032vasetType 3
9033lineWidth 2
9034)
9035xt "80750,106000,91000,106000"
9036pts [
9037"80750,106000"
9038"91000,106000"
9039]
9040)
9041start &191
9042sat 32
9043eat 16
9044sty 1
9045st 0
9046sf 1
9047si 0
9048tg (WTG
9049uid 17852,0
9050ps "ConnStartEndStrategy"
9051stg "STSignalDisplayStrategy"
9052f (Text
9053uid 17853,0
9054va (VaSet
9055)
9056xt "82000,105000,90400,106000"
9057st "w5300_state : (7:0)"
9058blo "82000,105800"
9059tm "WireNameMgr"
9060)
9061)
9062on &200
9063)
9064*270 (Wire
9065uid 17856,0
9066shape (OrthoPolyLine
9067uid 17857,0
9068va (VaSet
9069vasetType 3
9070)
9071xt "155000,135000,165000,135000"
9072pts [
9073"155000,135000"
9074"165000,135000"
9075]
9076)
9077end &102
9078sat 16
9079eat 1
9080st 0
9081sf 1
9082si 0
9083tg (WTG
9084uid 17862,0
9085ps "ConnStartEndStrategy"
9086stg "STSignalDisplayStrategy"
9087f (Text
9088uid 17863,0
9089va (VaSet
9090)
9091xt "157000,134000,165400,135000"
9092st "w5300_state : (7:0)"
9093blo "157000,134800"
9094tm "WireNameMgr"
9095)
9096)
9097on &200
9098)
9099*271 (Wire
9100uid 18068,0
9101shape (OrthoPolyLine
9102uid 18069,0
9103va (VaSet
9104vasetType 3
9105)
9106xt "80750,107000,93000,107000"
9107pts [
9108"80750,107000"
9109"93000,107000"
9110]
9111)
9112start &192
9113sat 32
9114eat 16
9115st 0
9116sf 1
9117si 0
9118tg (WTG
9119uid 18072,0
9120ps "ConnStartEndStrategy"
9121stg "STSignalDisplayStrategy"
9122f (Text
9123uid 18073,0
9124va (VaSet
9125)
9126xt "82000,106000,92400,107000"
9127st "debug_data_ram_empty"
9128blo "82000,106800"
9129tm "WireNameMgr"
9130)
9131)
9132on &201
9133)
9134*272 (Wire
9135uid 18076,0
9136shape (OrthoPolyLine
9137uid 18077,0
9138va (VaSet
9139vasetType 3
9140)
9141xt "80750,108000,91000,108000"
9142pts [
9143"80750,108000"
9144"91000,108000"
9145]
9146)
9147start &193
9148sat 32
9149eat 16
9150st 0
9151sf 1
9152si 0
9153tg (WTG
9154uid 18080,0
9155ps "ConnStartEndStrategy"
9156stg "STSignalDisplayStrategy"
9157f (Text
9158uid 18081,0
9159va (VaSet
9160)
9161xt "82000,107000,89500,108000"
9162st "debug_data_valid"
9163blo "82000,107800"
9164tm "WireNameMgr"
9165)
9166)
9167on &202
9168)
9169]
9170bg "65535,65535,65535"
9171grid (Grid
9172origin "0,0"
9173isVisible 1
9174isActive 1
9175xSpacing 1000
9176xySpacing 1000
9177xShown 1
9178yShown 1
9179color "26368,26368,26368"
9180)
9181packageList *273 (PackageList
9182uid 41,0
9183stg "VerticalLayoutStrategy"
9184textVec [
9185*274 (Text
9186uid 42,0
9187va (VaSet
9188font "arial,8,1"
9189)
9190xt "0,0,5400,1000"
9191st "Package List"
9192blo "0,800"
9193)
9194*275 (MLText
9195uid 43,0
9196va (VaSet
9197)
9198xt "0,1000,16100,9000"
9199st "LIBRARY ieee;
9200USE ieee.std_logic_1164.all;
9201USE ieee.std_logic_arith.all;
9202USE IEEE.NUMERIC_STD.all;
9203USE ieee.std_logic_unsigned.all;
9204
9205LIBRARY FACT_FAD_lib;
9206USE FACT_FAD_lib.fad_definitions.all;"
9207tm "PackageList"
9208)
9209]
9210)
9211compDirBlock (MlTextGroup
9212uid 44,0
9213stg "VerticalLayoutStrategy"
9214textVec [
9215*276 (Text
9216uid 45,0
9217va (VaSet
9218isHidden 1
9219font "Arial,8,1"
9220)
9221xt "20000,0,28100,1000"
9222st "Compiler Directives"
9223blo "20000,800"
9224)
9225*277 (Text
9226uid 46,0
9227va (VaSet
9228isHidden 1
9229font "Arial,8,1"
9230)
9231xt "20000,1000,29600,2000"
9232st "Pre-module directives:"
9233blo "20000,1800"
9234)
9235*278 (MLText
9236uid 47,0
9237va (VaSet
9238isHidden 1
9239)
9240xt "20000,2000,28200,4000"
9241st "`resetall
9242`timescale 1ns/10ps"
9243tm "BdCompilerDirectivesTextMgr"
9244)
9245*279 (Text
9246uid 48,0
9247va (VaSet
9248isHidden 1
9249font "Arial,8,1"
9250)
9251xt "20000,4000,30100,5000"
9252st "Post-module directives:"
9253blo "20000,4800"
9254)
9255*280 (MLText
9256uid 49,0
9257va (VaSet
9258isHidden 1
9259)
9260xt "20000,0,20000,0"
9261tm "BdCompilerDirectivesTextMgr"
9262)
9263*281 (Text
9264uid 50,0
9265va (VaSet
9266isHidden 1
9267font "Arial,8,1"
9268)
9269xt "20000,5000,29900,6000"
9270st "End-module directives:"
9271blo "20000,5800"
9272)
9273*282 (MLText
9274uid 51,0
9275va (VaSet
9276isHidden 1
9277)
9278xt "20000,6000,20000,6000"
9279tm "BdCompilerDirectivesTextMgr"
9280)
9281]
9282associable 1
9283)
9284windowSize "0,22,1681,1050"
9285viewArea "93768,63089,209266,135295"
9286cachedDiagramExtent "-23000,0,198300,153000"
9287pageSetupInfo (PageSetupInfo
9288ptrCmd ""
9289toPrinter 1
9290exportedDirectories [
9291"$HDS_PROJECT_DIR/HTMLExport"
9292]
9293exportStdIncludeRefs 1
9294exportStdPackageRefs 1
9295)
9296hasePageBreakOrigin 1
9297pageBreakOrigin "-73000,0"
9298lastUid 18085,0
9299defaultCommentText (CommentText
9300shape (Rectangle
9301layer 0
9302va (VaSet
9303vasetType 1
9304fg "65280,65280,46080"
9305lineColor "0,0,32768"
9306)
9307xt "0,0,15000,5000"
9308)
9309text (MLText
9310va (VaSet
9311fg "0,0,32768"
9312)
9313xt "200,200,2400,1200"
9314st "
9315Text
9316"
9317tm "CommentText"
9318wrapOption 3
9319visibleHeight 4600
9320visibleWidth 14600
9321)
9322)
9323defaultPanel (Panel
9324shape (RectFrame
9325va (VaSet
9326vasetType 1
9327fg "65535,65535,65535"
9328lineColor "32768,0,0"
9329lineWidth 2
9330)
9331xt "0,0,20000,20000"
9332)
9333title (TextAssociate
9334ps "TopLeftStrategy"
9335text (Text
9336va (VaSet
9337font "Arial,8,1"
9338)
9339xt "1000,1000,3800,2000"
9340st "Panel0"
9341blo "1000,1800"
9342tm "PanelText"
9343)
9344)
9345)
9346defaultBlk (Blk
9347shape (Rectangle
9348va (VaSet
9349vasetType 1
9350fg "39936,56832,65280"
9351lineColor "0,0,32768"
9352lineWidth 2
9353)
9354xt "0,0,8000,10000"
9355)
9356ttg (MlTextGroup
9357ps "CenterOffsetStrategy"
9358stg "VerticalLayoutStrategy"
9359textVec [
9360*283 (Text
9361va (VaSet
9362font "Arial,8,1"
9363)
9364xt "2200,3500,5800,4500"
9365st "<library>"
9366blo "2200,4300"
9367tm "BdLibraryNameMgr"
9368)
9369*284 (Text
9370va (VaSet
9371font "Arial,8,1"
9372)
9373xt "2200,4500,5600,5500"
9374st "<block>"
9375blo "2200,5300"
9376tm "BlkNameMgr"
9377)
9378*285 (Text
9379va (VaSet
9380font "Arial,8,1"
9381)
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10326*310 (GroupColHdr
10327tm "GroupColHdrMgr"
10328)
10329*311 (NameColHdr
10330tm "BlockDiagramNameColHdrMgr"
10331)
10332*312 (ModeColHdr
10333tm "BlockDiagramModeColHdrMgr"
10334)
10335*313 (TypeColHdr
10336tm "BlockDiagramTypeColHdrMgr"
10337)
10338*314 (BoundsColHdr
10339tm "BlockDiagramBoundsColHdrMgr"
10340)
10341*315 (InitColHdr
10342tm "BlockDiagramInitColHdrMgr"
10343)
10344*316 (EolColHdr
10345tm "BlockDiagramEolColHdrMgr"
10346)
10347*317 (LeafLogPort
10348port (LogicalPort
10349m 4
10350decl (Decl
10351n "board_id"
10352t "std_logic_vector"
10353b "(3 downto 0)"
10354preAdd 0
10355posAdd 0
10356o 73
10357suid 5,0
10358)
10359)
10360uid 327,0
10361)
10362*318 (LeafLogPort
10363port (LogicalPort
10364m 4
10365decl (Decl
10366n "crate_id"
10367t "std_logic_vector"
10368b "(1 downto 0)"
10369o 74
10370suid 6,0
10371)
10372)
10373uid 329,0
10374)
10375*319 (LeafLogPort
10376port (LogicalPort
10377m 4
10378decl (Decl
10379n "adc_data_array"
10380t "adc_data_array_type"
10381o 72
10382suid 29,0
10383)
10384)
10385uid 1491,0
10386)
10387*320 (LeafLogPort
10388port (LogicalPort
10389m 1
10390decl (Decl
10391n "RSRLOAD"
10392t "std_logic"
10393o 43
10394suid 57,0
10395i "'0'"
10396)
10397)
10398uid 2435,0
10399)
10400*321 (LeafLogPort
10401port (LogicalPort
10402m 1
10403decl (Decl
10404n "DAC_CS"
10405t "std_logic"
10406o 26
10407suid 66,0
10408)
10409)
10410uid 3039,0
10411)
10412*322 (LeafLogPort
10413port (LogicalPort
10414decl (Decl
10415n "X_50M"
10416t "STD_LOGIC"
10417preAdd 0
10418posAdd 0
10419o 17
10420suid 67,0
10421)
10422)
10423uid 3276,0
10424)
10425*323 (LeafLogPort
10426port (LogicalPort
10427decl (Decl
10428n "TRG"
10429t "STD_LOGIC"
10430o 15
10431suid 68,0
10432)
10433)
10434uid 3278,0
10435)
10436*324 (LeafLogPort
10437port (LogicalPort
10438m 1
10439decl (Decl
10440n "A_CLK"
10441t "std_logic_vector"
10442b "(3 downto 0)"
10443o 21
10444suid 71,0
10445)
10446)
10447uid 3280,0
10448)
10449*325 (LeafLogPort
10450port (LogicalPort
10451m 1
10452decl (Decl
10453n "OE_ADC"
10454t "STD_LOGIC"
10455preAdd 0
10456posAdd 0
10457o 35
10458suid 73,0
10459)
10460)
10461uid 3382,0
10462)
10463*326 (LeafLogPort
10464port (LogicalPort
10465decl (Decl
10466n "A_OTR"
10467t "std_logic_vector"
10468b "(3 DOWNTO 0)"
10469o 5
10470suid 74,0
10471)
10472)
10473uid 3384,0
10474)
10475*327 (LeafLogPort
10476port (LogicalPort
10477decl (Decl
10478n "A0_D"
10479t "std_logic_vector"
10480b "(11 DOWNTO 0)"
10481o 1
10482suid 79,0
10483)
10484)
10485uid 3386,0
10486)
10487*328 (LeafLogPort
10488port (LogicalPort
10489decl (Decl
10490n "A1_D"
10491t "std_logic_vector"
10492b "(11 DOWNTO 0)"
10493o 2
10494suid 80,0
10495)
10496)
10497uid 3388,0
10498)
10499*329 (LeafLogPort
10500port (LogicalPort
10501decl (Decl
10502n "A2_D"
10503t "std_logic_vector"
10504b "(11 DOWNTO 0)"
10505o 3
10506suid 81,0
10507)
10508)
10509uid 3390,0
10510)
10511*330 (LeafLogPort
10512port (LogicalPort
10513decl (Decl
10514n "A3_D"
10515t "std_logic_vector"
10516b "(11 DOWNTO 0)"
10517o 4
10518suid 82,0
10519)
10520)
10521uid 3392,0
10522)
10523*331 (LeafLogPort
10524port (LogicalPort
10525decl (Decl
10526n "D0_SROUT"
10527t "std_logic"
10528o 6
10529suid 91,0
10530)
10531)
10532uid 3524,0
10533)
10534*332 (LeafLogPort
10535port (LogicalPort
10536decl (Decl
10537n "D1_SROUT"
10538t "std_logic"
10539o 7
10540suid 92,0
10541)
10542)
10543uid 3526,0
10544)
10545*333 (LeafLogPort
10546port (LogicalPort
10547decl (Decl
10548n "D2_SROUT"
10549t "std_logic"
10550o 8
10551suid 93,0
10552)
10553)
10554uid 3528,0
10555)
10556*334 (LeafLogPort
10557port (LogicalPort
10558decl (Decl
10559n "D3_SROUT"
10560t "std_logic"
10561o 9
10562suid 94,0
10563)
10564)
10565uid 3530,0
10566)
10567*335 (LeafLogPort
10568port (LogicalPort
10569m 1
10570decl (Decl
10571n "D_A"
10572t "std_logic_vector"
10573b "(3 DOWNTO 0)"
10574o 29
10575suid 95,0
10576i "(others => '0')"
10577)
10578)
10579uid 3532,0
10580)
10581*336 (LeafLogPort
10582port (LogicalPort
10583m 1
10584decl (Decl
10585n "DWRITE"
10586t "std_logic"
10587o 28
10588suid 96,0
10589i "'0'"
10590)
10591)
10592uid 3534,0
10593)
10594*337 (LeafLogPort
10595port (LogicalPort
10596m 1
10597decl (Decl
10598n "S_CLK"
10599t "std_logic"
10600o 45
10601suid 105,0
10602)
10603)
10604uid 3654,0
10605)
10606*338 (LeafLogPort
10607port (LogicalPort
10608m 1
10609decl (Decl
10610n "W_A"
10611t "std_logic_vector"
10612b "(9 DOWNTO 0)"
10613o 51
10614suid 106,0
10615)
10616)
10617uid 3656,0
10618)
10619*339 (LeafLogPort
10620port (LogicalPort
10621m 2
10622decl (Decl
10623n "W_D"
10624t "std_logic_vector"
10625b "(15 DOWNTO 0)"
10626o 57
10627suid 107,0
10628)
10629)
10630uid 3658,0
10631)
10632*340 (LeafLogPort
10633port (LogicalPort
10634m 1
10635decl (Decl
10636n "W_RES"
10637t "std_logic"
10638o 54
10639suid 108,0
10640i "'1'"
10641)
10642)
10643uid 3660,0
10644)
10645*341 (LeafLogPort
10646port (LogicalPort
10647m 1
10648decl (Decl
10649n "W_RD"
10650t "std_logic"
10651o 53
10652suid 109,0
10653i "'1'"
10654)
10655)
10656uid 3662,0
10657)
10658*342 (LeafLogPort
10659port (LogicalPort
10660m 1
10661decl (Decl
10662n "W_WR"
10663t "std_logic"
10664o 55
10665suid 110,0
10666i "'1'"
10667)
10668)
10669uid 3664,0
10670)
10671*343 (LeafLogPort
10672port (LogicalPort
10673decl (Decl
10674n "W_INT"
10675t "std_logic"
10676o 16
10677suid 111,0
10678)
10679)
10680uid 3666,0
10681)
10682*344 (LeafLogPort
10683port (LogicalPort
10684m 1
10685decl (Decl
10686n "W_CS"
10687t "std_logic"
10688o 52
10689suid 112,0
10690i "'1'"
10691)
10692)
10693uid 3668,0
10694)
10695*345 (LeafLogPort
10696port (LogicalPort
10697m 1
10698decl (Decl
10699n "MOSI"
10700t "std_logic"
10701o 34
10702suid 113,0
10703i "'0'"
10704)
10705)
10706uid 3696,0
10707)
10708*346 (LeafLogPort
10709port (LogicalPort
10710m 2
10711decl (Decl
10712n "MISO"
10713t "std_logic"
10714preAdd 0
10715posAdd 0
10716o 56
10717suid 114,0
10718)
10719)
10720uid 3698,0
10721)
10722*347 (LeafLogPort
10723port (LogicalPort
10724m 1
10725decl (Decl
10726n "RS485_C_RE"
10727t "std_logic"
10728o 39
10729suid 127,0
10730)
10731)
10732uid 3888,0
10733)
10734*348 (LeafLogPort
10735port (LogicalPort
10736m 1
10737decl (Decl
10738n "RS485_C_DE"
10739t "std_logic"
10740o 37
10741suid 128,0
10742)
10743)
10744uid 3890,0
10745)
10746*349 (LeafLogPort
10747port (LogicalPort
10748m 1
10749decl (Decl
10750n "RS485_E_RE"
10751t "std_logic"
10752o 42
10753suid 129,0
10754)
10755)
10756uid 3892,0
10757)
10758*350 (LeafLogPort
10759port (LogicalPort
10760m 1
10761decl (Decl
10762n "RS485_E_DE"
10763t "std_logic"
10764o 40
10765suid 130,0
10766)
10767)
10768uid 3894,0
10769)
10770*351 (LeafLogPort
10771port (LogicalPort
10772m 1
10773decl (Decl
10774n "DENABLE"
10775t "std_logic"
10776o 27
10777suid 131,0
10778i "'0'"
10779)
10780)
10781uid 3896,0
10782)
10783*352 (LeafLogPort
10784port (LogicalPort
10785m 1
10786decl (Decl
10787n "EE_CS"
10788t "std_logic"
10789o 32
10790suid 133,0
10791)
10792)
10793uid 3900,0
10794)
10795*353 (LeafLogPort
10796port (LogicalPort
10797m 1
10798decl (Decl
10799n "D_T"
10800t "std_logic_vector"
10801b "(7 DOWNTO 0)"
10802o 30
10803suid 141,0
10804i "(OTHERS => '0')"
10805)
10806)
10807uid 5322,0
10808)
10809*354 (LeafLogPort
10810port (LogicalPort
10811m 1
10812decl (Decl
10813n "D_T2"
10814t "std_logic_vector"
10815b "(1 DOWNTO 0)"
10816o 31
10817suid 154,0
10818i "(others => '0')"
10819)
10820)
10821uid 6872,0
10822scheme 0
10823)
10824*355 (LeafLogPort
10825port (LogicalPort
10826m 1
10827decl (Decl
10828n "A1_T"
10829t "std_logic_vector"
10830b "(7 DOWNTO 0)"
10831o 19
10832suid 155,0
10833i "(OTHERS => '0')"
10834)
10835)
10836uid 7134,0
10837scheme 0
10838)
10839*356 (LeafLogPort
10840port (LogicalPort
10841m 4
10842decl (Decl
10843n "CLK_50"
10844t "std_logic"
10845o 63
10846suid 163,0
10847)
10848)
10849uid 9516,0
10850)
10851*357 (LeafLogPort
10852port (LogicalPort
10853m 1
10854decl (Decl
10855n "A0_T"
10856t "std_logic_vector"
10857b "(7 DOWNTO 0)"
10858o 18
10859suid 166,0
10860i "(others => '0')"
10861)
10862)
10863uid 10294,0
10864scheme 0
10865)
10866*358 (LeafLogPort
10867port (LogicalPort
10868decl (Decl
10869n "RS485_C_DI"
10870t "std_logic"
10871o 13
10872suid 197,0
10873)
10874)
10875uid 11084,0
10876scheme 0
10877)
10878*359 (LeafLogPort
10879port (LogicalPort
10880m 1
10881decl (Decl
10882n "RS485_C_DO"
10883t "std_logic"
10884o 38
10885suid 198,0
10886)
10887)
10888uid 11086,0
10889scheme 0
10890)
10891*360 (LeafLogPort
10892port (LogicalPort
10893decl (Decl
10894n "RS485_E_DI"
10895t "std_logic"
10896o 14
10897suid 200,0
10898)
10899)
10900uid 11504,0
10901scheme 0
10902)
10903*361 (LeafLogPort
10904port (LogicalPort
10905m 1
10906decl (Decl
10907n "RS485_E_DO"
10908t "std_logic"
10909o 41
10910suid 201,0
10911)
10912)
10913uid 11506,0
10914scheme 0
10915)
10916*362 (LeafLogPort
10917port (LogicalPort
10918m 1
10919decl (Decl
10920n "SRIN"
10921t "std_logic"
10922o 44
10923suid 203,0
10924i "'0'"
10925)
10926)
10927uid 12336,0
10928)
10929*363 (LeafLogPort
10930port (LogicalPort
10931m 1
10932decl (Decl
10933n "AMBER_LED"
10934t "std_logic"
10935o 20
10936suid 207,0
10937)
10938)
10939uid 12768,0
10940)
10941*364 (LeafLogPort
10942port (LogicalPort
10943m 1
10944decl (Decl
10945n "GREEN_LED"
10946t "std_logic"
10947o 33
10948suid 208,0
10949)
10950)
10951uid 12770,0
10952)
10953*365 (LeafLogPort
10954port (LogicalPort
10955m 1
10956decl (Decl
10957n "RED_LED"
10958t "std_logic"
10959o 36
10960suid 209,0
10961)
10962)
10963uid 12772,0
10964)
10965*366 (LeafLogPort
10966port (LogicalPort
10967decl (Decl
10968n "LINE"
10969t "std_logic_vector"
10970b "( 5 DOWNTO 0 )"
10971o 11
10972suid 210,0
10973)
10974)
10975uid 13514,0
10976scheme 0
10977)
10978*367 (LeafLogPort
10979port (LogicalPort
10980decl (Decl
10981n "REFCLK"
10982t "std_logic"
10983o 12
10984suid 211,0
10985)
10986)
10987uid 13626,0
10988scheme 0
10989)
10990*368 (LeafLogPort
10991port (LogicalPort
10992decl (Decl
10993n "D_T_in"
10994t "std_logic_vector"
10995b "(1 DOWNTO 0)"
10996o 10
10997suid 213,0
10998)
10999)
11000uid 14320,0
11001scheme 0
11002)
11003*369 (LeafLogPort
11004port (LogicalPort
11005m 4
11006decl (Decl
11007n "led"
11008t "std_logic_vector"
11009b "(7 DOWNTO 0)"
11010posAdd 0
11011o 77
11012suid 215,0
11013i "(OTHERS => '0')"
11014)
11015)
11016uid 15181,0
11017)
11018*370 (LeafLogPort
11019port (LogicalPort
11020decl (Decl
11021n "D_PLLLCK"
11022t "std_logic_vector"
11023b "(3 DOWNTO 0)"
11024o 81
11025suid 216,0
11026)
11027)
11028uid 15704,0
11029scheme 0
11030)
11031*371 (LeafLogPort
11032port (LogicalPort
11033m 1
11034decl (Decl
11035n "TCS"
11036t "std_logic_vector"
11037b "(3 DOWNTO 0)"
11038o 70
11039suid 217,0
11040)
11041)
11042uid 15843,0
11043scheme 0
11044)
11045*372 (LeafLogPort
11046port (LogicalPort
11047m 1
11048decl (Decl
11049n "DSRCLK"
11050t "std_logic_vector"
11051b "(3 DOWNTO 0)"
11052o 60
11053suid 222,0
11054i "(others => '0')"
11055)
11056)
11057uid 16055,0
11058scheme 0
11059)
11060*373 (LeafLogPort
11061port (LogicalPort
11062m 4
11063decl (Decl
11064n "SRCLK"
11065t "std_logic"
11066o 61
11067suid 225,0
11068i "'0'"
11069)
11070)
11071uid 16253,0
11072)
11073*374 (LeafLogPort
11074port (LogicalPort
11075m 4
11076decl (Decl
11077n "alarm_refclk_too_high"
11078t "std_logic"
11079o 62
11080suid 226,0
11081i "'0'"
11082)
11083)
11084uid 16582,0
11085)
11086*375 (LeafLogPort
11087port (LogicalPort
11088m 4
11089decl (Decl
11090n "alarm_refclk_too_low"
11091t "std_logic"
11092o 63
11093suid 227,0
11094i "'0'"
11095)
11096)
11097uid 16584,0
11098)
11099*376 (LeafLogPort
11100port (LogicalPort
11101m 4
11102decl (Decl
11103n "counter_result"
11104t "std_logic_vector"
11105b "(11 downto 0)"
11106o 64
11107suid 230,0
11108i "(others => '0')"
11109)
11110)
11111uid 16586,0
11112)
11113*377 (LeafLogPort
11114port (LogicalPort
11115lang 2
11116m 4
11117decl (Decl
11118n "ADC_CLK"
11119t "std_logic"
11120o 61
11121suid 231,0
11122)
11123)
11124uid 17310,0
11125)
11126*378 (LeafLogPort
11127port (LogicalPort
11128lang 2
11129m 1
11130decl (Decl
11131n "TRG_V"
11132t "std_logic"
11133o 62
11134suid 232,0
11135i "'0'"
11136)
11137)
11138uid 17399,0
11139scheme 0
11140)
11141*379 (LeafLogPort
11142port (LogicalPort
11143m 4
11144decl (Decl
11145n "w5300_state"
11146t "std_logic_vector"
11147b "(7 DOWNTO 0)"
11148eolc "-- state is encoded here ... useful for debugging."
11149posAdd 0
11150o 63
11151suid 233,0
11152)
11153)
11154uid 17854,0
11155)
11156*380 (LeafLogPort
11157port (LogicalPort
11158m 4
11159decl (Decl
11160n "debug_data_ram_empty"
11161t "std_logic"
11162o 64
11163suid 234,0
11164)
11165)
11166uid 18082,0
11167)
11168*381 (LeafLogPort
11169port (LogicalPort
11170m 4
11171decl (Decl
11172n "debug_data_valid"
11173t "std_logic"
11174o 65
11175suid 235,0
11176)
11177)
11178uid 18084,0
11179)
11180]
11181)
11182pdm (PhysicalDM
11183displayShortBounds 1
11184editShortBounds 1
11185uid 67,0
11186optionalChildren [
11187*382 (Sheet
11188sheetRow (SheetRow
11189headerVa (MVa
11190cellColor "49152,49152,49152"
11191fontColor "0,0,0"
11192font "Tahoma,10,0"
11193)
11194cellVa (MVa
11195cellColor "65535,65535,65535"
11196fontColor "0,0,0"
11197font "Tahoma,10,0"
11198)
11199groupVa (MVa
11200cellColor "39936,56832,65280"
11201fontColor "0,0,0"
11202font "Tahoma,10,0"
11203)
11204emptyMRCItem *383 (MRCItem
11205litem &304
11206pos 65
11207dimension 20
11208)
11209uid 69,0
11210optionalChildren [
11211*384 (MRCItem
11212litem &305
11213pos 0
11214dimension 20
11215uid 70,0
11216)
11217*385 (MRCItem
11218litem &306
11219pos 1
11220dimension 23
11221uid 71,0
11222)
11223*386 (MRCItem
11224litem &307
11225pos 2
11226hidden 1
11227dimension 20
11228uid 72,0
11229)
11230*387 (MRCItem
11231litem &317
11232pos 42
11233dimension 20
11234uid 328,0
11235)
11236*388 (MRCItem
11237litem &318
11238pos 43
11239dimension 20
11240uid 330,0
11241)
11242*389 (MRCItem
11243litem &319
11244pos 44
11245dimension 20
11246uid 1492,0
11247)
11248*390 (MRCItem
11249litem &320
11250pos 0
11251dimension 20
11252uid 2436,0
11253)
11254*391 (MRCItem
11255litem &321
11256pos 1
11257dimension 20
11258uid 3040,0
11259)
11260*392 (MRCItem
11261litem &322
11262pos 2
11263dimension 20
11264uid 3277,0
11265)
11266*393 (MRCItem
11267litem &323
11268pos 3
11269dimension 20
11270uid 3279,0
11271)
11272*394 (MRCItem
11273litem &324
11274pos 4
11275dimension 20
11276uid 3281,0
11277)
11278*395 (MRCItem
11279litem &325
11280pos 5
11281dimension 20
11282uid 3383,0
11283)
11284*396 (MRCItem
11285litem &326
11286pos 6
11287dimension 20
11288uid 3385,0
11289)
11290*397 (MRCItem
11291litem &327
11292pos 7
11293dimension 20
11294uid 3387,0
11295)
11296*398 (MRCItem
11297litem &328
11298pos 8
11299dimension 20
11300uid 3389,0
11301)
11302*399 (MRCItem
11303litem &329
11304pos 9
11305dimension 20
11306uid 3391,0
11307)
11308*400 (MRCItem
11309litem &330
11310pos 10
11311dimension 20
11312uid 3393,0
11313)
11314*401 (MRCItem
11315litem &331
11316pos 11
11317dimension 20
11318uid 3525,0
11319)
11320*402 (MRCItem
11321litem &332
11322pos 12
11323dimension 20
11324uid 3527,0
11325)
11326*403 (MRCItem
11327litem &333
11328pos 13
11329dimension 20
11330uid 3529,0
11331)
11332*404 (MRCItem
11333litem &334
11334pos 14
11335dimension 20
11336uid 3531,0
11337)
11338*405 (MRCItem
11339litem &335
11340pos 15
11341dimension 20
11342uid 3533,0
11343)
11344*406 (MRCItem
11345litem &336
11346pos 16
11347dimension 20
11348uid 3535,0
11349)
11350*407 (MRCItem
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11354uid 3655,0
11355)
11356*408 (MRCItem
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11359dimension 20
11360uid 3657,0
11361)
11362*409 (MRCItem
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11364pos 19
11365dimension 20
11366uid 3659,0
11367)
11368*410 (MRCItem
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11371dimension 20
11372uid 3661,0
11373)
11374*411 (MRCItem
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11377dimension 20
11378uid 3663,0
11379)
11380*412 (MRCItem
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11382pos 22
11383dimension 20
11384uid 3665,0
11385)
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11390uid 3667,0
11391)
11392*414 (MRCItem
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11395dimension 20
11396uid 3669,0
11397)
11398*415 (MRCItem
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11400pos 25
11401dimension 20
11402uid 3697,0
11403)
11404*416 (MRCItem
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11407dimension 20
11408uid 3699,0
11409)
11410*417 (MRCItem
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11412pos 27
11413dimension 20
11414uid 3889,0
11415)
11416*418 (MRCItem
11417litem &348
11418pos 28
11419dimension 20
11420uid 3891,0
11421)
11422*419 (MRCItem
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11424pos 29
11425dimension 20
11426uid 3893,0
11427)
11428*420 (MRCItem
11429litem &350
11430pos 30
11431dimension 20
11432uid 3895,0
11433)
11434*421 (MRCItem
11435litem &351
11436pos 31
11437dimension 20
11438uid 3897,0
11439)
11440*422 (MRCItem
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11442pos 32
11443dimension 20
11444uid 3901,0
11445)
11446*423 (MRCItem
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11448pos 33
11449dimension 20
11450uid 5323,0
11451)
11452*424 (MRCItem
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11454pos 34
11455dimension 20
11456uid 6873,0
11457)
11458*425 (MRCItem
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11460pos 35
11461dimension 20
11462uid 7135,0
11463)
11464*426 (MRCItem
11465litem &356
11466pos 45
11467dimension 20
11468uid 9517,0
11469)
11470*427 (MRCItem
11471litem &357
11472pos 36
11473dimension 20
11474uid 10295,0
11475)
11476*428 (MRCItem
11477litem &358
11478pos 37
11479dimension 20
11480uid 11085,0
11481)
11482*429 (MRCItem
11483litem &359
11484pos 38
11485dimension 20
11486uid 11087,0
11487)
11488*430 (MRCItem
11489litem &360
11490pos 39
11491dimension 20
11492uid 11505,0
11493)
11494*431 (MRCItem
11495litem &361
11496pos 40
11497dimension 20
11498uid 11507,0
11499)
11500*432 (MRCItem
11501litem &362
11502pos 41
11503dimension 20
11504uid 12337,0
11505)
11506*433 (MRCItem
11507litem &363
11508pos 46
11509dimension 20
11510uid 12769,0
11511)
11512*434 (MRCItem
11513litem &364
11514pos 47
11515dimension 20
11516uid 12771,0
11517)
11518*435 (MRCItem
11519litem &365
11520pos 48
11521dimension 20
11522uid 12773,0
11523)
11524*436 (MRCItem
11525litem &366
11526pos 49
11527dimension 20
11528uid 13515,0
11529)
11530*437 (MRCItem
11531litem &367
11532pos 50
11533dimension 20
11534uid 13627,0
11535)
11536*438 (MRCItem
11537litem &368
11538pos 51
11539dimension 20
11540uid 14321,0
11541)
11542*439 (MRCItem
11543litem &369
11544pos 52
11545dimension 20
11546uid 15182,0
11547)
11548*440 (MRCItem
11549litem &370
11550pos 53
11551dimension 20
11552uid 15705,0
11553)
11554*441 (MRCItem
11555litem &371
11556pos 54
11557dimension 20
11558uid 15844,0
11559)
11560*442 (MRCItem
11561litem &372
11562pos 55
11563dimension 20
11564uid 16056,0
11565)
11566*443 (MRCItem
11567litem &373
11568pos 56
11569dimension 20
11570uid 16254,0
11571)
11572*444 (MRCItem
11573litem &374
11574pos 57
11575dimension 20
11576uid 16583,0
11577)
11578*445 (MRCItem
11579litem &375
11580pos 58
11581dimension 20
11582uid 16585,0
11583)
11584*446 (MRCItem
11585litem &376
11586pos 59
11587dimension 20
11588uid 16587,0
11589)
11590*447 (MRCItem
11591litem &377
11592pos 60
11593dimension 20
11594uid 17311,0
11595)
11596*448 (MRCItem
11597litem &378
11598pos 61
11599dimension 20
11600uid 17400,0
11601)
11602*449 (MRCItem
11603litem &379
11604pos 62
11605dimension 20
11606uid 17855,0
11607)
11608*450 (MRCItem
11609litem &380
11610pos 63
11611dimension 20
11612uid 18083,0
11613)
11614*451 (MRCItem
11615litem &381
11616pos 64
11617dimension 20
11618uid 18085,0
11619)
11620]
11621)
11622sheetCol (SheetCol
11623propVa (MVa
11624cellColor "0,49152,49152"
11625fontColor "0,0,0"
11626font "Tahoma,10,0"
11627textAngle 90
11628)
11629uid 73,0
11630optionalChildren [
11631*452 (MRCItem
11632litem &308
11633pos 0
11634dimension 20
11635uid 74,0
11636)
11637*453 (MRCItem
11638litem &310
11639pos 1
11640dimension 50
11641uid 75,0
11642)
11643*454 (MRCItem
11644litem &311
11645pos 2
11646dimension 100
11647uid 76,0
11648)
11649*455 (MRCItem
11650litem &312
11651pos 3
11652dimension 50
11653uid 77,0
11654)
11655*456 (MRCItem
11656litem &313
11657pos 4
11658dimension 100
11659uid 78,0
11660)
11661*457 (MRCItem
11662litem &314
11663pos 5
11664dimension 100
11665uid 79,0
11666)
11667*458 (MRCItem
11668litem &315
11669pos 6
11670dimension 182
11671uid 80,0
11672)
11673*459 (MRCItem
11674litem &316
11675pos 7
11676dimension 80
11677uid 81,0
11678)
11679]
11680)
11681fixedCol 4
11682fixedRow 2
11683name "Ports"
11684uid 68,0
11685vaOverrides [
11686]
11687)
11688]
11689)
11690uid 53,0
11691)
11692genericsCommonDM (CommonDM
11693ldm (LogicalDM
11694emptyRow *460 (LEmptyRow
11695)
11696uid 83,0
11697optionalChildren [
11698*461 (RefLabelRowHdr
11699)
11700*462 (TitleRowHdr
11701)
11702*463 (FilterRowHdr
11703)
11704*464 (RefLabelColHdr
11705tm "RefLabelColHdrMgr"
11706)
11707*465 (RowExpandColHdr
11708tm "RowExpandColHdrMgr"
11709)
11710*466 (GroupColHdr
11711tm "GroupColHdrMgr"
11712)
11713*467 (NameColHdr
11714tm "GenericNameColHdrMgr"
11715)
11716*468 (TypeColHdr
11717tm "GenericTypeColHdrMgr"
11718)
11719*469 (InitColHdr
11720tm "GenericValueColHdrMgr"
11721)
11722*470 (PragmaColHdr
11723tm "GenericPragmaColHdrMgr"
11724)
11725*471 (EolColHdr
11726tm "GenericEolColHdrMgr"
11727)
11728]
11729)
11730pdm (PhysicalDM
11731displayShortBounds 1
11732editShortBounds 1
11733uid 95,0
11734optionalChildren [
11735*472 (Sheet
11736sheetRow (SheetRow
11737headerVa (MVa
11738cellColor "49152,49152,49152"
11739fontColor "0,0,0"
11740font "Tahoma,10,0"
11741)
11742cellVa (MVa
11743cellColor "65535,65535,65535"
11744fontColor "0,0,0"
11745font "Tahoma,10,0"
11746)
11747groupVa (MVa
11748cellColor "39936,56832,65280"
11749fontColor "0,0,0"
11750font "Tahoma,10,0"
11751)
11752emptyMRCItem *473 (MRCItem
11753litem &460
11754pos 0
11755dimension 20
11756)
11757uid 97,0
11758optionalChildren [
11759*474 (MRCItem
11760litem &461
11761pos 0
11762dimension 20
11763uid 98,0
11764)
11765*475 (MRCItem
11766litem &462
11767pos 1
11768dimension 23
11769uid 99,0
11770)
11771*476 (MRCItem
11772litem &463
11773pos 2
11774hidden 1
11775dimension 20
11776uid 100,0
11777)
11778]
11779)
11780sheetCol (SheetCol
11781propVa (MVa
11782cellColor "0,49152,49152"
11783fontColor "0,0,0"
11784font "Tahoma,10,0"
11785textAngle 90
11786)
11787uid 101,0
11788optionalChildren [
11789*477 (MRCItem
11790litem &464
11791pos 0
11792dimension 20
11793uid 102,0
11794)
11795*478 (MRCItem
11796litem &466
11797pos 1
11798dimension 50
11799uid 103,0
11800)
11801*479 (MRCItem
11802litem &467
11803pos 2
11804dimension 100
11805uid 104,0
11806)
11807*480 (MRCItem
11808litem &468
11809pos 3
11810dimension 100
11811uid 105,0
11812)
11813*481 (MRCItem
11814litem &469
11815pos 4
11816dimension 50
11817uid 106,0
11818)
11819*482 (MRCItem
11820litem &470
11821pos 5
11822dimension 50
11823uid 107,0
11824)
11825*483 (MRCItem
11826litem &471
11827pos 6
11828dimension 80
11829uid 108,0
11830)
11831]
11832)
11833fixedCol 3
11834fixedRow 2
11835name "Ports"
11836uid 96,0
11837vaOverrides [
11838]
11839)
11840]
11841)
11842uid 82,0
11843type 1
11844)
11845activeModelName "BlockDiag"
11846)
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