source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd @ 10958

Last change on this file since 10958 was 10958, checked in by neise, 9 years ago
File size: 173.6 KB
Line 
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1010uid 491,0
1011va (VaSet
1012vasetType 1
1013fg "0,0,32768"
1014)
1015optionalChildren [
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1017uid 492,0
1018sl 0
1019xt "90500,68625,92000,69375"
1020)
1021(Line
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1024xt "90000,69000,90500,69000"
1025pts [
1026"90000,69000"
1027"90500,69000"
1028]
1029)
1030]
1031)
1032stc 0
1033sf 1
1034tg (WTG
1035uid 494,0
1036ps "PortIoTextPlaceStrategy"
1037stg "STSignalDisplayStrategy"
1038f (Text
1039uid 495,0
1040va (VaSet
1041)
1042xt "93000,68500,95400,69500"
1043st "W_D"
1044blo "93000,69300"
1045tm "WireNameMgr"
1046)
1047)
1048)
1049*24 (PortIoIn
1050uid 496,0
1051shape (CompositeShape
1052uid 497,0
1053va (VaSet
1054vasetType 1
1055fg "0,0,32768"
1056)
1057optionalChildren [
1058(Pentagon
1059uid 498,0
1060sl 0
1061ro 90
1062xt "90500,73625,92000,74375"
1063)
1064(Line
1065uid 499,0
1066sl 0
1067ro 90
1068xt "90000,74000,90500,74000"
1069pts [
1070"90500,74000"
1071"90000,74000"
1072]
1073)
1074]
1075)
1076stc 0
1077sf 1
1078tg (WTG
1079uid 500,0
1080ps "PortIoTextPlaceStrategy"
1081stg "STSignalDisplayStrategy"
1082f (Text
1083uid 501,0
1084va (VaSet
1085)
1086xt "93000,73500,96300,74500"
1087st "W_INT"
1088blo "93000,74300"
1089tm "WireNameMgr"
1090)
1091)
1092)
1093*25 (PortIoOut
1094uid 502,0
1095shape (CompositeShape
1096uid 503,0
1097va (VaSet
1098vasetType 1
1099fg "0,0,32768"
1100)
1101optionalChildren [
1102(Pentagon
1103uid 504,0
1104sl 0
1105ro 270
1106xt "90500,71625,92000,72375"
1107)
1108(Line
1109uid 505,0
1110sl 0
1111ro 270
1112xt "90000,72000,90500,72000"
1113pts [
1114"90000,72000"
1115"90500,72000"
1116]
1117)
1118]
1119)
1120stc 0
1121sf 1
1122tg (WTG
1123uid 506,0
1124ps "PortIoTextPlaceStrategy"
1125stg "STSignalDisplayStrategy"
1126f (Text
1127uid 507,0
1128va (VaSet
1129)
1130xt "93000,71500,95900,72500"
1131st "W_RD"
1132blo "93000,72300"
1133tm "WireNameMgr"
1134)
1135)
1136)
1137*26 (PortIoOut
1138uid 508,0
1139shape (CompositeShape
1140uid 509,0
1141va (VaSet
1142vasetType 1
1143fg "0,0,32768"
1144)
1145optionalChildren [
1146(Pentagon
1147uid 510,0
1148sl 0
1149ro 270
1150xt "90500,72625,92000,73375"
1151)
1152(Line
1153uid 511,0
1154sl 0
1155ro 270
1156xt "90000,73000,90500,73000"
1157pts [
1158"90000,73000"
1159"90500,73000"
1160]
1161)
1162]
1163)
1164stc 0
1165sf 1
1166tg (WTG
1167uid 512,0
1168ps "PortIoTextPlaceStrategy"
1169stg "STSignalDisplayStrategy"
1170f (Text
1171uid 513,0
1172va (VaSet
1173)
1174xt "93000,72500,96200,73500"
1175st "W_WR"
1176blo "93000,73300"
1177tm "WireNameMgr"
1178)
1179)
1180)
1181*27 (Net
1182uid 1465,0
1183decl (Decl
1184n "adc_data_array"
1185t "adc_data_array_type"
1186o 57
1187suid 29,0
1188)
1189declText (MLText
1190uid 1466,0
1191va (VaSet
1192font "Courier New,8,0"
1193)
1194xt "39000,50400,66000,51200"
1195st "SIGNAL adc_data_array        : adc_data_array_type"
1196)
1197)
1198*28 (Net
1199uid 2407,0
1200decl (Decl
1201n "RSRLOAD"
1202t "std_logic"
1203o 40
1204suid 57,0
1205i "'0'"
1206)
1207declText (MLText
1208uid 2408,0
1209va (VaSet
1210font "Courier New,8,0"
1211)
1212xt "39000,35000,71500,35800"
1213st "RSRLOAD               : std_logic                      := '0'"
1214)
1215)
1216*29 (PortIoOut
1217uid 2415,0
1218shape (CompositeShape
1219uid 2416,0
1220va (VaSet
1221vasetType 1
1222fg "0,0,32768"
1223)
1224optionalChildren [
1225(Pentagon
1226uid 2417,0
1227sl 0
1228ro 90
1229xt "19000,110625,20500,111375"
1230)
1231(Line
1232uid 2418,0
1233sl 0
1234ro 90
1235xt "20500,111000,21000,111000"
1236pts [
1237"21000,111000"
1238"20500,111000"
1239]
1240)
1241]
1242)
1243stc 0
1244sf 1
1245tg (WTG
1246uid 2419,0
1247ps "PortIoTextPlaceStrategy"
1248stg "STSignalDisplayStrategy"
1249f (Text
1250uid 2420,0
1251va (VaSet
1252)
1253xt "13800,110500,18000,111500"
1254st "RSRLOAD"
1255ju 2
1256blo "18000,111300"
1257tm "WireNameMgr"
1258)
1259)
1260)
1261*30 (Net
1262uid 3025,0
1263decl (Decl
1264n "DAC_CS"
1265t "std_logic"
1266o 22
1267suid 66,0
1268)
1269declText (MLText
1270uid 3026,0
1271va (VaSet
1272font "Courier New,8,0"
1273)
1274xt "39000,20600,57000,21400"
1275st "DAC_CS                : std_logic"
1276)
1277)
1278*31 (PortIoOut
1279uid 3153,0
1280shape (CompositeShape
1281uid 3154,0
1282va (VaSet
1283vasetType 1
1284fg "0,0,32768"
1285)
1286optionalChildren [
1287(Pentagon
1288uid 3155,0
1289sl 0
1290ro 90
1291xt "-3000,70625,-1500,71375"
1292)
1293(Line
1294uid 3156,0
1295sl 0
1296ro 90
1297xt "-1500,71000,-1000,71000"
1298pts [
1299"-1000,71000"
1300"-1500,71000"
1301]
1302)
1303]
1304)
1305stc 0
1306sf 1
1307tg (WTG
1308uid 3157,0
1309ps "PortIoTextPlaceStrategy"
1310stg "STSignalDisplayStrategy"
1311f (Text
1312uid 3158,0
1313va (VaSet
1314)
1315xt "-6900,70500,-4000,71500"
1316st "A_CLK"
1317ju 2
1318blo "-4000,71300"
1319tm "WireNameMgr"
1320)
1321)
1322)
1323*32 (Net
1324uid 3216,0
1325decl (Decl
1326n "X_50M"
1327t "STD_LOGIC"
1328preAdd 0
1329posAdd 0
1330o 17
1331suid 67,0
1332)
1333declText (MLText
1334uid 3217,0
1335va (VaSet
1336font "Courier New,8,0"
1337)
1338xt "39000,16600,57000,17400"
1339st "X_50M                 : STD_LOGIC"
1340)
1341)
1342*33 (Net
1343uid 3226,0
1344decl (Decl
1345n "TRG"
1346t "STD_LOGIC"
1347o 15
1348suid 68,0
1349)
1350declText (MLText
1351uid 3227,0
1352va (VaSet
1353font "Courier New,8,0"
1354)
1355xt "39000,15000,57000,15800"
1356st "TRG                   : STD_LOGIC"
1357)
1358)
1359*34 (HdlText
1360uid 3248,0
1361optionalChildren [
1362*35 (EmbeddedText
1363uid 3254,0
1364commentText (CommentText
1365uid 3255,0
1366ps "CenterOffsetStrategy"
1367shape (Rectangle
1368uid 3256,0
1369va (VaSet
1370vasetType 1
1371fg "65535,65535,65535"
1372lineColor "0,0,32768"
1373lineWidth 2
1374)
1375xt "-14000,63000,12000,69000"
1376)
1377oxt "0,0,18000,5000"
1378text (MLText
1379uid 3257,0
1380va (VaSet
1381)
1382xt "-13800,63200,-9000,69200"
1383st "
1384A_CLK <= (
1385ADC_CLK,
1386ADC_CLK,
1387ADC_CLK,
1388ADC_CLK
1389);
1390
1391"
1392tm "HdlTextMgr"
1393wrapOption 3
1394visibleHeight 6000
1395visibleWidth 26000
1396)
1397)
1398)
1399]
1400shape (Rectangle
1401uid 3249,0
1402va (VaSet
1403vasetType 1
1404fg "65535,65535,37120"
1405lineColor "0,0,32768"
1406lineWidth 2
1407)
1408xt "5000,70000,13000,73000"
1409)
1410oxt "0,0,8000,10000"
1411ttg (MlTextGroup
1412uid 3250,0
1413ps "CenterOffsetStrategy"
1414stg "VerticalLayoutStrategy"
1415textVec [
1416*36 (Text
1417uid 3251,0
1418va (VaSet
1419font "Arial,8,1"
1420)
1421xt "6150,70000,10350,71000"
1422st "ADC_CLK"
1423blo "6150,70800"
1424tm "HdlTextNameMgr"
1425)
1426*37 (Text
1427uid 3252,0
1428va (VaSet
1429font "Arial,8,1"
1430)
1431xt "6150,71000,6950,72000"
1432st "2"
1433blo "6150,71800"
1434tm "HdlTextNumberMgr"
1435)
1436]
1437)
1438viewicon (ZoomableIcon
1439uid 3253,0
1440sl 0
1441va (VaSet
1442vasetType 1
1443fg "49152,49152,49152"
1444)
1445xt "5250,71250,6750,72750"
1446iconName "TextFile.png"
1447iconMaskName "TextFile.msk"
1448ftype 21
1449)
1450viewiconposition 0
1451)
1452*38 (Net
1453uid 3266,0
1454decl (Decl
1455n "A_CLK"
1456t "std_logic_vector"
1457b "(3 downto 0)"
1458o 21
1459suid 71,0
1460)
1461declText (MLText
1462uid 3267,0
1463va (VaSet
1464font "Courier New,8,0"
1465)
1466xt "39000,19800,67000,20600"
1467st "A_CLK                 : std_logic_vector(3 downto 0)"
1468)
1469)
1470*39 (PortIoOut
1471uid 3284,0
1472shape (CompositeShape
1473uid 3285,0
1474va (VaSet
1475vasetType 1
1476fg "0,0,32768"
1477)
1478optionalChildren [
1479(Pentagon
1480uid 3286,0
1481sl 0
1482ro 90
1483xt "19000,89625,20500,90375"
1484)
1485(Line
1486uid 3287,0
1487sl 0
1488ro 90
1489xt "20500,90000,21000,90000"
1490pts [
1491"21000,90000"
1492"20500,90000"
1493]
1494)
1495]
1496)
1497stc 0
1498sf 1
1499tg (WTG
1500uid 3288,0
1501ps "PortIoTextPlaceStrategy"
1502stg "STSignalDisplayStrategy"
1503f (Text
1504uid 3289,0
1505va (VaSet
1506)
1507xt "14300,89500,18000,90500"
1508st "OE_ADC"
1509ju 2
1510blo "18000,90300"
1511tm "WireNameMgr"
1512)
1513)
1514)
1515*40 (Net
1516uid 3290,0
1517decl (Decl
1518n "OE_ADC"
1519t "STD_LOGIC"
1520preAdd 0
1521posAdd 0
1522o 32
1523suid 73,0
1524)
1525declText (MLText
1526uid 3291,0
1527va (VaSet
1528font "Courier New,8,0"
1529)
1530xt "39000,28600,57000,29400"
1531st "OE_ADC                : STD_LOGIC"
1532)
1533)
1534*41 (PortIoIn
1535uid 3292,0
1536shape (CompositeShape
1537uid 3293,0
1538va (VaSet
1539vasetType 1
1540fg "0,0,32768"
1541)
1542optionalChildren [
1543(Pentagon
1544uid 3294,0
1545sl 0
1546ro 270
1547xt "19000,88625,20500,89375"
1548)
1549(Line
1550uid 3295,0
1551sl 0
1552ro 270
1553xt "20500,89000,21000,89000"
1554pts [
1555"20500,89000"
1556"21000,89000"
1557]
1558)
1559]
1560)
1561stc 0
1562sf 1
1563tg (WTG
1564uid 3296,0
1565ps "PortIoTextPlaceStrategy"
1566stg "STSignalDisplayStrategy"
1567f (Text
1568uid 3297,0
1569va (VaSet
1570)
1571xt "14900,88500,18000,89500"
1572st "A_OTR"
1573ju 2
1574blo "18000,89300"
1575tm "WireNameMgr"
1576)
1577)
1578)
1579*42 (Net
1580uid 3298,0
1581decl (Decl
1582n "A_OTR"
1583t "std_logic_vector"
1584b "(3 DOWNTO 0)"
1585o 5
1586suid 74,0
1587)
1588declText (MLText
1589uid 3299,0
1590va (VaSet
1591font "Courier New,8,0"
1592)
1593xt "39000,7000,67000,7800"
1594st "A_OTR                 : std_logic_vector(3 DOWNTO 0)"
1595)
1596)
1597*43 (HdlText
1598uid 3300,0
1599optionalChildren [
1600*44 (EmbeddedText
1601uid 3306,0
1602commentText (CommentText
1603uid 3307,0
1604ps "CenterOffsetStrategy"
1605shape (Rectangle
1606uid 3308,0
1607va (VaSet
1608vasetType 1
1609fg "65535,65535,65535"
1610lineColor "0,0,32768"
1611lineWidth 2
1612)
1613xt "19000,99000,38000,101000"
1614)
1615oxt "0,0,18000,5000"
1616text (MLText
1617uid 3309,0
1618va (VaSet
1619)
1620xt "19200,99200,35900,101200"
1621st "
1622adc_data_array <= ( A0_D, A1_D, A2_D, A3_D );
1623
1624"
1625tm "HdlTextMgr"
1626wrapOption 3
1627visibleHeight 2000
1628visibleWidth 19000
1629)
1630)
1631)
1632]
1633shape (Rectangle
1634uid 3301,0
1635va (VaSet
1636vasetType 1
1637fg "65535,65535,37120"
1638lineColor "0,0,32768"
1639lineWidth 2
1640)
1641xt "24000,94000,30000,99000"
1642)
1643oxt "0,0,8000,10000"
1644ttg (MlTextGroup
1645uid 3302,0
1646ps "CenterOffsetStrategy"
1647stg "VerticalLayoutStrategy"
1648textVec [
1649*45 (Text
1650uid 3303,0
1651va (VaSet
1652font "Arial,8,1"
1653)
1654xt "27150,95000,31750,96000"
1655st "ADC_DATA"
1656blo "27150,95800"
1657tm "HdlTextNameMgr"
1658)
1659*46 (Text
1660uid 3304,0
1661va (VaSet
1662font "Arial,8,1"
1663)
1664xt "27150,96000,27950,97000"
1665st "3"
1666blo "27150,96800"
1667tm "HdlTextNumberMgr"
1668)
1669]
1670)
1671viewicon (ZoomableIcon
1672uid 3305,0
1673sl 0
1674va (VaSet
1675vasetType 1
1676fg "49152,49152,49152"
1677)
1678xt "24250,97250,25750,98750"
1679iconName "TextFile.png"
1680iconMaskName "TextFile.msk"
1681ftype 21
1682)
1683viewiconposition 0
1684)
1685*47 (PortIoIn
1686uid 3310,0
1687shape (CompositeShape
1688uid 3311,0
1689va (VaSet
1690vasetType 1
1691fg "0,0,32768"
1692)
1693optionalChildren [
1694(Pentagon
1695uid 3312,0
1696sl 0
1697ro 270
1698xt "19000,94625,20500,95375"
1699)
1700(Line
1701uid 3313,0
1702sl 0
1703ro 270
1704xt "20500,95000,21000,95000"
1705pts [
1706"20500,95000"
1707"21000,95000"
1708]
1709)
1710]
1711)
1712stc 0
1713sf 1
1714tg (WTG
1715uid 3314,0
1716ps "PortIoTextPlaceStrategy"
1717stg "STSignalDisplayStrategy"
1718f (Text
1719uid 3315,0
1720va (VaSet
1721)
1722xt "15400,94500,18000,95500"
1723st "A0_D"
1724ju 2
1725blo "18000,95300"
1726tm "WireNameMgr"
1727)
1728)
1729)
1730*48 (PortIoIn
1731uid 3332,0
1732shape (CompositeShape
1733uid 3333,0
1734va (VaSet
1735vasetType 1
1736fg "0,0,32768"
1737)
1738optionalChildren [
1739(Pentagon
1740uid 3334,0
1741sl 0
1742ro 270
1743xt "19000,95625,20500,96375"
1744)
1745(Line
1746uid 3335,0
1747sl 0
1748ro 270
1749xt "20500,96000,21000,96000"
1750pts [
1751"20500,96000"
1752"21000,96000"
1753]
1754)
1755]
1756)
1757stc 0
1758sf 1
1759tg (WTG
1760uid 3336,0
1761ps "PortIoTextPlaceStrategy"
1762stg "STSignalDisplayStrategy"
1763f (Text
1764uid 3337,0
1765va (VaSet
1766)
1767xt "15500,95500,18000,96500"
1768st "A1_D"
1769ju 2
1770blo "18000,96300"
1771tm "WireNameMgr"
1772)
1773)
1774)
1775*49 (PortIoIn
1776uid 3338,0
1777shape (CompositeShape
1778uid 3339,0
1779va (VaSet
1780vasetType 1
1781fg "0,0,32768"
1782)
1783optionalChildren [
1784(Pentagon
1785uid 3340,0
1786sl 0
1787ro 270
1788xt "19000,96625,20500,97375"
1789)
1790(Line
1791uid 3341,0
1792sl 0
1793ro 270
1794xt "20500,97000,21000,97000"
1795pts [
1796"20500,97000"
1797"21000,97000"
1798]
1799)
1800]
1801)
1802stc 0
1803sf 1
1804tg (WTG
1805uid 3342,0
1806ps "PortIoTextPlaceStrategy"
1807stg "STSignalDisplayStrategy"
1808f (Text
1809uid 3343,0
1810va (VaSet
1811)
1812xt "15400,96500,18000,97500"
1813st "A2_D"
1814ju 2
1815blo "18000,97300"
1816tm "WireNameMgr"
1817)
1818)
1819)
1820*50 (PortIoIn
1821uid 3344,0
1822shape (CompositeShape
1823uid 3345,0
1824va (VaSet
1825vasetType 1
1826fg "0,0,32768"
1827)
1828optionalChildren [
1829(Pentagon
1830uid 3346,0
1831sl 0
1832ro 270
1833xt "19000,97625,20500,98375"
1834)
1835(Line
1836uid 3347,0
1837sl 0
1838ro 270
1839xt "20500,98000,21000,98000"
1840pts [
1841"20500,98000"
1842"21000,98000"
1843]
1844)
1845]
1846)
1847stc 0
1848sf 1
1849tg (WTG
1850uid 3348,0
1851ps "PortIoTextPlaceStrategy"
1852stg "STSignalDisplayStrategy"
1853f (Text
1854uid 3349,0
1855va (VaSet
1856)
1857xt "15400,97500,18000,98500"
1858st "A3_D"
1859ju 2
1860blo "18000,98300"
1861tm "WireNameMgr"
1862)
1863)
1864)
1865*51 (Net
1866uid 3374,0
1867decl (Decl
1868n "A0_D"
1869t "std_logic_vector"
1870b "(11 DOWNTO 0)"
1871o 1
1872suid 79,0
1873)
1874declText (MLText
1875uid 3375,0
1876va (VaSet
1877font "Courier New,8,0"
1878)
1879xt "39000,3800,67500,4600"
1880st "A0_D                  : std_logic_vector(11 DOWNTO 0)"
1881)
1882)
1883*52 (Net
1884uid 3376,0
1885decl (Decl
1886n "A1_D"
1887t "std_logic_vector"
1888b "(11 DOWNTO 0)"
1889o 2
1890suid 80,0
1891)
1892declText (MLText
1893uid 3377,0
1894va (VaSet
1895font "Courier New,8,0"
1896)
1897xt "39000,4600,67500,5400"
1898st "A1_D                  : std_logic_vector(11 DOWNTO 0)"
1899)
1900)
1901*53 (Net
1902uid 3378,0
1903decl (Decl
1904n "A2_D"
1905t "std_logic_vector"
1906b "(11 DOWNTO 0)"
1907o 3
1908suid 81,0
1909)
1910declText (MLText
1911uid 3379,0
1912va (VaSet
1913font "Courier New,8,0"
1914)
1915xt "39000,5400,67500,6200"
1916st "A2_D                  : std_logic_vector(11 DOWNTO 0)"
1917)
1918)
1919*54 (Net
1920uid 3380,0
1921decl (Decl
1922n "A3_D"
1923t "std_logic_vector"
1924b "(11 DOWNTO 0)"
1925o 4
1926suid 82,0
1927)
1928declText (MLText
1929uid 3381,0
1930va (VaSet
1931font "Courier New,8,0"
1932)
1933xt "39000,6200,67500,7000"
1934st "A3_D                  : std_logic_vector(11 DOWNTO 0)"
1935)
1936)
1937*55 (PortIoIn
1938uid 3476,0
1939shape (CompositeShape
1940uid 3477,0
1941va (VaSet
1942vasetType 1
1943fg "0,0,32768"
1944)
1945optionalChildren [
1946(Pentagon
1947uid 3478,0
1948sl 0
1949ro 270
1950xt "19000,104625,20500,105375"
1951)
1952(Line
1953uid 3479,0
1954sl 0
1955ro 270
1956xt "20500,105000,21000,105000"
1957pts [
1958"20500,105000"
1959"21000,105000"
1960]
1961)
1962]
1963)
1964stc 0
1965sf 1
1966tg (WTG
1967uid 3480,0
1968ps "PortIoTextPlaceStrategy"
1969stg "STSignalDisplayStrategy"
1970f (Text
1971uid 3481,0
1972va (VaSet
1973)
1974xt "13200,104500,18000,105500"
1975st "D0_SROUT"
1976ju 2
1977blo "18000,105300"
1978tm "WireNameMgr"
1979)
1980)
1981)
1982*56 (PortIoIn
1983uid 3482,0
1984shape (CompositeShape
1985uid 3483,0
1986va (VaSet
1987vasetType 1
1988fg "0,0,32768"
1989)
1990optionalChildren [
1991(Pentagon
1992uid 3484,0
1993sl 0
1994ro 270
1995xt "19000,105625,20500,106375"
1996)
1997(Line
1998uid 3485,0
1999sl 0
2000ro 270
2001xt "20500,106000,21000,106000"
2002pts [
2003"20500,106000"
2004"21000,106000"
2005]
2006)
2007]
2008)
2009stc 0
2010sf 1
2011tg (WTG
2012uid 3486,0
2013ps "PortIoTextPlaceStrategy"
2014stg "STSignalDisplayStrategy"
2015f (Text
2016uid 3487,0
2017va (VaSet
2018)
2019xt "13300,105500,18000,106500"
2020st "D1_SROUT"
2021ju 2
2022blo "18000,106300"
2023tm "WireNameMgr"
2024)
2025)
2026)
2027*57 (PortIoIn
2028uid 3488,0
2029shape (CompositeShape
2030uid 3489,0
2031va (VaSet
2032vasetType 1
2033fg "0,0,32768"
2034)
2035optionalChildren [
2036(Pentagon
2037uid 3490,0
2038sl 0
2039ro 270
2040xt "19000,106625,20500,107375"
2041)
2042(Line
2043uid 3491,0
2044sl 0
2045ro 270
2046xt "20500,107000,21000,107000"
2047pts [
2048"20500,107000"
2049"21000,107000"
2050]
2051)
2052]
2053)
2054stc 0
2055sf 1
2056tg (WTG
2057uid 3492,0
2058ps "PortIoTextPlaceStrategy"
2059stg "STSignalDisplayStrategy"
2060f (Text
2061uid 3493,0
2062va (VaSet
2063)
2064xt "13200,106500,18000,107500"
2065st "D2_SROUT"
2066ju 2
2067blo "18000,107300"
2068tm "WireNameMgr"
2069)
2070)
2071)
2072*58 (PortIoIn
2073uid 3494,0
2074shape (CompositeShape
2075uid 3495,0
2076va (VaSet
2077vasetType 1
2078fg "0,0,32768"
2079)
2080optionalChildren [
2081(Pentagon
2082uid 3496,0
2083sl 0
2084ro 270
2085xt "19000,107625,20500,108375"
2086)
2087(Line
2088uid 3497,0
2089sl 0
2090ro 270
2091xt "20500,108000,21000,108000"
2092pts [
2093"20500,108000"
2094"21000,108000"
2095]
2096)
2097]
2098)
2099stc 0
2100sf 1
2101tg (WTG
2102uid 3498,0
2103ps "PortIoTextPlaceStrategy"
2104stg "STSignalDisplayStrategy"
2105f (Text
2106uid 3499,0
2107va (VaSet
2108)
2109xt "13200,107500,18000,108500"
2110st "D3_SROUT"
2111ju 2
2112blo "18000,108300"
2113tm "WireNameMgr"
2114)
2115)
2116)
2117*59 (Net
2118uid 3500,0
2119decl (Decl
2120n "D0_SROUT"
2121t "std_logic"
2122o 6
2123suid 91,0
2124)
2125declText (MLText
2126uid 3501,0
2127va (VaSet
2128font "Courier New,8,0"
2129)
2130xt "39000,7800,57000,8600"
2131st "D0_SROUT              : std_logic"
2132)
2133)
2134*60 (Net
2135uid 3502,0
2136decl (Decl
2137n "D1_SROUT"
2138t "std_logic"
2139o 7
2140suid 92,0
2141)
2142declText (MLText
2143uid 3503,0
2144va (VaSet
2145font "Courier New,8,0"
2146)
2147xt "39000,8600,57000,9400"
2148st "D1_SROUT              : std_logic"
2149)
2150)
2151*61 (Net
2152uid 3504,0
2153decl (Decl
2154n "D2_SROUT"
2155t "std_logic"
2156o 8
2157suid 93,0
2158)
2159declText (MLText
2160uid 3505,0
2161va (VaSet
2162font "Courier New,8,0"
2163)
2164xt "39000,9400,57000,10200"
2165st "D2_SROUT              : std_logic"
2166)
2167)
2168*62 (Net
2169uid 3506,0
2170decl (Decl
2171n "D3_SROUT"
2172t "std_logic"
2173o 9
2174suid 94,0
2175)
2176declText (MLText
2177uid 3507,0
2178va (VaSet
2179font "Courier New,8,0"
2180)
2181xt "39000,10200,57000,11000"
2182st "D3_SROUT              : std_logic"
2183)
2184)
2185*63 (PortIoOut
2186uid 3508,0
2187shape (CompositeShape
2188uid 3509,0
2189va (VaSet
2190vasetType 1
2191fg "0,0,32768"
2192)
2193optionalChildren [
2194(Pentagon
2195uid 3510,0
2196sl 0
2197ro 90
2198xt "19000,108625,20500,109375"
2199)
2200(Line
2201uid 3511,0
2202sl 0
2203ro 90
2204xt "20500,109000,21000,109000"
2205pts [
2206"21000,109000"
2207"20500,109000"
2208]
2209)
2210]
2211)
2212stc 0
2213sf 1
2214tg (WTG
2215uid 3512,0
2216ps "PortIoTextPlaceStrategy"
2217stg "STSignalDisplayStrategy"
2218f (Text
2219uid 3513,0
2220va (VaSet
2221)
2222xt "15900,108500,18000,109500"
2223st "D_A"
2224ju 2
2225blo "18000,109300"
2226tm "WireNameMgr"
2227)
2228)
2229)
2230*64 (Net
2231uid 3514,0
2232decl (Decl
2233n "D_A"
2234t "std_logic_vector"
2235b "(3 DOWNTO 0)"
2236o 26
2237suid 95,0
2238i "(others => '0')"
2239)
2240declText (MLText
2241uid 3515,0
2242va (VaSet
2243font "Courier New,8,0"
2244)
2245xt "39000,23800,77500,24600"
2246st "D_A                   : std_logic_vector(3 DOWNTO 0)   := (others => '0')"
2247)
2248)
2249*65 (PortIoOut
2250uid 3516,0
2251shape (CompositeShape
2252uid 3517,0
2253va (VaSet
2254vasetType 1
2255fg "0,0,32768"
2256)
2257optionalChildren [
2258(Pentagon
2259uid 3518,0
2260sl 0
2261ro 90
2262xt "19000,109625,20500,110375"
2263)
2264(Line
2265uid 3519,0
2266sl 0
2267ro 90
2268xt "20500,110000,21000,110000"
2269pts [
2270"21000,110000"
2271"20500,110000"
2272]
2273)
2274]
2275)
2276stc 0
2277sf 1
2278tg (WTG
2279uid 3520,0
2280ps "PortIoTextPlaceStrategy"
2281stg "STSignalDisplayStrategy"
2282f (Text
2283uid 3521,0
2284va (VaSet
2285)
2286xt "14200,109500,18000,110500"
2287st "DWRITE"
2288ju 2
2289blo "18000,110300"
2290tm "WireNameMgr"
2291)
2292)
2293)
2294*66 (Net
2295uid 3522,0
2296decl (Decl
2297n "DWRITE"
2298t "std_logic"
2299o 25
2300suid 96,0
2301i "'0'"
2302)
2303declText (MLText
2304uid 3523,0
2305va (VaSet
2306font "Courier New,8,0"
2307)
2308xt "39000,23000,71500,23800"
2309st "DWRITE                : std_logic                      := '0'"
2310)
2311)
2312*67 (PortIoOut
2313uid 3536,0
2314shape (CompositeShape
2315uid 3537,0
2316va (VaSet
2317vasetType 1
2318fg "0,0,32768"
2319)
2320optionalChildren [
2321(Pentagon
2322uid 3538,0
2323sl 0
2324ro 270
2325xt "97500,83625,99000,84375"
2326)
2327(Line
2328uid 3539,0
2329sl 0
2330ro 270
2331xt "97000,84000,97500,84000"
2332pts [
2333"97000,84000"
2334"97500,84000"
2335]
2336)
2337]
2338)
2339stc 0
2340sf 1
2341tg (WTG
2342uid 3540,0
2343ps "PortIoTextPlaceStrategy"
2344stg "STSignalDisplayStrategy"
2345f (Text
2346uid 3541,0
2347va (VaSet
2348)
2349xt "100000,83500,103700,84500"
2350st "DAC_CS"
2351blo "100000,84300"
2352tm "WireNameMgr"
2353)
2354)
2355)
2356*68 (PortIoOut
2357uid 3624,0
2358shape (CompositeShape
2359uid 3625,0
2360va (VaSet
2361vasetType 1
2362fg "0,0,32768"
2363)
2364optionalChildren [
2365(Pentagon
2366uid 3626,0
2367sl 0
2368ro 270
2369xt "99500,96625,101000,97375"
2370)
2371(Line
2372uid 3627,0
2373sl 0
2374ro 270
2375xt "99000,97000,99500,97000"
2376pts [
2377"99000,97000"
2378"99500,97000"
2379]
2380)
2381]
2382)
2383stc 0
2384sf 1
2385tg (WTG
2386uid 3628,0
2387ps "PortIoTextPlaceStrategy"
2388stg "STSignalDisplayStrategy"
2389f (Text
2390uid 3629,0
2391va (VaSet
2392)
2393xt "101750,96500,104650,97500"
2394st "S_CLK"
2395blo "101750,97300"
2396tm "WireNameMgr"
2397)
2398)
2399)
2400*69 (Net
2401uid 3630,0
2402decl (Decl
2403n "S_CLK"
2404t "std_logic"
2405o 42
2406suid 105,0
2407)
2408declText (MLText
2409uid 3631,0
2410va (VaSet
2411font "Courier New,8,0"
2412)
2413xt "39000,36600,57000,37400"
2414st "S_CLK                 : std_logic"
2415)
2416)
2417*70 (Net
2418uid 3632,0
2419decl (Decl
2420n "W_A"
2421t "std_logic_vector"
2422b "(9 DOWNTO 0)"
2423o 45
2424suid 106,0
2425)
2426declText (MLText
2427uid 3633,0
2428va (VaSet
2429font "Courier New,8,0"
2430)
2431xt "39000,39000,67000,39800"
2432st "W_A                   : std_logic_vector(9 DOWNTO 0)"
2433)
2434)
2435*71 (Net
2436uid 3634,0
2437decl (Decl
2438n "W_D"
2439t "std_logic_vector"
2440b "(15 DOWNTO 0)"
2441o 52
2442suid 107,0
2443)
2444declText (MLText
2445uid 3635,0
2446va (VaSet
2447font "Courier New,8,0"
2448)
2449xt "39000,44600,67500,45400"
2450st "W_D                   : std_logic_vector(15 DOWNTO 0)"
2451)
2452)
2453*72 (Net
2454uid 3636,0
2455decl (Decl
2456n "W_RES"
2457t "std_logic"
2458o 48
2459suid 108,0
2460i "'1'"
2461)
2462declText (MLText
2463uid 3637,0
2464va (VaSet
2465font "Courier New,8,0"
2466)
2467xt "39000,41400,71500,42200"
2468st "W_RES                 : std_logic                      := '1'"
2469)
2470)
2471*73 (Net
2472uid 3638,0
2473decl (Decl
2474n "W_RD"
2475t "std_logic"
2476o 47
2477suid 109,0
2478i "'1'"
2479)
2480declText (MLText
2481uid 3639,0
2482va (VaSet
2483font "Courier New,8,0"
2484)
2485xt "39000,40600,71500,41400"
2486st "W_RD                  : std_logic                      := '1'"
2487)
2488)
2489*74 (Net
2490uid 3640,0
2491decl (Decl
2492n "W_WR"
2493t "std_logic"
2494o 50
2495suid 110,0
2496i "'1'"
2497)
2498declText (MLText
2499uid 3641,0
2500va (VaSet
2501font "Courier New,8,0"
2502)
2503xt "39000,43000,71500,43800"
2504st "W_WR                  : std_logic                      := '1'"
2505)
2506)
2507*75 (Net
2508uid 3642,0
2509decl (Decl
2510n "W_INT"
2511t "std_logic"
2512o 16
2513suid 111,0
2514)
2515declText (MLText
2516uid 3643,0
2517va (VaSet
2518font "Courier New,8,0"
2519)
2520xt "39000,15800,57000,16600"
2521st "W_INT                 : std_logic"
2522)
2523)
2524*76 (Net
2525uid 3644,0
2526decl (Decl
2527n "W_CS"
2528t "std_logic"
2529o 46
2530suid 112,0
2531i "'1'"
2532)
2533declText (MLText
2534uid 3645,0
2535va (VaSet
2536font "Courier New,8,0"
2537)
2538xt "39000,39800,71500,40600"
2539st "W_CS                  : std_logic                      := '1'"
2540)
2541)
2542*77 (PortIoInOut
2543uid 3674,0
2544shape (CompositeShape
2545uid 3675,0
2546va (VaSet
2547vasetType 1
2548fg "0,0,32768"
2549)
2550optionalChildren [
2551(Hexagon
2552uid 3676,0
2553sl 0
2554xt "90500,98625,92000,99375"
2555)
2556(Line
2557uid 3677,0
2558sl 0
2559xt "90000,99000,90500,99000"
2560pts [
2561"90000,99000"
2562"90500,99000"
2563]
2564)
2565]
2566)
2567stc 0
2568sf 1
2569tg (WTG
2570uid 3678,0
2571ps "PortIoTextPlaceStrategy"
2572stg "STSignalDisplayStrategy"
2573f (Text
2574uid 3679,0
2575va (VaSet
2576)
2577xt "93000,98500,95700,99500"
2578st "MISO"
2579blo "93000,99300"
2580tm "WireNameMgr"
2581)
2582)
2583)
2584*78 (Net
2585uid 3680,0
2586decl (Decl
2587n "MOSI"
2588t "std_logic"
2589o 31
2590suid 113,0
2591i "'0'"
2592)
2593declText (MLText
2594uid 3681,0
2595va (VaSet
2596font "Courier New,8,0"
2597)
2598xt "39000,27800,71500,28600"
2599st "MOSI                  : std_logic                      := '0'"
2600)
2601)
2602*79 (PortIoOut
2603uid 3688,0
2604shape (CompositeShape
2605uid 3689,0
2606va (VaSet
2607vasetType 1
2608fg "0,0,32768"
2609)
2610optionalChildren [
2611(Pentagon
2612uid 3690,0
2613sl 0
2614ro 270
2615xt "99500,99625,101000,100375"
2616)
2617(Line
2618uid 3691,0
2619sl 0
2620ro 270
2621xt "99000,100000,99500,100000"
2622pts [
2623"99000,100000"
2624"99500,100000"
2625]
2626)
2627]
2628)
2629stc 0
2630sf 1
2631tg (WTG
2632uid 3692,0
2633ps "PortIoTextPlaceStrategy"
2634stg "STSignalDisplayStrategy"
2635f (Text
2636uid 3693,0
2637va (VaSet
2638)
2639xt "102000,99500,104700,100500"
2640st "MOSI"
2641blo "102000,100300"
2642tm "WireNameMgr"
2643)
2644)
2645)
2646*80 (Net
2647uid 3694,0
2648decl (Decl
2649n "MISO"
2650t "std_logic"
2651preAdd 0
2652posAdd 0
2653o 51
2654suid 114,0
2655)
2656declText (MLText
2657uid 3695,0
2658va (VaSet
2659font "Courier New,8,0"
2660)
2661xt "39000,43800,57000,44600"
2662st "MISO                  : std_logic"
2663)
2664)
2665*81 (PortIoOut
2666uid 3716,0
2667shape (CompositeShape
2668uid 3717,0
2669va (VaSet
2670vasetType 1
2671fg "0,0,32768"
2672)
2673optionalChildren [
2674(Pentagon
2675uid 3718,0
2676sl 0
2677ro 270
2678xt "176500,127625,178000,128375"
2679)
2680(Line
2681uid 3719,0
2682sl 0
2683ro 270
2684xt "176000,128000,176500,128000"
2685pts [
2686"176000,128000"
2687"176500,128000"
2688]
2689)
2690]
2691)
2692stc 0
2693sf 1
2694tg (WTG
2695uid 3720,0
2696ps "PortIoTextPlaceStrategy"
2697stg "STSignalDisplayStrategy"
2698f (Text
2699uid 3721,0
2700va (VaSet
2701)
2702xt "179000,127500,185100,128500"
2703st "RS485_C_DE"
2704blo "179000,128300"
2705tm "WireNameMgr"
2706)
2707)
2708)
2709*82 (PortIoOut
2710uid 3722,0
2711shape (CompositeShape
2712uid 3723,0
2713va (VaSet
2714vasetType 1
2715fg "0,0,32768"
2716)
2717optionalChildren [
2718(Pentagon
2719uid 3724,0
2720sl 0
2721ro 270
2722xt "176500,128625,178000,129375"
2723)
2724(Line
2725uid 3725,0
2726sl 0
2727ro 270
2728xt "176000,129000,176500,129000"
2729pts [
2730"176000,129000"
2731"176500,129000"
2732]
2733)
2734]
2735)
2736stc 0
2737sf 1
2738tg (WTG
2739uid 3726,0
2740ps "PortIoTextPlaceStrategy"
2741stg "STSignalDisplayStrategy"
2742f (Text
2743uid 3727,0
2744va (VaSet
2745)
2746xt "179000,128500,185200,129500"
2747st "RS485_C_DO"
2748blo "179000,129300"
2749tm "WireNameMgr"
2750)
2751)
2752)
2753*83 (PortIoOut
2754uid 3728,0
2755shape (CompositeShape
2756uid 3729,0
2757va (VaSet
2758vasetType 1
2759fg "0,0,32768"
2760)
2761optionalChildren [
2762(Pentagon
2763uid 3730,0
2764sl 0
2765ro 270
2766xt "85500,147625,87000,148375"
2767)
2768(Line
2769uid 3731,0
2770sl 0
2771ro 270
2772xt "85000,148000,85500,148000"
2773pts [
2774"85000,148000"
2775"85500,148000"
2776]
2777)
2778]
2779)
2780stc 0
2781sf 1
2782tg (WTG
2783uid 3732,0
2784ps "PortIoTextPlaceStrategy"
2785stg "STSignalDisplayStrategy"
2786f (Text
2787uid 3733,0
2788va (VaSet
2789)
2790xt "88000,147500,94000,148500"
2791st "RS485_E_RE"
2792blo "88000,148300"
2793tm "WireNameMgr"
2794)
2795)
2796)
2797*84 (PortIoOut
2798uid 3734,0
2799shape (CompositeShape
2800uid 3735,0
2801va (VaSet
2802vasetType 1
2803fg "0,0,32768"
2804)
2805optionalChildren [
2806(Pentagon
2807uid 3736,0
2808sl 0
2809ro 270
2810xt "85500,146625,87000,147375"
2811)
2812(Line
2813uid 3737,0
2814sl 0
2815ro 270
2816xt "85000,147000,85500,147000"
2817pts [
2818"85000,147000"
2819"85500,147000"
2820]
2821)
2822]
2823)
2824stc 0
2825sf 1
2826tg (WTG
2827uid 3738,0
2828ps "PortIoTextPlaceStrategy"
2829stg "STSignalDisplayStrategy"
2830f (Text
2831uid 3739,0
2832va (VaSet
2833)
2834xt "88000,146500,94100,147500"
2835st "RS485_E_DE"
2836blo "88000,147300"
2837tm "WireNameMgr"
2838)
2839)
2840)
2841*85 (PortIoOut
2842uid 3740,0
2843shape (CompositeShape
2844uid 3741,0
2845va (VaSet
2846vasetType 1
2847fg "0,0,32768"
2848)
2849optionalChildren [
2850(Pentagon
2851uid 3742,0
2852sl 0
2853ro 270
2854xt "82500,120625,84000,121375"
2855)
2856(Line
2857uid 3743,0
2858sl 0
2859ro 270
2860xt "82000,121000,82500,121000"
2861pts [
2862"82000,121000"
2863"82500,121000"
2864]
2865)
2866]
2867)
2868stc 0
2869sf 1
2870tg (WTG
2871uid 3744,0
2872ps "PortIoTextPlaceStrategy"
2873stg "STSignalDisplayStrategy"
2874f (Text
2875uid 3745,0
2876va (VaSet
2877)
2878xt "85000,120500,89100,121500"
2879st "DENABLE"
2880blo "85000,121300"
2881tm "WireNameMgr"
2882)
2883)
2884)
2885*86 (PortIoOut
2886uid 3752,0
2887shape (CompositeShape
2888uid 3753,0
2889va (VaSet
2890vasetType 1
2891fg "0,0,32768"
2892)
2893optionalChildren [
2894(Pentagon
2895uid 3754,0
2896sl 0
2897ro 270
2898xt "176500,135625,178000,136375"
2899)
2900(Line
2901uid 3755,0
2902sl 0
2903ro 270
2904xt "176000,136000,176500,136000"
2905pts [
2906"176000,136000"
2907"176500,136000"
2908]
2909)
2910]
2911)
2912stc 0
2913sf 1
2914tg (WTG
2915uid 3756,0
2916ps "PortIoTextPlaceStrategy"
2917stg "STSignalDisplayStrategy"
2918f (Text
2919uid 3757,0
2920va (VaSet
2921)
2922xt "179000,135500,182000,136500"
2923st "EE_CS"
2924blo "179000,136300"
2925tm "WireNameMgr"
2926)
2927)
2928)
2929*87 (Net
2930uid 3866,0
2931decl (Decl
2932n "RS485_C_RE"
2933t "std_logic"
2934o 36
2935suid 127,0
2936)
2937declText (MLText
2938uid 3867,0
2939va (VaSet
2940font "Courier New,8,0"
2941)
2942xt "39000,31800,57000,32600"
2943st "RS485_C_RE            : std_logic"
2944)
2945)
2946*88 (Net
2947uid 3868,0
2948decl (Decl
2949n "RS485_C_DE"
2950t "std_logic"
2951o 34
2952suid 128,0
2953)
2954declText (MLText
2955uid 3869,0
2956va (VaSet
2957font "Courier New,8,0"
2958)
2959xt "39000,30200,57000,31000"
2960st "RS485_C_DE            : std_logic"
2961)
2962)
2963*89 (Net
2964uid 3870,0
2965decl (Decl
2966n "RS485_E_RE"
2967t "std_logic"
2968o 39
2969suid 129,0
2970)
2971declText (MLText
2972uid 3871,0
2973va (VaSet
2974font "Courier New,8,0"
2975)
2976xt "39000,34200,57000,35000"
2977st "RS485_E_RE            : std_logic"
2978)
2979)
2980*90 (Net
2981uid 3872,0
2982decl (Decl
2983n "RS485_E_DE"
2984t "std_logic"
2985o 37
2986suid 130,0
2987)
2988declText (MLText
2989uid 3873,0
2990va (VaSet
2991font "Courier New,8,0"
2992)
2993xt "39000,32600,57000,33400"
2994st "RS485_E_DE            : std_logic"
2995)
2996)
2997*91 (Net
2998uid 3874,0
2999decl (Decl
3000n "DENABLE"
3001t "std_logic"
3002o 23
3003suid 131,0
3004i "'0'"
3005)
3006declText (MLText
3007uid 3875,0
3008va (VaSet
3009font "Courier New,8,0"
3010)
3011xt "39000,21400,71500,22200"
3012st "DENABLE               : std_logic                      := '0'"
3013)
3014)
3015*92 (Net
3016uid 3878,0
3017decl (Decl
3018n "EE_CS"
3019t "std_logic"
3020o 29
3021suid 133,0
3022)
3023declText (MLText
3024uid 3879,0
3025va (VaSet
3026font "Courier New,8,0"
3027)
3028xt "39000,26200,57000,27000"
3029st "EE_CS                 : std_logic"
3030)
3031)
3032*93 (PortIoOut
3033uid 4916,0
3034shape (CompositeShape
3035uid 4917,0
3036va (VaSet
3037vasetType 1
3038fg "0,0,32768"
3039)
3040optionalChildren [
3041(Pentagon
3042uid 4918,0
3043sl 0
3044ro 270
3045xt "176500,114625,178000,115375"
3046)
3047(Line
3048uid 4919,0
3049sl 0
3050ro 270
3051xt "176000,115000,176500,115000"
3052pts [
3053"176000,115000"
3054"176500,115000"
3055]
3056)
3057]
3058)
3059stc 0
3060sf 1
3061tg (WTG
3062uid 4920,0
3063ps "PortIoTextPlaceStrategy"
3064stg "STSignalDisplayStrategy"
3065f (Text
3066uid 4921,0
3067va (VaSet
3068)
3069xt "179000,114500,181000,115500"
3070st "D_T"
3071blo "179000,115300"
3072tm "WireNameMgr"
3073)
3074)
3075)
3076*94 (Net
3077uid 5320,0
3078decl (Decl
3079n "D_T"
3080t "std_logic_vector"
3081b "(7 DOWNTO 0)"
3082o 27
3083suid 141,0
3084i "(OTHERS => '0')"
3085)
3086declText (MLText
3087uid 5321,0
3088va (VaSet
3089font "Courier New,8,0"
3090)
3091xt "39000,24600,77500,25400"
3092st "D_T                   : std_logic_vector(7 DOWNTO 0)   := (OTHERS => '0')"
3093)
3094)
3095*95 (PortIoOut
3096uid 6874,0
3097shape (CompositeShape
3098uid 6875,0
3099va (VaSet
3100vasetType 1
3101fg "0,0,32768"
3102)
3103optionalChildren [
3104(Pentagon
3105uid 6876,0
3106sl 0
3107ro 270
3108xt "176500,124625,178000,125375"
3109)
3110(Line
3111uid 6877,0
3112sl 0
3113ro 270
3114xt "176000,125000,176500,125000"
3115pts [
3116"176000,125000"
3117"176500,125000"
3118]
3119)
3120]
3121)
3122stc 0
3123sf 1
3124tg (WTG
3125uid 6878,0
3126ps "PortIoTextPlaceStrategy"
3127stg "STSignalDisplayStrategy"
3128f (Text
3129uid 6879,0
3130va (VaSet
3131)
3132xt "179000,124500,181500,125500"
3133st "D_T2"
3134blo "179000,125300"
3135tm "WireNameMgr"
3136)
3137)
3138)
3139*96 (Net
3140uid 6886,0
3141decl (Decl
3142n "D_T2"
3143t "std_logic_vector"
3144b "(1 DOWNTO 0)"
3145o 28
3146suid 154,0
3147i "(others => '0')"
3148)
3149declText (MLText
3150uid 6887,0
3151va (VaSet
3152font "Courier New,8,0"
3153)
3154xt "39000,25400,77500,26200"
3155st "D_T2                  : std_logic_vector(1 DOWNTO 0)   := (others => '0')"
3156)
3157)
3158*97 (PortIoOut
3159uid 7138,0
3160shape (CompositeShape
3161uid 7139,0
3162va (VaSet
3163vasetType 1
3164fg "0,0,32768"
3165)
3166optionalChildren [
3167(Pentagon
3168uid 7140,0
3169sl 0
3170ro 270
3171xt "176500,117625,178000,118375"
3172)
3173(Line
3174uid 7141,0
3175sl 0
3176ro 270
3177xt "176000,118000,176500,118000"
3178pts [
3179"176000,118000"
3180"176500,118000"
3181]
3182)
3183]
3184)
3185stc 0
3186sf 1
3187tg (WTG
3188uid 7142,0
3189ps "PortIoTextPlaceStrategy"
3190stg "STSignalDisplayStrategy"
3191f (Text
3192uid 7143,0
3193va (VaSet
3194)
3195xt "179000,117500,181400,118500"
3196st "A1_T"
3197blo "179000,118300"
3198tm "WireNameMgr"
3199)
3200)
3201)
3202*98 (Net
3203uid 7150,0
3204decl (Decl
3205n "A1_T"
3206t "std_logic_vector"
3207b "(7 DOWNTO 0)"
3208o 19
3209suid 155,0
3210i "(OTHERS => '0')"
3211)
3212declText (MLText
3213uid 7151,0
3214va (VaSet
3215font "Courier New,8,0"
3216)
3217xt "39000,18200,77500,19000"
3218st "A1_T                  : std_logic_vector(7 DOWNTO 0)   := (OTHERS => '0')"
3219)
3220)
3221*99 (Net
3222uid 9500,0
3223decl (Decl
3224n "CLK_50"
3225t "std_logic"
3226o 54
3227suid 163,0
3228)
3229declText (MLText
3230uid 9501,0
3231va (VaSet
3232font "Courier New,8,0"
3233)
3234xt "39000,47200,61000,48000"
3235st "SIGNAL CLK_50                : std_logic"
3236)
3237)
3238*100 (PortIoOut
3239uid 10296,0
3240shape (CompositeShape
3241uid 10297,0
3242va (VaSet
3243vasetType 1
3244fg "0,0,32768"
3245)
3246optionalChildren [
3247(Pentagon
3248uid 10298,0
3249sl 0
3250ro 270
3251xt "176500,116625,178000,117375"
3252)
3253(Line
3254uid 10299,0
3255sl 0
3256ro 270
3257xt "176000,117000,176500,117000"
3258pts [
3259"176000,117000"
3260"176500,117000"
3261]
3262)
3263]
3264)
3265stc 0
3266sf 1
3267tg (WTG
3268uid 10300,0
3269ps "PortIoTextPlaceStrategy"
3270stg "STSignalDisplayStrategy"
3271f (Text
3272uid 10301,0
3273va (VaSet
3274)
3275xt "179000,116500,181500,117500"
3276st "A0_T"
3277blo "179000,117300"
3278tm "WireNameMgr"
3279)
3280)
3281)
3282*101 (Net
3283uid 10308,0
3284decl (Decl
3285n "A0_T"
3286t "std_logic_vector"
3287b "(7 DOWNTO 0)"
3288o 18
3289suid 166,0
3290i "(others => '0')"
3291)
3292declText (MLText
3293uid 10309,0
3294va (VaSet
3295font "Courier New,8,0"
3296)
3297xt "39000,17400,77500,18200"
3298st "A0_T                  : std_logic_vector(7 DOWNTO 0)   := (others => '0')"
3299)
3300)
3301*102 (HdlText
3302uid 10310,0
3303optionalChildren [
3304*103 (EmbeddedText
3305uid 10316,0
3306commentText (CommentText
3307uid 10317,0
3308ps "CenterOffsetStrategy"
3309shape (Rectangle
3310uid 10318,0
3311va (VaSet
3312vasetType 1
3313fg "65535,65535,65535"
3314lineColor "0,0,32768"
3315lineWidth 2
3316)
3317xt "114000,57000,146000,99000"
3318)
3319oxt "0,0,18000,5000"
3320text (MLText
3321uid 10319,0
3322va (VaSet
3323)
3324xt "114200,57200,135600,99200"
3325st "
3326-- testpins D_T2 are used as MAX3485 outputs.
3327
3328--D_T <= (others => '0');
3329D_T <= w5300_state;
3330--D_T2(0) <= debug_data_valid;
3331D_T2(0) <= debug_data_ram_empty;
3332--D_T2(1) <= socket_tx_free_out(16);
3333
3334D_T2(1) <= TRG_V;
3335--D_T2 <= ( others => '0' );
3336
3337
3338A0_T <= (others => '0');
3339A1_T <= (others => '1');
3340
3341
3342--A0_T <= DG_state;
3343W_T(3 downto 0) <= mem_manager_state;
3344--A1_T(7 downto 4) <= \"1100\";
3345
3346--A0_T <= socket_tx_free_out(7 downto 0);
3347--A0_T <= spi_debug_16bit(7 downto 0);
3348--A1_T <= spi_debug_16bit(15 downto 8);
3349--A1_T <= socket_tx_free_out(15 downto 8);
3350
3351-- check SPI interfac
3352--A1_T(7) <= sclk;
3353--A1_T(6) <= MISO;
3354--A1_T(5) <= mosi1;
3355
3356--A1_T(4) <= dac_cs1;
3357--A1_T( 3 downto 0) <= sensor_cs;
3358
3359
3360--D_T(3 downto 0) <=  counter_result ( 11 downto 8);
3361--D_T(4) <= alarm_refclk_too_low;
3362--D_T(5) <= alarm_refclk_too_high;
3363--D_T(6) <= '0';
3364--D_T(7) <= '0';
3365
3366
3367
3368-- additional MAX3485 is switched to shutdown mode
3369RS485_C_RE <= '1';  --inverted logic
3370RS485_C_DE <= '0';   
3371RS485_C_DO <= '0';
3372-- MAX3485 receiver out pit is fed out... should be HIGH-Z
3373
3374
3375-- EEPROM is not used on FAD. CS is always high.
3376EE_CS <= '1';
3377"
3378tm "HdlTextMgr"
3379wrapOption 3
3380visibleHeight 42000
3381visibleWidth 32000
3382)
3383)
3384)
3385]
3386shape (Rectangle
3387uid 10311,0
3388va (VaSet
3389vasetType 1
3390fg "65535,65535,37120"
3391lineColor "0,0,32768"
3392lineWidth 2
3393)
3394xt "165000,104000,171000,140000"
3395)
3396oxt "0,0,8000,10000"
3397ttg (MlTextGroup
3398uid 10312,0
3399ps "CenterOffsetStrategy"
3400stg "VerticalLayoutStrategy"
3401textVec [
3402*104 (Text
3403uid 10313,0
3404va (VaSet
3405font "Arial,8,1"
3406)
3407xt "168150,107000,169850,108000"
3408st "eb3"
3409blo "168150,107800"
3410tm "HdlTextNameMgr"
3411)
3412*105 (Text
3413uid 10314,0
3414va (VaSet
3415font "Arial,8,1"
3416)
3417xt "168150,108000,168950,109000"
3418st "9"
3419blo "168150,108800"
3420tm "HdlTextNumberMgr"
3421)
3422]
3423)
3424viewicon (ZoomableIcon
3425uid 10315,0
3426sl 0
3427va (VaSet
3428vasetType 1
3429fg "49152,49152,49152"
3430)
3431xt "165250,138250,166750,139750"
3432iconName "TextFile.png"
3433iconMaskName "TextFile.msk"
3434ftype 21
3435)
3436viewiconposition 0
3437)
3438*106 (PortIoOut
3439uid 11104,0
3440shape (CompositeShape
3441uid 11105,0
3442va (VaSet
3443vasetType 1
3444fg "0,0,32768"
3445)
3446optionalChildren [
3447(Pentagon
3448uid 11106,0
3449sl 0
3450ro 270
3451xt "176500,129625,178000,130375"
3452)
3453(Line
3454uid 11107,0
3455sl 0
3456ro 270
3457xt "176000,130000,176500,130000"
3458pts [
3459"176000,130000"
3460"176500,130000"
3461]
3462)
3463]
3464)
3465stc 0
3466sf 1
3467tg (WTG
3468uid 11108,0
3469ps "PortIoTextPlaceStrategy"
3470stg "STSignalDisplayStrategy"
3471f (Text
3472uid 11109,0
3473va (VaSet
3474)
3475xt "179000,129500,185000,130500"
3476st "RS485_C_RE"
3477blo "179000,130300"
3478tm "WireNameMgr"
3479)
3480)
3481)
3482*107 (Net
3483uid 11116,0
3484decl (Decl
3485n "RS485_C_DO"
3486t "std_logic"
3487o 35
3488suid 198,0
3489)
3490declText (MLText
3491uid 11117,0
3492va (VaSet
3493font "Courier New,8,0"
3494)
3495xt "39000,31000,57000,31800"
3496st "RS485_C_DO            : std_logic"
3497)
3498)
3499*108 (PortIoIn
3500uid 11508,0
3501shape (CompositeShape
3502uid 11509,0
3503va (VaSet
3504vasetType 1
3505fg "0,0,32768"
3506)
3507optionalChildren [
3508(Pentagon
3509uid 11510,0
3510sl 0
3511ro 90
3512xt "85500,149625,87000,150375"
3513)
3514(Line
3515uid 11511,0
3516sl 0
3517ro 90
3518xt "85000,150000,85500,150000"
3519pts [
3520"85500,150000"
3521"85000,150000"
3522]
3523)
3524]
3525)
3526stc 0
3527sf 1
3528tg (WTG
3529uid 11512,0
3530ps "PortIoTextPlaceStrategy"
3531stg "STSignalDisplayStrategy"
3532f (Text
3533uid 11513,0
3534va (VaSet
3535)
3536xt "88000,149500,94000,150500"
3537st "RS485_E_DI"
3538blo "88000,150300"
3539tm "WireNameMgr"
3540)
3541)
3542)
3543*109 (Net
3544uid 11520,0
3545decl (Decl
3546n "RS485_E_DI"
3547t "std_logic"
3548o 14
3549suid 200,0
3550)
3551declText (MLText
3552uid 11521,0
3553va (VaSet
3554font "Courier New,8,0"
3555)
3556xt "39000,14200,57000,15000"
3557st "RS485_E_DI            : std_logic"
3558)
3559)
3560*110 (Net
3561uid 11534,0
3562decl (Decl
3563n "RS485_E_DO"
3564t "std_logic"
3565o 38
3566suid 201,0
3567)
3568declText (MLText
3569uid 11535,0
3570va (VaSet
3571font "Courier New,8,0"
3572)
3573xt "39000,33400,57000,34200"
3574st "RS485_E_DO            : std_logic"
3575)
3576)
3577*111 (PortIoOut
3578uid 12326,0
3579shape (CompositeShape
3580uid 12327,0
3581va (VaSet
3582vasetType 1
3583fg "0,0,32768"
3584)
3585optionalChildren [
3586(Pentagon
3587uid 12328,0
3588sl 0
3589ro 270
3590xt "87500,139625,89000,140375"
3591)
3592(Line
3593uid 12329,0
3594sl 0
3595ro 270
3596xt "87000,140000,87500,140000"
3597pts [
3598"87000,140000"
3599"87500,140000"
3600]
3601)
3602]
3603)
3604stc 0
3605sf 1
3606tg (WTG
3607uid 12330,0
3608ps "PortIoTextPlaceStrategy"
3609stg "STSignalDisplayStrategy"
3610f (Text
3611uid 12331,0
3612va (VaSet
3613)
3614xt "89000,139500,91500,140500"
3615st "SRIN"
3616blo "89000,140300"
3617tm "WireNameMgr"
3618)
3619)
3620)
3621*112 (Net
3622uid 12334,0
3623decl (Decl
3624n "SRIN"
3625t "std_logic"
3626o 41
3627suid 203,0
3628i "'0'"
3629)
3630declText (MLText
3631uid 12335,0
3632va (VaSet
3633font "Courier New,8,0"
3634)
3635xt "39000,35800,71500,36600"
3636st "SRIN                  : std_logic                      := '0'"
3637)
3638)
3639*113 (PortIoOut
3640uid 12539,0
3641shape (CompositeShape
3642uid 12540,0
3643va (VaSet
3644vasetType 1
3645fg "0,0,32768"
3646)
3647optionalChildren [
3648(Pentagon
3649uid 12541,0
3650sl 0
3651ro 270
3652xt "87500,140625,89000,141375"
3653)
3654(Line
3655uid 12542,0
3656sl 0
3657ro 270
3658xt "87000,141000,87500,141000"
3659pts [
3660"87000,141000"
3661"87500,141000"
3662]
3663)
3664]
3665)
3666stc 0
3667sf 1
3668tg (WTG
3669uid 12543,0
3670ps "PortIoTextPlaceStrategy"
3671stg "STSignalDisplayStrategy"
3672f (Text
3673uid 12544,0
3674va (VaSet
3675)
3676xt "90000,140500,95200,141500"
3677st "AMBER_LED"
3678blo "90000,141300"
3679tm "WireNameMgr"
3680)
3681)
3682)
3683*114 (PortIoOut
3684uid 12553,0
3685shape (CompositeShape
3686uid 12554,0
3687va (VaSet
3688vasetType 1
3689fg "0,0,32768"
3690)
3691optionalChildren [
3692(Pentagon
3693uid 12555,0
3694sl 0
3695ro 270
3696xt "87500,141625,89000,142375"
3697)
3698(Line
3699uid 12556,0
3700sl 0
3701ro 270
3702xt "87000,142000,87500,142000"
3703pts [
3704"87000,142000"
3705"87500,142000"
3706]
3707)
3708]
3709)
3710stc 0
3711sf 1
3712tg (WTG
3713uid 12557,0
3714ps "PortIoTextPlaceStrategy"
3715stg "STSignalDisplayStrategy"
3716f (Text
3717uid 12558,0
3718va (VaSet
3719)
3720xt "90000,141500,95000,142500"
3721st "GREEN_LED"
3722blo "90000,142300"
3723tm "WireNameMgr"
3724)
3725)
3726)
3727*115 (PortIoOut
3728uid 12567,0
3729shape (CompositeShape
3730uid 12568,0
3731va (VaSet
3732vasetType 1
3733fg "0,0,32768"
3734)
3735optionalChildren [
3736(Pentagon
3737uid 12569,0
3738sl 0
3739ro 270
3740xt "87500,142625,89000,143375"
3741)
3742(Line
3743uid 12570,0
3744sl 0
3745ro 270
3746xt "87000,143000,87500,143000"
3747pts [
3748"87000,143000"
3749"87500,143000"
3750]
3751)
3752]
3753)
3754stc 0
3755sf 1
3756tg (WTG
3757uid 12571,0
3758ps "PortIoTextPlaceStrategy"
3759stg "STSignalDisplayStrategy"
3760f (Text
3761uid 12572,0
3762va (VaSet
3763)
3764xt "90000,142500,94000,143500"
3765st "RED_LED"
3766blo "90000,143300"
3767tm "WireNameMgr"
3768)
3769)
3770)
3771*116 (Net
3772uid 12762,0
3773decl (Decl
3774n "AMBER_LED"
3775t "std_logic"
3776o 20
3777suid 207,0
3778)
3779declText (MLText
3780uid 12763,0
3781va (VaSet
3782font "Courier New,8,0"
3783)
3784xt "39000,19000,57000,19800"
3785st "AMBER_LED             : std_logic"
3786)
3787)
3788*117 (Net
3789uid 12764,0
3790decl (Decl
3791n "GREEN_LED"
3792t "std_logic"
3793o 30
3794suid 208,0
3795)
3796declText (MLText
3797uid 12765,0
3798va (VaSet
3799font "Courier New,8,0"
3800)
3801xt "39000,27000,57000,27800"
3802st "GREEN_LED             : std_logic"
3803)
3804)
3805*118 (Net
3806uid 12766,0
3807decl (Decl
3808n "RED_LED"
3809t "std_logic"
3810o 33
3811suid 209,0
3812)
3813declText (MLText
3814uid 12767,0
3815va (VaSet
3816font "Courier New,8,0"
3817)
3818xt "39000,29400,57000,30200"
3819st "RED_LED               : std_logic"
3820)
3821)
3822*119 (PortIoIn
3823uid 13516,0
3824shape (CompositeShape
3825uid 13517,0
3826va (VaSet
3827vasetType 1
3828fg "0,0,32768"
3829)
3830optionalChildren [
3831(Pentagon
3832uid 13518,0
3833sl 0
3834ro 270
3835xt "20000,80625,21500,81375"
3836)
3837(Line
3838uid 13519,0
3839sl 0
3840ro 270
3841xt "21500,81000,22000,81000"
3842pts [
3843"21500,81000"
3844"22000,81000"
3845]
3846)
3847]
3848)
3849stc 0
3850sf 1
3851tg (WTG
3852uid 13520,0
3853ps "PortIoTextPlaceStrategy"
3854stg "STSignalDisplayStrategy"
3855f (Text
3856uid 13521,0
3857va (VaSet
3858)
3859xt "16700,80500,19000,81500"
3860st "LINE"
3861ju 2
3862blo "19000,81300"
3863tm "WireNameMgr"
3864)
3865)
3866)
3867*120 (Net
3868uid 13528,0
3869decl (Decl
3870n "LINE"
3871t "std_logic_vector"
3872b "( 5 DOWNTO 0 )"
3873o 12
3874suid 210,0
3875)
3876declText (MLText
3877uid 13529,0
3878va (VaSet
3879font "Courier New,8,0"
3880)
3881xt "39000,12600,68000,13400"
3882st "LINE                  : std_logic_vector( 5 DOWNTO 0 )"
3883)
3884)
3885*121 (PortIoIn
3886uid 13628,0
3887shape (CompositeShape
3888uid 13629,0
3889va (VaSet
3890vasetType 1
3891fg "0,0,32768"
3892)
3893optionalChildren [
3894(Pentagon
3895uid 13630,0
3896sl 0
3897ro 270
3898xt "47000,132625,48500,133375"
3899)
3900(Line
3901uid 13631,0
3902sl 0
3903ro 270
3904xt "48500,133000,49000,133000"
3905pts [
3906"48500,133000"
3907"49000,133000"
3908]
3909)
3910]
3911)
3912stc 0
3913sf 1
3914tg (WTG
3915uid 13632,0
3916ps "PortIoTextPlaceStrategy"
3917stg "STSignalDisplayStrategy"
3918f (Text
3919uid 13633,0
3920va (VaSet
3921)
3922xt "42700,132500,46000,133500"
3923st "REFCLK"
3924ju 2
3925blo "46000,133300"
3926tm "WireNameMgr"
3927)
3928)
3929)
3930*122 (Net
3931uid 13640,0
3932decl (Decl
3933n "REFCLK"
3934t "std_logic"
3935o 13
3936suid 211,0
3937)
3938declText (MLText
3939uid 13641,0
3940va (VaSet
3941font "Courier New,8,0"
3942)
3943xt "39000,13400,57000,14200"
3944st "REFCLK                : std_logic"
3945)
3946)
3947*123 (PortIoIn
3948uid 14322,0
3949shape (CompositeShape
3950uid 14323,0
3951va (VaSet
3952vasetType 1
3953fg "0,0,32768"
3954)
3955optionalChildren [
3956(Pentagon
3957uid 14324,0
3958sl 0
3959ro 270
3960xt "47000,131625,48500,132375"
3961)
3962(Line
3963uid 14325,0
3964sl 0
3965ro 270
3966xt "48500,132000,49000,132000"
3967pts [
3968"48500,132000"
3969"49000,132000"
3970]
3971)
3972]
3973)
3974stc 0
3975sf 1
3976tg (WTG
3977uid 14326,0
3978ps "PortIoTextPlaceStrategy"
3979stg "STSignalDisplayStrategy"
3980f (Text
3981uid 14327,0
3982va (VaSet
3983)
3984xt "42900,131500,46000,132500"
3985st "D_T_in"
3986ju 2
3987blo "46000,132300"
3988tm "WireNameMgr"
3989)
3990)
3991)
3992*124 (Net
3993uid 14334,0
3994decl (Decl
3995n "D_T_in"
3996t "std_logic_vector"
3997b "(1 DOWNTO 0)"
3998o 11
3999suid 213,0
4000)
4001declText (MLText
4002uid 14335,0
4003va (VaSet
4004font "Courier New,8,0"
4005)
4006xt "39000,11800,67000,12600"
4007st "D_T_in                : std_logic_vector(1 DOWNTO 0)"
4008)
4009)
4010*125 (Net
4011uid 15173,0
4012decl (Decl
4013n "led"
4014t "std_logic_vector"
4015b "(7 DOWNTO 0)"
4016posAdd 0
4017o 65
4018suid 215,0
4019i "(OTHERS => '0')"
4020)
4021declText (MLText
4022uid 15174,0
4023va (VaSet
4024font "Courier New,8,0"
4025)
4026xt "39000,57600,81000,58400"
4027st "SIGNAL led                   : std_logic_vector(7 DOWNTO 0)   := (OTHERS => '0')"
4028)
4029)
4030*126 (PortIoOut
4031uid 15557,0
4032shape (CompositeShape
4033uid 15558,0
4034va (VaSet
4035vasetType 1
4036fg "0,0,32768"
4037)
4038optionalChildren [
4039(Pentagon
4040uid 15559,0
4041sl 0
4042ro 270
4043xt "85500,148625,87000,149375"
4044)
4045(Line
4046uid 15560,0
4047sl 0
4048ro 270
4049xt "85000,149000,85500,149000"
4050pts [
4051"85000,149000"
4052"85500,149000"
4053]
4054)
4055]
4056)
4057stc 0
4058sf 1
4059tg (WTG
4060uid 15561,0
4061ps "PortIoTextPlaceStrategy"
4062stg "STSignalDisplayStrategy"
4063f (Text
4064uid 15562,0
4065va (VaSet
4066)
4067xt "88000,148500,94200,149500"
4068st "RS485_E_DO"
4069blo "88000,149300"
4070tm "WireNameMgr"
4071)
4072)
4073)
4074*127 (PortIoIn
4075uid 15706,0
4076shape (CompositeShape
4077uid 15707,0
4078va (VaSet
4079vasetType 1
4080fg "0,0,32768"
4081)
4082optionalChildren [
4083(Pentagon
4084uid 15708,0
4085sl 0
4086ro 270
4087xt "47000,136625,48500,137375"
4088)
4089(Line
4090uid 15709,0
4091sl 0
4092ro 270
4093xt "48500,137000,49000,137000"
4094pts [
4095"48500,137000"
4096"49000,137000"
4097]
4098)
4099]
4100)
4101stc 0
4102sf 1
4103tg (WTG
4104uid 15710,0
4105ps "PortIoTextPlaceStrategy"
4106stg "STSignalDisplayStrategy"
4107f (Text
4108uid 15711,0
4109va (VaSet
4110)
4111xt "41900,136500,46000,137500"
4112st "D_PLLLCK"
4113ju 2
4114blo "46000,137300"
4115tm "WireNameMgr"
4116)
4117)
4118)
4119*128 (Net
4120uid 15718,0
4121decl (Decl
4122n "D_PLLLCK"
4123t "std_logic_vector"
4124b "(3 DOWNTO 0)"
4125o 10
4126suid 216,0
4127)
4128declText (MLText
4129uid 15719,0
4130va (VaSet
4131font "Courier New,8,0"
4132)
4133xt "39000,11000,67000,11800"
4134st "D_PLLLCK              : std_logic_vector(3 DOWNTO 0)"
4135)
4136)
4137*129 (PortIoOut
4138uid 15845,0
4139shape (CompositeShape
4140uid 15846,0
4141va (VaSet
4142vasetType 1
4143fg "0,0,32768"
4144)
4145optionalChildren [
4146(Pentagon
4147uid 15847,0
4148sl 0
4149ro 270
4150xt "95500,87625,97000,88375"
4151)
4152(Line
4153uid 15848,0
4154sl 0
4155ro 270
4156xt "95000,88000,95500,88000"
4157pts [
4158"95000,88000"
4159"95500,88000"
4160]
4161)
4162]
4163)
4164stc 0
4165sf 1
4166tg (WTG
4167uid 15849,0
4168ps "PortIoTextPlaceStrategy"
4169stg "STSignalDisplayStrategy"
4170f (Text
4171uid 15850,0
4172va (VaSet
4173)
4174xt "98000,87500,100000,88500"
4175st "TCS"
4176blo "98000,88300"
4177tm "WireNameMgr"
4178)
4179)
4180)
4181*130 (Net
4182uid 15857,0
4183decl (Decl
4184n "TCS"
4185t "std_logic_vector"
4186b "(3 DOWNTO 0)"
4187o 43
4188suid 217,0
4189)
4190declText (MLText
4191uid 15858,0
4192va (VaSet
4193font "Courier New,8,0"
4194)
4195xt "39000,37400,67000,38200"
4196st "TCS                   : std_logic_vector(3 DOWNTO 0)"
4197)
4198)
4199*131 (PortIoOut
4200uid 16057,0
4201shape (CompositeShape
4202uid 16058,0
4203va (VaSet
4204vasetType 1
4205fg "0,0,32768"
4206)
4207optionalChildren [
4208(Pentagon
4209uid 16059,0
4210sl 0
4211ro 90
4212xt "19000,112625,20500,113375"
4213)
4214(Line
4215uid 16060,0
4216sl 0
4217ro 90
4218xt "20500,113000,21000,113000"
4219pts [
4220"21000,113000"
4221"20500,113000"
4222]
4223)
4224]
4225)
4226stc 0
4227sf 1
4228tg (WTG
4229uid 16061,0
4230ps "PortIoTextPlaceStrategy"
4231stg "STSignalDisplayStrategy"
4232f (Text
4233uid 16062,0
4234va (VaSet
4235)
4236xt "14500,112500,18000,113500"
4237st "DSRCLK"
4238ju 2
4239blo "18000,113300"
4240tm "WireNameMgr"
4241)
4242)
4243)
4244*132 (Net
4245uid 16069,0
4246decl (Decl
4247n "DSRCLK"
4248t "std_logic_vector"
4249b "(3 DOWNTO 0)"
4250o 24
4251suid 222,0
4252i "(others => '0')"
4253)
4254declText (MLText
4255uid 16070,0
4256va (VaSet
4257font "Courier New,8,0"
4258)
4259xt "39000,22200,77500,23000"
4260st "DSRCLK                : std_logic_vector(3 DOWNTO 0)   := (others => '0')"
4261)
4262)
4263*133 (Net
4264uid 16245,0
4265decl (Decl
4266n "SRCLK"
4267t "std_logic"
4268o 56
4269suid 225,0
4270i "'0'"
4271)
4272declText (MLText
4273uid 16246,0
4274va (VaSet
4275font "Courier New,8,0"
4276)
4277xt "39000,49600,75000,50400"
4278st "SIGNAL SRCLK                 : std_logic                      := '0'"
4279)
4280)
4281*134 (HdlText
4282uid 16336,0
4283optionalChildren [
4284*135 (EmbeddedText
4285uid 16342,0
4286commentText (CommentText
4287uid 16343,0
4288ps "CenterOffsetStrategy"
4289shape (Rectangle
4290uid 16344,0
4291va (VaSet
4292vasetType 1
4293fg "65535,65535,65535"
4294lineColor "0,0,32768"
4295lineWidth 2
4296)
4297xt "23000,116000,42000,118000"
4298)
4299oxt "0,0,18000,5000"
4300text (MLText
4301uid 16345,0
4302va (VaSet
4303)
4304xt "23200,116200,40600,117200"
4305st "
4306DSRCLK <= ( SRCLK, SRCLK,SRCLK,SRCLK);
4307"
4308tm "HdlTextMgr"
4309wrapOption 3
4310visibleHeight 2000
4311visibleWidth 19000
4312)
4313)
4314)
4315]
4316shape (Rectangle
4317uid 16337,0
4318va (VaSet
4319vasetType 1
4320fg "65535,65535,37120"
4321lineColor "0,0,32768"
4322lineWidth 2
4323)
4324xt "30000,112000,34000,116000"
4325)
4326oxt "0,0,8000,10000"
4327ttg (MlTextGroup
4328uid 16338,0
4329ps "CenterOffsetStrategy"
4330stg "VerticalLayoutStrategy"
4331textVec [
4332*136 (Text
4333uid 16339,0
4334va (VaSet
4335font "Arial,8,1"
4336)
4337xt "30150,112000,33350,113000"
4338st "SRCLK"
4339blo "30150,112800"
4340tm "HdlTextNameMgr"
4341)
4342*137 (Text
4343uid 16340,0
4344va (VaSet
4345font "Arial,8,1"
4346)
4347xt "30150,113000,30950,114000"
4348st "1"
4349blo "30150,113800"
4350tm "HdlTextNumberMgr"
4351)
4352]
4353)
4354viewicon (ZoomableIcon
4355uid 16341,0
4356sl 0
4357va (VaSet
4358vasetType 1
4359fg "49152,49152,49152"
4360)
4361xt "30250,114250,31750,115750"
4362iconName "TextFile.png"
4363iconMaskName "TextFile.msk"
4364ftype 21
4365)
4366viewiconposition 0
4367)
4368*138 (Net
4369uid 16536,0
4370decl (Decl
4371n "alarm_refclk_too_high"
4372t "std_logic"
4373o 58
4374suid 226,0
4375i "'0'"
4376)
4377declText (MLText
4378uid 16537,0
4379va (VaSet
4380font "Courier New,8,0"
4381)
4382xt "39000,51200,75000,52000"
4383st "SIGNAL alarm_refclk_too_high : std_logic                      := '0'"
4384)
4385)
4386*139 (Net
4387uid 16544,0
4388decl (Decl
4389n "alarm_refclk_too_low"
4390t "std_logic"
4391o 59
4392suid 227,0
4393i "'0'"
4394)
4395declText (MLText
4396uid 16545,0
4397va (VaSet
4398font "Courier New,8,0"
4399)
4400xt "39000,52000,75000,52800"
4401st "SIGNAL alarm_refclk_too_low  : std_logic                      := '0'"
4402)
4403)
4404*140 (Net
4405uid 16574,0
4406decl (Decl
4407n "counter_result"
4408t "std_logic_vector"
4409b "(11 downto 0)"
4410o 61
4411suid 230,0
4412i "(others => '0')"
4413)
4414declText (MLText
4415uid 16575,0
4416va (VaSet
4417font "Courier New,8,0"
4418)
4419xt "39000,53600,81000,54400"
4420st "SIGNAL counter_result        : std_logic_vector(11 downto 0)  := (others => '0')"
4421)
4422)
4423*141 (SaComponent
4424uid 17195,0
4425optionalChildren [
4426*142 (CptPort
4427uid 17027,0
4428ps "OnEdgeStrategy"
4429shape (Triangle
4430uid 17028,0
4431ro 90
4432va (VaSet
4433vasetType 1
4434fg "0,65535,0"
4435)
4436xt "80000,70625,80750,71375"
4437)
4438tg (CPTG
4439uid 17029,0
4440ps "CptPortTextPlaceStrategy"
4441stg "RightVerticalLayoutStrategy"
4442f (Text
4443uid 17030,0
4444va (VaSet
4445)
4446xt "74800,70500,79000,71500"
4447st "wiz_reset"
4448ju 2
4449blo "79000,71300"
4450)
4451)
4452thePort (LogicalPort
4453m 1
4454decl (Decl
4455n "wiz_reset"
4456t "std_logic"
4457o 50
4458suid 2,0
4459i "'1'"
4460)
4461)
4462)
4463*143 (CptPort
4464uid 17031,0
4465ps "OnEdgeStrategy"
4466shape (Triangle
4467uid 17032,0
4468ro 90
4469va (VaSet
4470vasetType 1
4471fg "0,65535,0"
4472)
4473xt "80000,119625,80750,120375"
4474)
4475tg (CPTG
4476uid 17033,0
4477ps "CptPortTextPlaceStrategy"
4478stg "RightVerticalLayoutStrategy"
4479f (Text
4480uid 17034,0
4481va (VaSet
4482)
4483xt "74600,119500,79000,120500"
4484st "led : (7:0)"
4485ju 2
4486blo "79000,120300"
4487)
4488)
4489thePort (LogicalPort
4490m 1
4491decl (Decl
4492n "led"
4493t "std_logic_vector"
4494b "(7 DOWNTO 0)"
4495posAdd 0
4496o 38
4497suid 7,0
4498i "(OTHERS => '0')"
4499)
4500)
4501)
4502*144 (CptPort
4503uid 17035,0
4504ps "OnEdgeStrategy"
4505shape (Triangle
4506uid 17036,0
4507ro 90
4508va (VaSet
4509vasetType 1
4510fg "0,65535,0"
4511)
4512xt "51250,77625,52000,78375"
4513)
4514tg (CPTG
4515uid 17037,0
4516ps "CptPortTextPlaceStrategy"
4517stg "VerticalLayoutStrategy"
4518f (Text
4519uid 17038,0
4520va (VaSet
4521)
4522xt "53000,77500,56000,78500"
4523st "trigger"
4524blo "53000,78300"
4525)
4526)
4527thePort (LogicalPort
4528decl (Decl
4529n "trigger"
4530t "std_logic"
4531preAdd 0
4532posAdd 0
4533o 14
4534suid 18,0
4535)
4536)
4537)
4538*145 (CptPort
4539uid 17039,0
4540ps "OnEdgeStrategy"
4541shape (Triangle
4542uid 17040,0
4543ro 270
4544va (VaSet
4545vasetType 1
4546fg "0,65535,0"
4547)
4548xt "51250,89625,52000,90375"
4549)
4550tg (CPTG
4551uid 17041,0
4552ps "CptPortTextPlaceStrategy"
4553stg "VerticalLayoutStrategy"
4554f (Text
4555uid 17042,0
4556va (VaSet
4557)
4558xt "53000,89500,56500,90500"
4559st "adc_oeb"
4560blo "53000,90300"
4561)
4562)
4563thePort (LogicalPort
4564m 1
4565decl (Decl
4566n "adc_oeb"
4567t "std_logic"
4568o 26
4569suid 21,0
4570i "'1'"
4571)
4572)
4573)
4574*146 (CptPort
4575uid 17043,0
4576ps "OnEdgeStrategy"
4577shape (Triangle
4578uid 17044,0
4579ro 90
4580va (VaSet
4581vasetType 1
4582fg "0,65535,0"
4583)
4584xt "51250,80625,52000,81375"
4585)
4586tg (CPTG
4587uid 17045,0
4588ps "CptPortTextPlaceStrategy"
4589stg "VerticalLayoutStrategy"
4590f (Text
4591uid 17046,0
4592va (VaSet
4593)
4594xt "53000,80500,59700,81500"
4595st "board_id : (3:0)"
4596blo "53000,81300"
4597)
4598)
4599thePort (LogicalPort
4600decl (Decl
4601n "board_id"
4602t "std_logic_vector"
4603b "(3 DOWNTO 0)"
4604o 10
4605suid 24,0
4606)
4607)
4608)
4609*147 (CptPort
4610uid 17047,0
4611ps "OnEdgeStrategy"
4612shape (Triangle
4613uid 17048,0
4614ro 90
4615va (VaSet
4616vasetType 1
4617fg "0,65535,0"
4618)
4619xt "51250,81625,52000,82375"
4620)
4621tg (CPTG
4622uid 17049,0
4623ps "CptPortTextPlaceStrategy"
4624stg "VerticalLayoutStrategy"
4625f (Text
4626uid 17050,0
4627va (VaSet
4628)
4629xt "53000,81500,59400,82500"
4630st "crate_id : (1:0)"
4631blo "53000,82300"
4632)
4633)
4634thePort (LogicalPort
4635decl (Decl
4636n "crate_id"
4637t "std_logic_vector"
4638b "(1 DOWNTO 0)"
4639o 11
4640suid 25,0
4641)
4642)
4643)
4644*148 (CptPort
4645uid 17051,0
4646ps "OnEdgeStrategy"
4647shape (Triangle
4648uid 17052,0
4649ro 90
4650va (VaSet
4651vasetType 1
4652fg "0,65535,0"
4653)
4654xt "80000,67625,80750,68375"
4655)
4656tg (CPTG
4657uid 17053,0
4658ps "CptPortTextPlaceStrategy"
4659stg "RightVerticalLayoutStrategy"
4660f (Text
4661uid 17054,0
4662va (VaSet
4663)
4664xt "72100,67500,79000,68500"
4665st "wiz_addr : (9:0)"
4666ju 2
4667blo "79000,68300"
4668)
4669)
4670thePort (LogicalPort
4671m 1
4672decl (Decl
4673n "wiz_addr"
4674t "std_logic_vector"
4675b "(9 DOWNTO 0)"
4676o 47
4677suid 26,0
4678)
4679)
4680)
4681*149 (CptPort
4682uid 17055,0
4683ps "OnEdgeStrategy"
4684shape (Diamond
4685uid 17056,0
4686ro 90
4687va (VaSet
4688vasetType 1
4689fg "0,65535,0"
4690)
4691xt "80000,68625,80750,69375"
4692)
4693tg (CPTG
4694uid 17057,0
4695ps "CptPortTextPlaceStrategy"
4696stg "RightVerticalLayoutStrategy"
4697f (Text
4698uid 17058,0
4699va (VaSet
4700)
4701xt "71800,68500,79000,69500"
4702st "wiz_data : (15:0)"
4703ju 2
4704blo "79000,69300"
4705)
4706)
4707thePort (LogicalPort
4708m 2
4709decl (Decl
4710n "wiz_data"
4711t "std_logic_vector"
4712b "(15 DOWNTO 0)"
4713o 53
4714suid 27,0
4715)
4716)
4717)
4718*150 (CptPort
4719uid 17059,0
4720ps "OnEdgeStrategy"
4721shape (Triangle
4722uid 17060,0
4723ro 90
4724va (VaSet
4725vasetType 1
4726fg "0,65535,0"
4727)
4728xt "80000,74625,80750,75375"
4729)
4730tg (CPTG
4731uid 17061,0
4732ps "CptPortTextPlaceStrategy"
4733stg "RightVerticalLayoutStrategy"
4734f (Text
4735uid 17062,0
4736va (VaSet
4737)
4738xt "76000,74500,79000,75500"
4739st "wiz_cs"
4740ju 2
4741blo "79000,75300"
4742)
4743)
4744thePort (LogicalPort
4745m 1
4746decl (Decl
4747n "wiz_cs"
4748t "std_logic"
4749o 48
4750suid 28,0
4751i "'1'"
4752)
4753)
4754)
4755*151 (CptPort
4756uid 17063,0
4757ps "OnEdgeStrategy"
4758shape (Triangle
4759uid 17064,0
4760ro 90
4761va (VaSet
4762vasetType 1
4763fg "0,65535,0"
4764)
4765xt "80000,72625,80750,73375"
4766)
4767tg (CPTG
4768uid 17065,0
4769ps "CptPortTextPlaceStrategy"
4770stg "RightVerticalLayoutStrategy"
4771f (Text
4772uid 17066,0
4773va (VaSet
4774)
4775xt "75800,72500,79000,73500"
4776st "wiz_wr"
4777ju 2
4778blo "79000,73300"
4779)
4780)
4781thePort (LogicalPort
4782m 1
4783decl (Decl
4784n "wiz_wr"
4785t "std_logic"
4786o 51
4787suid 29,0
4788i "'1'"
4789)
4790)
4791)
4792*152 (CptPort
4793uid 17067,0
4794ps "OnEdgeStrategy"
4795shape (Triangle
4796uid 17068,0
4797ro 90
4798va (VaSet
4799vasetType 1
4800fg "0,65535,0"
4801)
4802xt "80000,71625,80750,72375"
4803)
4804tg (CPTG
4805uid 17069,0
4806ps "CptPortTextPlaceStrategy"
4807stg "RightVerticalLayoutStrategy"
4808f (Text
4809uid 17070,0
4810va (VaSet
4811)
4812xt "75900,71500,79000,72500"
4813st "wiz_rd"
4814ju 2
4815blo "79000,72300"
4816)
4817)
4818thePort (LogicalPort
4819m 1
4820decl (Decl
4821n "wiz_rd"
4822t "std_logic"
4823o 49
4824suid 30,0
4825i "'1'"
4826)
4827)
4828)
4829*153 (CptPort
4830uid 17071,0
4831ps "OnEdgeStrategy"
4832shape (Triangle
4833uid 17072,0
4834ro 270
4835va (VaSet
4836vasetType 1
4837fg "0,65535,0"
4838)
4839xt "80000,73625,80750,74375"
4840)
4841tg (CPTG
4842uid 17073,0
4843ps "CptPortTextPlaceStrategy"
4844stg "RightVerticalLayoutStrategy"
4845f (Text
4846uid 17074,0
4847va (VaSet
4848)
4849xt "75800,73500,79000,74500"
4850st "wiz_int"
4851ju 2
4852blo "79000,74300"
4853)
4854)
4855thePort (LogicalPort
4856decl (Decl
4857n "wiz_int"
4858t "std_logic"
4859o 15
4860suid 31,0
4861)
4862)
4863)
4864*154 (CptPort
4865uid 17075,0
4866ps "OnEdgeStrategy"
4867shape (Triangle
4868uid 17076,0
4869ro 270
4870va (VaSet
4871vasetType 1
4872fg "0,65535,0"
4873)
4874xt "51250,73625,52000,74375"
4875)
4876tg (CPTG
4877uid 17077,0
4878ps "CptPortTextPlaceStrategy"
4879stg "VerticalLayoutStrategy"
4880f (Text
4881uid 17078,0
4882va (VaSet
4883)
4884xt "53000,73500,57800,74500"
4885st "CLK_25_PS"
4886blo "53000,74300"
4887)
4888)
4889thePort (LogicalPort
4890m 1
4891decl (Decl
4892n "CLK_25_PS"
4893t "std_logic"
4894o 17
4895suid 35,0
4896)
4897)
4898)
4899*155 (CptPort
4900uid 17079,0
4901ps "OnEdgeStrategy"
4902shape (Triangle
4903uid 17080,0
4904ro 90
4905va (VaSet
4906vasetType 1
4907fg "0,65535,0"
4908)
4909xt "80000,115625,80750,116375"
4910)
4911tg (CPTG
4912uid 17081,0
4913ps "CptPortTextPlaceStrategy"
4914stg "RightVerticalLayoutStrategy"
4915f (Text
4916uid 17082,0
4917va (VaSet
4918)
4919xt "75700,115500,79000,116500"
4920st "CLK_50"
4921ju 2
4922blo "79000,116300"
4923)
4924)
4925thePort (LogicalPort
4926m 1
4927decl (Decl
4928n "CLK_50"
4929t "std_logic"
4930preAdd 0
4931posAdd 0
4932o 18
4933suid 37,0
4934)
4935)
4936)
4937*156 (CptPort
4938uid 17083,0
4939ps "OnEdgeStrategy"
4940shape (Triangle
4941uid 17084,0
4942ro 90
4943va (VaSet
4944vasetType 1
4945fg "0,65535,0"
4946)
4947xt "51250,67625,52000,68375"
4948)
4949tg (CPTG
4950uid 17085,0
4951ps "CptPortTextPlaceStrategy"
4952stg "VerticalLayoutStrategy"
4953f (Text
4954uid 17086,0
4955va (VaSet
4956)
4957xt "53000,67500,54900,68500"
4958st "CLK"
4959blo "53000,68300"
4960)
4961)
4962thePort (LogicalPort
4963decl (Decl
4964n "CLK"
4965t "std_logic"
4966o 1
4967suid 38,0
4968)
4969)
4970)
4971*157 (CptPort
4972uid 17087,0
4973ps "OnEdgeStrategy"
4974shape (Triangle
4975uid 17088,0
4976ro 90
4977va (VaSet
4978vasetType 1
4979fg "0,65535,0"
4980)
4981xt "51250,88625,52000,89375"
4982)
4983tg (CPTG
4984uid 17089,0
4985ps "CptPortTextPlaceStrategy"
4986stg "VerticalLayoutStrategy"
4987f (Text
4988uid 17090,0
4989va (VaSet
4990)
4991xt "53000,88500,62300,89500"
4992st "adc_otr_array : (3:0)"
4993blo "53000,89300"
4994)
4995)
4996thePort (LogicalPort
4997decl (Decl
4998n "adc_otr_array"
4999t "std_logic_vector"
5000b "(3 DOWNTO 0)"
5001o 9
5002suid 40,0
5003)
5004)
5005)
5006*158 (CptPort
5007uid 17091,0
5008ps "OnEdgeStrategy"
5009shape (Triangle
5010uid 17092,0
5011ro 90
5012va (VaSet
5013vasetType 1
5014fg "0,65535,0"
5015)
5016xt "51250,94625,52000,95375"
5017)
5018tg (CPTG
5019uid 17093,0
5020ps "CptPortTextPlaceStrategy"
5021stg "VerticalLayoutStrategy"
5022f (Text
5023uid 17094,0
5024va (VaSet
5025)
5026xt "53000,94500,59900,95500"
5027st "adc_data_array"
5028blo "53000,95300"
5029)
5030)
5031thePort (LogicalPort
5032decl (Decl
5033n "adc_data_array"
5034t "adc_data_array_type"
5035o 8
5036suid 41,0
5037)
5038)
5039)
5040*159 (CptPort
5041uid 17095,0
5042ps "OnEdgeStrategy"
5043shape (Triangle
5044uid 17096,0
5045ro 270
5046va (VaSet
5047vasetType 1
5048fg "0,65535,0"
5049)
5050xt "51250,108625,52000,109375"
5051)
5052tg (CPTG
5053uid 17097,0
5054ps "CptPortTextPlaceStrategy"
5055stg "VerticalLayoutStrategy"
5056f (Text
5057uid 17098,0
5058va (VaSet
5059)
5060xt "53000,108500,62500,109500"
5061st "drs_channel_id : (3:0)"
5062blo "53000,109300"
5063)
5064)
5065thePort (LogicalPort
5066m 1
5067decl (Decl
5068n "drs_channel_id"
5069t "std_logic_vector"
5070b "(3 downto 0)"
5071o 35
5072suid 48,0
5073i "(others => '0')"
5074)
5075)
5076)
5077*160 (CptPort
5078uid 17099,0
5079ps "OnEdgeStrategy"
5080shape (Triangle
5081uid 17100,0
5082ro 270
5083va (VaSet
5084vasetType 1
5085fg "0,65535,0"
5086)
5087xt "51250,109625,52000,110375"
5088)
5089tg (CPTG
5090uid 17101,0
5091ps "CptPortTextPlaceStrategy"
5092stg "VerticalLayoutStrategy"
5093f (Text
5094uid 17102,0
5095va (VaSet
5096)
5097xt "53000,109500,58200,110500"
5098st "drs_dwrite"
5099blo "53000,110300"
5100)
5101)
5102thePort (LogicalPort
5103m 1
5104decl (Decl
5105n "drs_dwrite"
5106t "std_logic"
5107o 36
5108suid 49,0
5109i "'1'"
5110)
5111)
5112)
5113*161 (CptPort
5114uid 17103,0
5115ps "OnEdgeStrategy"
5116shape (Triangle
5117uid 17104,0
5118ro 90
5119va (VaSet
5120vasetType 1
5121fg "0,65535,0"
5122)
5123xt "51250,104625,52000,105375"
5124)
5125tg (CPTG
5126uid 17105,0
5127ps "CptPortTextPlaceStrategy"
5128stg "VerticalLayoutStrategy"
5129f (Text
5130uid 17106,0
5131va (VaSet
5132)
5133xt "53000,104500,58800,105500"
5134st "SROUT_in_0"
5135blo "53000,105300"
5136)
5137)
5138thePort (LogicalPort
5139decl (Decl
5140n "SROUT_in_0"
5141t "std_logic"
5142o 4
5143suid 52,0
5144)
5145)
5146)
5147*162 (CptPort
5148uid 17107,0
5149ps "OnEdgeStrategy"
5150shape (Triangle
5151uid 17108,0
5152ro 90
5153va (VaSet
5154vasetType 1
5155fg "0,65535,0"
5156)
5157xt "51250,105625,52000,106375"
5158)
5159tg (CPTG
5160uid 17109,0
5161ps "CptPortTextPlaceStrategy"
5162stg "VerticalLayoutStrategy"
5163f (Text
5164uid 17110,0
5165va (VaSet
5166)
5167xt "53000,105500,58700,106500"
5168st "SROUT_in_1"
5169blo "53000,106300"
5170)
5171)
5172thePort (LogicalPort
5173decl (Decl
5174n "SROUT_in_1"
5175t "std_logic"
5176o 5
5177suid 53,0
5178)
5179)
5180)
5181*163 (CptPort
5182uid 17111,0
5183ps "OnEdgeStrategy"
5184shape (Triangle
5185uid 17112,0
5186ro 90
5187va (VaSet
5188vasetType 1
5189fg "0,65535,0"
5190)
5191xt "51250,106625,52000,107375"
5192)
5193tg (CPTG
5194uid 17113,0
5195ps "CptPortTextPlaceStrategy"
5196stg "VerticalLayoutStrategy"
5197f (Text
5198uid 17114,0
5199va (VaSet
5200)
5201xt "53000,106500,58800,107500"
5202st "SROUT_in_2"
5203blo "53000,107300"
5204)
5205)
5206thePort (LogicalPort
5207decl (Decl
5208n "SROUT_in_2"
5209t "std_logic"
5210o 6
5211suid 54,0
5212)
5213)
5214)
5215*164 (CptPort
5216uid 17115,0
5217ps "OnEdgeStrategy"
5218shape (Triangle
5219uid 17116,0
5220ro 90
5221va (VaSet
5222vasetType 1
5223fg "0,65535,0"
5224)
5225xt "51250,107625,52000,108375"
5226)
5227tg (CPTG
5228uid 17117,0
5229ps "CptPortTextPlaceStrategy"
5230stg "VerticalLayoutStrategy"
5231f (Text
5232uid 17118,0
5233va (VaSet
5234)
5235xt "53000,107500,58800,108500"
5236st "SROUT_in_3"
5237blo "53000,108300"
5238)
5239)
5240thePort (LogicalPort
5241decl (Decl
5242n "SROUT_in_3"
5243t "std_logic"
5244o 7
5245suid 55,0
5246)
5247)
5248)
5249*165 (CptPort
5250uid 17119,0
5251ps "OnEdgeStrategy"
5252shape (Triangle
5253uid 17120,0
5254ro 270
5255va (VaSet
5256vasetType 1
5257fg "0,65535,0"
5258)
5259xt "51250,110625,52000,111375"
5260)
5261tg (CPTG
5262uid 17121,0
5263ps "CptPortTextPlaceStrategy"
5264stg "VerticalLayoutStrategy"
5265f (Text
5266uid 17122,0
5267va (VaSet
5268)
5269xt "53000,110500,57200,111500"
5270st "RSRLOAD"
5271blo "53000,111300"
5272)
5273)
5274thePort (LogicalPort
5275m 1
5276decl (Decl
5277n "RSRLOAD"
5278t "std_logic"
5279o 23
5280suid 56,0
5281i "'0'"
5282)
5283)
5284)
5285*166 (CptPort
5286uid 17123,0
5287ps "OnEdgeStrategy"
5288shape (Triangle
5289uid 17124,0
5290ro 270
5291va (VaSet
5292vasetType 1
5293fg "0,65535,0"
5294)
5295xt "51250,112625,52000,113375"
5296)
5297tg (CPTG
5298uid 17125,0
5299ps "CptPortTextPlaceStrategy"
5300stg "VerticalLayoutStrategy"
5301f (Text
5302uid 17126,0
5303va (VaSet
5304)
5305xt "53000,112500,55900,113500"
5306st "SRCLK"
5307blo "53000,113300"
5308)
5309)
5310thePort (LogicalPort
5311m 1
5312decl (Decl
5313n "SRCLK"
5314t "std_logic"
5315o 24
5316suid 57,0
5317i "'0'"
5318)
5319)
5320)
5321*167 (CptPort
5322uid 17127,0
5323ps "OnEdgeStrategy"
5324shape (Triangle
5325uid 17128,0
5326ro 90
5327va (VaSet
5328vasetType 1
5329fg "0,65535,0"
5330)
5331xt "80000,97625,80750,98375"
5332)
5333tg (CPTG
5334uid 17129,0
5335ps "CptPortTextPlaceStrategy"
5336stg "RightVerticalLayoutStrategy"
5337f (Text
5338uid 17130,0
5339va (VaSet
5340)
5341xt "77100,97500,79000,98500"
5342st "sclk"
5343ju 2
5344blo "79000,98300"
5345)
5346)
5347thePort (LogicalPort
5348m 1
5349decl (Decl
5350n "sclk"
5351t "std_logic"
5352o 42
5353suid 62,0
5354)
5355)
5356)
5357*168 (CptPort
5358uid 17131,0
5359ps "OnEdgeStrategy"
5360shape (Diamond
5361uid 17132,0
5362ro 90
5363va (VaSet
5364vasetType 1
5365fg "0,65535,0"
5366)
5367xt "80000,98625,80750,99375"
5368)
5369tg (CPTG
5370uid 17133,0
5371ps "CptPortTextPlaceStrategy"
5372stg "RightVerticalLayoutStrategy"
5373f (Text
5374uid 17134,0
5375va (VaSet
5376)
5377xt "77600,98500,79000,99500"
5378st "sio"
5379ju 2
5380blo "79000,99300"
5381)
5382)
5383thePort (LogicalPort
5384m 2
5385decl (Decl
5386n "sio"
5387t "std_logic"
5388preAdd 0
5389posAdd 0
5390o 52
5391suid 63,0
5392)
5393)
5394)
5395*169 (CptPort
5396uid 17135,0
5397ps "OnEdgeStrategy"
5398shape (Triangle
5399uid 17136,0
5400ro 90
5401va (VaSet
5402vasetType 1
5403fg "0,65535,0"
5404)
5405xt "80000,86625,80750,87375"
5406)
5407tg (CPTG
5408uid 17137,0
5409ps "CptPortTextPlaceStrategy"
5410stg "RightVerticalLayoutStrategy"
5411f (Text
5412uid 17138,0
5413va (VaSet
5414)
5415xt "76000,86500,79000,87500"
5416st "dac_cs"
5417ju 2
5418blo "79000,87300"
5419)
5420)
5421thePort (LogicalPort
5422m 1
5423decl (Decl
5424n "dac_cs"
5425t "std_logic"
5426o 31
5427suid 64,0
5428)
5429)
5430)
5431*170 (CptPort
5432uid 17139,0
5433ps "OnEdgeStrategy"
5434shape (Triangle
5435uid 17140,0
5436ro 90
5437va (VaSet
5438vasetType 1
5439fg "0,65535,0"
5440)
5441xt "80000,88625,80750,89375"
5442)
5443tg (CPTG
5444uid 17141,0
5445ps "CptPortTextPlaceStrategy"
5446stg "RightVerticalLayoutStrategy"
5447f (Text
5448uid 17142,0
5449va (VaSet
5450)
5451xt "72000,88500,79000,89500"
5452st "sensor_cs : (3:0)"
5453ju 2
5454blo "79000,89300"
5455)
5456)
5457thePort (LogicalPort
5458m 1
5459decl (Decl
5460n "sensor_cs"
5461t "std_logic_vector"
5462b "(3 DOWNTO 0)"
5463o 43
5464suid 65,0
5465)
5466)
5467)
5468*171 (CptPort
5469uid 17143,0
5470ps "OnEdgeStrategy"
5471shape (Triangle
5472uid 17144,0
5473ro 90
5474va (VaSet
5475vasetType 1
5476fg "0,65535,0"
5477)
5478xt "80000,99625,80750,100375"
5479)
5480tg (CPTG
5481uid 17145,0
5482ps "CptPortTextPlaceStrategy"
5483stg "RightVerticalLayoutStrategy"
5484f (Text
5485uid 17146,0
5486va (VaSet
5487)
5488xt "77000,99500,79000,100500"
5489st "mosi"
5490ju 2
5491blo "79000,100300"
5492)
5493)
5494thePort (LogicalPort
5495m 1
5496decl (Decl
5497n "mosi"
5498t "std_logic"
5499o 40
5500suid 66,0
5501i "'0'"
5502)
5503)
5504)
5505*172 (CptPort
5506uid 17147,0
5507ps "OnEdgeStrategy"
5508shape (Triangle
5509uid 17148,0
5510ro 90
5511va (VaSet
5512vasetType 1
5513fg "0,65535,0"
5514)
5515xt "80000,120625,80750,121375"
5516)
5517tg (CPTG
5518uid 17149,0
5519ps "CptPortTextPlaceStrategy"
5520stg "RightVerticalLayoutStrategy"
5521f (Text
5522uid 17150,0
5523va (VaSet
5524)
5525xt "75800,120500,79000,121500"
5526st "denable"
5527ju 2
5528blo "79000,121300"
5529)
5530)
5531thePort (LogicalPort
5532m 1
5533decl (Decl
5534n "denable"
5535t "std_logic"
5536eolc "-- default domino wave off"
5537posAdd 0
5538o 34
5539suid 67,0
5540i "'0'"
5541)
5542)
5543)
5544*173 (CptPort
5545uid 17151,0
5546ps "OnEdgeStrategy"
5547shape (Triangle
5548uid 17152,0
5549ro 90
5550va (VaSet
5551vasetType 1
5552fg "0,65535,0"
5553)
5554xt "80000,139625,80750,140375"
5555)
5556tg (CPTG
5557uid 17153,0
5558ps "CptPortTextPlaceStrategy"
5559stg "RightVerticalLayoutStrategy"
5560f (Text
5561uid 17154,0
5562va (VaSet
5563)
5564xt "74800,139500,79000,140500"
5565st "SRIN_out"
5566ju 2
5567blo "79000,140300"
5568)
5569)
5570thePort (LogicalPort
5571m 1
5572decl (Decl
5573n "SRIN_out"
5574t "std_logic"
5575o 25
5576suid 85,0
5577i "'0'"
5578)
5579)
5580)
5581*174 (CptPort
5582uid 17155,0
5583ps "OnEdgeStrategy"
5584shape (Triangle
5585uid 17156,0
5586ro 90
5587va (VaSet
5588vasetType 1
5589fg "0,65535,0"
5590)
5591xt "80000,141625,80750,142375"
5592)
5593tg (CPTG
5594uid 17157,0
5595ps "CptPortTextPlaceStrategy"
5596stg "RightVerticalLayoutStrategy"
5597f (Text
5598uid 17158,0
5599va (VaSet
5600)
5601xt "76600,141500,79000,142500"
5602st "green"
5603ju 2
5604blo "79000,142300"
5605)
5606)
5607thePort (LogicalPort
5608m 1
5609decl (Decl
5610n "green"
5611t "std_logic"
5612o 37
5613suid 86,0
5614)
5615)
5616)
5617*175 (CptPort
5618uid 17159,0
5619ps "OnEdgeStrategy"
5620shape (Triangle
5621uid 17160,0
5622ro 90
5623va (VaSet
5624vasetType 1
5625fg "0,65535,0"
5626)
5627xt "80000,140625,80750,141375"
5628)
5629tg (CPTG
5630uid 17161,0
5631ps "CptPortTextPlaceStrategy"
5632stg "RightVerticalLayoutStrategy"
5633f (Text
5634uid 17162,0
5635va (VaSet
5636)
5637xt "76300,140500,79000,141500"
5638st "amber"
5639ju 2
5640blo "79000,141300"
5641)
5642)
5643thePort (LogicalPort
5644m 1
5645decl (Decl
5646n "amber"
5647t "std_logic"
5648o 29
5649suid 87,0
5650)
5651)
5652)
5653*176 (CptPort
5654uid 17163,0
5655ps "OnEdgeStrategy"
5656shape (Triangle
5657uid 17164,0
5658ro 90
5659va (VaSet
5660vasetType 1
5661fg "0,65535,0"
5662)
5663xt "80000,142625,80750,143375"
5664)
5665tg (CPTG
5666uid 17165,0
5667ps "CptPortTextPlaceStrategy"
5668stg "RightVerticalLayoutStrategy"
5669f (Text
5670uid 17166,0
5671va (VaSet
5672)
5673xt "77300,142500,79000,143500"
5674st "red"
5675ju 2
5676blo "79000,143300"
5677)
5678)
5679thePort (LogicalPort
5680m 1
5681decl (Decl
5682n "red"
5683t "std_logic"
5684o 41
5685suid 88,0
5686)
5687)
5688)
5689*177 (CptPort
5690uid 17167,0
5691ps "OnEdgeStrategy"
5692shape (Triangle
5693uid 17168,0
5694ro 90
5695va (VaSet
5696vasetType 1
5697fg "0,65535,0"
5698)
5699xt "51250,131625,52000,132375"
5700)
5701tg (CPTG
5702uid 17169,0
5703ps "CptPortTextPlaceStrategy"
5704stg "VerticalLayoutStrategy"
5705f (Text
5706uid 17170,0
5707va (VaSet
5708)
5709xt "53000,131500,58500,132500"
5710st "D_T_in : (1:0)"
5711blo "53000,132300"
5712)
5713)
5714thePort (LogicalPort
5715decl (Decl
5716n "D_T_in"
5717t "std_logic_vector"
5718b "(1 DOWNTO 0)"
5719o 2
5720suid 91,0
5721)
5722)
5723)
5724*178 (CptPort
5725uid 17171,0
5726ps "OnEdgeStrategy"
5727shape (Triangle
5728uid 17172,0
5729ro 90
5730va (VaSet
5731vasetType 1
5732fg "0,65535,0"
5733)
5734xt "51250,132625,52000,133375"
5735)
5736tg (CPTG
5737uid 17173,0
5738ps "CptPortTextPlaceStrategy"
5739stg "VerticalLayoutStrategy"
5740f (Text
5741uid 17174,0
5742va (VaSet
5743)
5744xt "53000,132500,59100,133500"
5745st "drs_refclk_in"
5746blo "53000,133300"
5747)
5748)
5749thePort (LogicalPort
5750decl (Decl
5751n "drs_refclk_in"
5752t "std_logic"
5753eolc "-- used to check if DRS REFCLK exsists, if not DENABLE inhibit"
5754o 12
5755suid 92,0
5756)
5757)
5758)
5759*179 (CptPort
5760uid 17175,0
5761ps "OnEdgeStrategy"
5762shape (Triangle
5763uid 17176,0
5764ro 90
5765va (VaSet
5766vasetType 1
5767fg "0,65535,0"
5768)
5769xt "51250,136625,52000,137375"
5770)
5771tg (CPTG
5772uid 17177,0
5773ps "CptPortTextPlaceStrategy"
5774stg "VerticalLayoutStrategy"
5775f (Text
5776uid 17178,0
5777va (VaSet
5778)
5779xt "53000,136500,59700,137500"
5780st "plllock_in : (3:0)"
5781blo "53000,137300"
5782)
5783)
5784thePort (LogicalPort
5785decl (Decl
5786n "plllock_in"
5787t "std_logic_vector"
5788b "(3 DOWNTO 0)"
5789eolc "-- high level, if dominowave is running and DRS PLL locked"
5790o 13
5791suid 93,0
5792)
5793)
5794)
5795*180 (CptPort
5796uid 17179,0
5797ps "OnEdgeStrategy"
5798shape (Triangle
5799uid 17180,0
5800ro 90
5801va (VaSet
5802vasetType 1
5803fg "0,65535,0"
5804)
5805xt "80000,131625,80750,132375"
5806)
5807tg (CPTG
5808uid 17181,0
5809ps "CptPortTextPlaceStrategy"
5810stg "RightVerticalLayoutStrategy"
5811f (Text
5812uid 17182,0
5813va (VaSet
5814)
5815xt "69400,131500,79000,132500"
5816st "counter_result : (11:0)"
5817ju 2
5818blo "79000,132300"
5819)
5820)
5821thePort (LogicalPort
5822m 1
5823decl (Decl
5824n "counter_result"
5825t "std_logic_vector"
5826b "(11 DOWNTO 0)"
5827o 30
5828suid 94,0
5829)
5830)
5831)
5832*181 (CptPort
5833uid 17183,0
5834ps "OnEdgeStrategy"
5835shape (Triangle
5836uid 17184,0
5837ro 90
5838va (VaSet
5839vasetType 1
5840fg "0,65535,0"
5841)
5842xt "80000,129625,80750,130375"
5843)
5844tg (CPTG
5845uid 17185,0
5846ps "CptPortTextPlaceStrategy"
5847stg "RightVerticalLayoutStrategy"
5848f (Text
5849uid 17186,0
5850va (VaSet
5851)
5852xt "69000,129500,79000,130500"
5853st "alarm_refclk_too_high"
5854ju 2
5855blo "79000,130300"
5856)
5857)
5858thePort (LogicalPort
5859m 1
5860decl (Decl
5861n "alarm_refclk_too_high"
5862t "std_logic"
5863o 27
5864suid 95,0
5865)
5866)
5867)
5868*182 (CptPort
5869uid 17187,0
5870ps "OnEdgeStrategy"
5871shape (Triangle
5872uid 17188,0
5873ro 90
5874va (VaSet
5875vasetType 1
5876fg "0,65535,0"
5877)
5878xt "80000,130625,80750,131375"
5879)
5880tg (CPTG
5881uid 17189,0
5882ps "CptPortTextPlaceStrategy"
5883stg "RightVerticalLayoutStrategy"
5884f (Text
5885uid 17190,0
5886va (VaSet
5887)
5888xt "69400,130500,79000,131500"
5889st "alarm_refclk_too_low"
5890ju 2
5891blo "79000,131300"
5892)
5893)
5894thePort (LogicalPort
5895m 1
5896decl (Decl
5897n "alarm_refclk_too_low"
5898t "std_logic"
5899posAdd 0
5900o 28
5901suid 96,0
5902)
5903)
5904)
5905*183 (CptPort
5906uid 17191,0
5907ps "OnEdgeStrategy"
5908shape (Triangle
5909uid 17192,0
5910ro 270
5911va (VaSet
5912vasetType 1
5913fg "0,65535,0"
5914)
5915xt "51250,70625,52000,71375"
5916)
5917tg (CPTG
5918uid 17193,0
5919ps "CptPortTextPlaceStrategy"
5920stg "VerticalLayoutStrategy"
5921f (Text
5922uid 17194,0
5923va (VaSet
5924)
5925xt "53000,70500,57000,71500"
5926st "ADC_CLK"
5927blo "53000,71300"
5928)
5929)
5930thePort (LogicalPort
5931lang 2
5932m 1
5933decl (Decl
5934n "ADC_CLK"
5935t "std_logic"
5936o 16
5937suid 97,0
5938)
5939)
5940)
5941*184 (CptPort
5942uid 17620,0
5943ps "OnEdgeStrategy"
5944shape (Triangle
5945uid 17621,0
5946ro 90
5947va (VaSet
5948vasetType 1
5949fg "0,65535,0"
5950)
5951xt "80000,143625,80750,144375"
5952)
5953tg (CPTG
5954uid 17622,0
5955ps "CptPortTextPlaceStrategy"
5956stg "RightVerticalLayoutStrategy"
5957f (Text
5958uid 17623,0
5959va (VaSet
5960)
5961xt "73400,143500,79000,144500"
5962st "trigger_veto"
5963ju 2
5964blo "79000,144300"
5965)
5966)
5967thePort (LogicalPort
5968m 1
5969decl (Decl
5970n "trigger_veto"
5971t "std_logic"
5972o 45
5973suid 98,0
5974i "'1'"
5975)
5976)
5977)
5978*185 (CptPort
5979uid 17711,0
5980ps "OnEdgeStrategy"
5981shape (Triangle
5982uid 17712,0
5983ro 270
5984va (VaSet
5985vasetType 1
5986fg "0,65535,0"
5987)
5988xt "80000,149625,80750,150375"
5989)
5990tg (CPTG
5991uid 17713,0
5992ps "CptPortTextPlaceStrategy"
5993stg "RightVerticalLayoutStrategy"
5994f (Text
5995uid 17714,0
5996va (VaSet
5997)
5998xt "70900,149500,79000,150500"
5999st "FTM_RS485_rx_d"
6000ju 2
6001blo "79000,150300"
6002)
6003)
6004thePort (LogicalPort
6005decl (Decl
6006n "FTM_RS485_rx_d"
6007t "std_logic"
6008o 3
6009suid 99,0
6010)
6011)
6012)
6013*186 (CptPort
6014uid 17715,0
6015ps "OnEdgeStrategy"
6016shape (Triangle
6017uid 17716,0
6018ro 90
6019va (VaSet
6020vasetType 1
6021fg "0,65535,0"
6022)
6023xt "80000,147625,80750,148375"
6024)
6025tg (CPTG
6026uid 17717,0
6027ps "CptPortTextPlaceStrategy"
6028stg "RightVerticalLayoutStrategy"
6029f (Text
6030uid 17718,0
6031va (VaSet
6032)
6033xt "70600,147500,79000,148500"
6034st "FTM_RS485_rx_en"
6035ju 2
6036blo "79000,148300"
6037)
6038)
6039thePort (LogicalPort
6040m 1
6041decl (Decl
6042n "FTM_RS485_rx_en"
6043t "std_logic"
6044o 20
6045suid 101,0
6046)
6047)
6048)
6049*187 (CptPort
6050uid 17719,0
6051ps "OnEdgeStrategy"
6052shape (Triangle
6053uid 17720,0
6054ro 90
6055va (VaSet
6056vasetType 1
6057fg "0,65535,0"
6058)
6059xt "80000,148625,80750,149375"
6060)
6061tg (CPTG
6062uid 17721,0
6063ps "CptPortTextPlaceStrategy"
6064stg "RightVerticalLayoutStrategy"
6065f (Text
6066uid 17722,0
6067va (VaSet
6068)
6069xt "70900,148500,79000,149500"
6070st "FTM_RS485_tx_d"
6071ju 2
6072blo "79000,149300"
6073)
6074)
6075thePort (LogicalPort
6076m 1
6077decl (Decl
6078n "FTM_RS485_tx_d"
6079t "std_logic"
6080o 21
6081suid 100,0
6082)
6083)
6084)
6085*188 (CptPort
6086uid 17723,0
6087ps "OnEdgeStrategy"
6088shape (Triangle
6089uid 17724,0
6090ro 90
6091va (VaSet
6092vasetType 1
6093fg "0,65535,0"
6094)
6095xt "80000,146625,80750,147375"
6096)
6097tg (CPTG
6098uid 17725,0
6099ps "CptPortTextPlaceStrategy"
6100stg "RightVerticalLayoutStrategy"
6101f (Text
6102uid 17726,0
6103va (VaSet
6104)
6105xt "70600,146500,79000,147500"
6106st "FTM_RS485_tx_en"
6107ju 2
6108blo "79000,147300"
6109)
6110)
6111thePort (LogicalPort
6112m 1
6113decl (Decl
6114n "FTM_RS485_tx_en"
6115t "std_logic"
6116o 22
6117suid 102,0
6118)
6119)
6120)
6121*189 (CptPort
6122uid 17842,0
6123ps "OnEdgeStrategy"
6124shape (Triangle
6125uid 17843,0
6126ro 90
6127va (VaSet
6128vasetType 1
6129fg "0,65535,0"
6130)
6131xt "80000,105625,80750,106375"
6132)
6133tg (CPTG
6134uid 17844,0
6135ps "CptPortTextPlaceStrategy"
6136stg "RightVerticalLayoutStrategy"
6137f (Text
6138uid 17845,0
6139va (VaSet
6140)
6141xt "70600,105500,79000,106500"
6142st "w5300_state : (7:0)"
6143ju 2
6144blo "79000,106300"
6145)
6146)
6147thePort (LogicalPort
6148m 1
6149decl (Decl
6150n "w5300_state"
6151t "std_logic_vector"
6152b "(7 DOWNTO 0)"
6153eolc "-- state is encoded here ... useful for debugging."
6154posAdd 0
6155o 46
6156suid 103,0
6157)
6158)
6159)
6160*190 (CptPort
6161uid 18058,0
6162ps "OnEdgeStrategy"
6163shape (Triangle
6164uid 18059,0
6165ro 90
6166va (VaSet
6167vasetType 1
6168fg "0,65535,0"
6169)
6170xt "80000,106625,80750,107375"
6171)
6172tg (CPTG
6173uid 18060,0
6174ps "CptPortTextPlaceStrategy"
6175stg "RightVerticalLayoutStrategy"
6176f (Text
6177uid 18061,0
6178va (VaSet
6179)
6180xt "68600,106500,79000,107500"
6181st "debug_data_ram_empty"
6182ju 2
6183blo "79000,107300"
6184)
6185)
6186thePort (LogicalPort
6187m 1
6188decl (Decl
6189n "debug_data_ram_empty"
6190t "std_logic"
6191o 32
6192suid 104,0
6193)
6194)
6195)
6196*191 (CptPort
6197uid 18062,0
6198ps "OnEdgeStrategy"
6199shape (Triangle
6200uid 18063,0
6201ro 90
6202va (VaSet
6203vasetType 1
6204fg "0,65535,0"
6205)
6206xt "80000,107625,80750,108375"
6207)
6208tg (CPTG
6209uid 18064,0
6210ps "CptPortTextPlaceStrategy"
6211stg "RightVerticalLayoutStrategy"
6212f (Text
6213uid 18065,0
6214va (VaSet
6215)
6216xt "71500,107500,79000,108500"
6217st "debug_data_valid"
6218ju 2
6219blo "79000,108300"
6220)
6221)
6222thePort (LogicalPort
6223m 1
6224decl (Decl
6225n "debug_data_valid"
6226t "std_logic"
6227o 33
6228suid 105,0
6229)
6230)
6231)
6232*192 (CptPort
6233uid 18187,0
6234ps "OnEdgeStrategy"
6235shape (Triangle
6236uid 18188,0
6237ro 90
6238va (VaSet
6239vasetType 1
6240fg "0,65535,0"
6241)
6242xt "80000,104625,80750,105375"
6243)
6244tg (CPTG
6245uid 18189,0
6246ps "CptPortTextPlaceStrategy"
6247stg "RightVerticalLayoutStrategy"
6248f (Text
6249uid 18190,0
6250va (VaSet
6251)
6252xt "67600,104500,79000,105500"
6253st "mem_manager_state : (3:0)"
6254ju 2
6255blo "79000,105300"
6256)
6257)
6258thePort (LogicalPort
6259lang 2
6260m 1
6261decl (Decl
6262n "mem_manager_state"
6263t "std_logic_vector"
6264b "(3 DOWNTO 0)"
6265eolc "-- state is encoded here ... useful for debugging."
6266posAdd 0
6267o 39
6268suid 106,0
6269)
6270)
6271)
6272*193 (CptPort
6273uid 18322,0
6274ps "OnEdgeStrategy"
6275shape (Triangle
6276uid 18323,0
6277ro 90
6278va (VaSet
6279vasetType 1
6280fg "0,65535,0"
6281)
6282xt "80000,108625,80750,109375"
6283)
6284tg (CPTG
6285uid 18324,0
6286ps "CptPortTextPlaceStrategy"
6287stg "RightVerticalLayoutStrategy"
6288f (Text
6289uid 18325,0
6290va (VaSet
6291)
6292xt "72100,108500,79000,109500"
6293st "DG_state : (7:0)"
6294ju 2
6295blo "79000,109300"
6296)
6297)
6298thePort (LogicalPort
6299m 1
6300decl (Decl
6301n "DG_state"
6302t "std_logic_vector"
6303b "(7 downto 0)"
6304prec "-- for debugging"
6305preAdd 0
6306o 19
6307suid 108,0
6308)
6309)
6310)
6311*194 (CptPort
6312uid 18471,0
6313ps "OnEdgeStrategy"
6314shape (Triangle
6315uid 18472,0
6316ro 90
6317va (VaSet
6318vasetType 1
6319fg "0,65535,0"
6320)
6321xt "80000,150625,80750,151375"
6322)
6323tg (CPTG
6324uid 18473,0
6325ps "CptPortTextPlaceStrategy"
6326stg "RightVerticalLayoutStrategy"
6327f (Text
6328uid 18474,0
6329va (VaSet
6330)
6331xt "67100,150500,79000,151500"
6332st "socket_tx_free_out : (16:0)"
6333ju 2
6334blo "79000,151300"
6335)
6336)
6337thePort (LogicalPort
6338m 1
6339decl (Decl
6340n "socket_tx_free_out"
6341t "std_logic_vector"
6342b "(16 DOWNTO 0)"
6343eolc "-- 17bit value .. that's true"
6344posAdd 0
6345o 44
6346suid 109,0
6347)
6348)
6349)
6350]
6351shape (Rectangle
6352uid 17196,0
6353va (VaSet
6354vasetType 1
6355fg "0,65535,0"
6356lineColor "0,32896,0"
6357lineWidth 2
6358)
6359xt "52000,66000,80000,153000"
6360)
6361oxt "15000,-8000,43000,70000"
6362ttg (MlTextGroup
6363uid 17197,0
6364ps "CenterOffsetStrategy"
6365stg "VerticalLayoutStrategy"
6366textVec [
6367*195 (Text
6368uid 17198,0
6369va (VaSet
6370font "Arial,8,1"
6371)
6372xt "55200,141000,61400,142000"
6373st "FACT_FAD_lib"
6374blo "55200,141800"
6375tm "BdLibraryNameMgr"
6376)
6377*196 (Text
6378uid 17199,0
6379va (VaSet
6380font "Arial,8,1"
6381)
6382xt "55200,142000,59400,143000"
6383st "FAD_main"
6384blo "55200,142800"
6385tm "CptNameMgr"
6386)
6387*197 (Text
6388uid 17200,0
6389va (VaSet
6390font "Arial,8,1"
6391)
6392xt "55200,143000,61000,144000"
6393st "I_board_main"
6394blo "55200,143800"
6395tm "InstanceNameMgr"
6396)
6397]
6398)
6399ga (GenericAssociation
6400uid 17201,0
6401ps "EdgeToEdgeStrategy"
6402matrix (Matrix
6403uid 17202,0
6404text (MLText
6405uid 17203,0
6406va (VaSet
6407font "Courier New,8,0"
6408)
6409xt "52000,65200,81500,66000"
6410st "RAMADDRWIDTH64b = LOG2_OF_RAM_SIZE_64B    ( integer )  "
6411)
6412header ""
6413)
6414elements [
6415(GiElement
6416name "RAMADDRWIDTH64b"
6417type "integer"
6418value "LOG2_OF_RAM_SIZE_64B"
6419)
6420]
6421)
6422viewicon (ZoomableIcon
6423uid 17204,0
6424sl 0
6425va (VaSet
6426vasetType 1
6427fg "49152,49152,49152"
6428)
6429xt "52250,151250,53750,152750"
6430iconName "BlockDiagram.png"
6431iconMaskName "BlockDiagram.msk"
6432ftype 1
6433)
6434viewiconposition 0
6435portVis (PortSigDisplay
6436)
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8272pts [
8273"80750,75000"
8274"90000,75000"
8275]
8276)
8277start &150
8278end &22
8279sat 32
8280eat 32
8281stc 0
8282st 0
8283sf 1
8284si 0
8285tg (WTG
8286uid 438,0
8287ps "ConnStartEndStrategy"
8288stg "STSignalDisplayStrategy"
8289f (Text
8290uid 439,0
8291va (VaSet
8292isHidden 1
8293)
8294xt "82000,74000,84900,75000"
8295st "W_CS"
8296blo "82000,74800"
8297tm "WireNameMgr"
8298)
8299)
8300on &76
8301)
8302*272 (Wire
8303uid 442,0
8304shape (OrthoPolyLine
8305uid 443,0
8306va (VaSet
8307vasetType 3
8308lineWidth 2
8309)
8310xt "80750,69000,90000,69000"
8311pts [
8312"80750,69000"
8313"90000,69000"
8314]
8315)
8316start &149
8317end &23
8318sat 32
8319eat 32
8320sty 1
8321stc 0
8322st 0
8323sf 1
8324si 0
8325tg (WTG
8326uid 446,0
8327ps "ConnStartEndStrategy"
8328stg "STSignalDisplayStrategy"
8329f (Text
8330uid 447,0
8331va (VaSet
8332isHidden 1
8333)
8334xt "82000,68000,84400,69000"
8335st "W_D"
8336blo "82000,68800"
8337tm "WireNameMgr"
8338)
8339)
8340on &71
8341)
8342*273 (Wire
8343uid 450,0
8344shape (OrthoPolyLine
8345uid 451,0
8346va (VaSet
8347vasetType 3
8348)
8349xt "80750,74000,90000,74000"
8350pts [
8351"90000,74000"
8352"80750,74000"
8353]
8354)
8355start &24
8356end &153
8357sat 32
8358eat 32
8359stc 0
8360st 0
8361sf 1
8362si 0
8363tg (WTG
8364uid 454,0
8365ps "ConnStartEndStrategy"
8366stg "STSignalDisplayStrategy"
8367f (Text
8368uid 455,0
8369va (VaSet
8370isHidden 1
8371)
8372xt "82000,73000,85300,74000"
8373st "W_INT"
8374blo "82000,73800"
8375tm "WireNameMgr"
8376)
8377)
8378on &75
8379)
8380*274 (Wire
8381uid 458,0
8382shape (OrthoPolyLine
8383uid 459,0
8384va (VaSet
8385vasetType 3
8386)
8387xt "80750,72000,90000,72000"
8388pts [
8389"80750,72000"
8390"90000,72000"
8391]
8392)
8393start &152
8394end &25
8395sat 32
8396eat 32
8397stc 0
8398st 0
8399sf 1
8400si 0
8401tg (WTG
8402uid 462,0
8403ps "ConnStartEndStrategy"
8404stg "STSignalDisplayStrategy"
8405f (Text
8406uid 463,0
8407va (VaSet
8408isHidden 1
8409)
8410xt "82000,71000,84900,72000"
8411st "W_RD"
8412blo "82000,71800"
8413tm "WireNameMgr"
8414)
8415)
8416on &73
8417)
8418*275 (Wire
8419uid 466,0
8420shape (OrthoPolyLine
8421uid 467,0
8422va (VaSet
8423vasetType 3
8424)
8425xt "80750,73000,90000,73000"
8426pts [
8427"80750,73000"
8428"90000,73000"
8429]
8430)
8431start &151
8432end &26
8433sat 32
8434eat 32
8435stc 0
8436st 0
8437sf 1
8438si 0
8439tg (WTG
8440uid 470,0
8441ps "ConnStartEndStrategy"
8442stg "STSignalDisplayStrategy"
8443f (Text
8444uid 471,0
8445va (VaSet
8446isHidden 1
8447)
8448xt "82000,72000,85200,73000"
8449st "W_WR"
8450blo "82000,72800"
8451tm "WireNameMgr"
8452)
8453)
8454on &74
8455)
8456*276 (Wire
8457uid 1467,0
8458shape (OrthoPolyLine
8459uid 1468,0
8460va (VaSet
8461vasetType 3
8462)
8463xt "30000,95000,51250,95000"
8464pts [
8465"30000,95000"
8466"41000,95000"
8467"51250,95000"
8468]
8469)
8470start &43
8471end &158
8472sat 2
8473eat 32
8474st 0
8475sf 1
8476si 0
8477tg (WTG
8478uid 1471,0
8479ps "ConnStartEndStrategy"
8480stg "STSignalDisplayStrategy"
8481f (Text
8482uid 1472,0
8483va (VaSet
8484)
8485xt "32000,94000,38900,95000"
8486st "adc_data_array"
8487blo "32000,94800"
8488tm "WireNameMgr"
8489)
8490)
8491on &27
8492)
8493*277 (Wire
8494uid 1730,0
8495shape (OrthoPolyLine
8496uid 1731,0
8497va (VaSet
8498vasetType 3
8499lineWidth 2
8500)
8501xt "21000,89000,51250,89000"
8502pts [
8503"21000,89000"
8504"51250,89000"
8505]
8506)
8507start &41
8508end &157
8509sat 32
8510eat 32
8511sty 1
8512stc 0
8513st 0
8514sf 1
8515si 0
8516tg (WTG
8517uid 1734,0
8518ps "ConnStartEndStrategy"
8519stg "STSignalDisplayStrategy"
8520f (Text
8521uid 1735,0
8522va (VaSet
8523isHidden 1
8524)
8525xt "22000,88000,25000,89000"
8526st "A_OTR"
8527blo "22000,88800"
8528tm "WireNameMgr"
8529)
8530)
8531on &42
8532)
8533*278 (Wire
8534uid 1833,0
8535shape (OrthoPolyLine
8536uid 1834,0
8537va (VaSet
8538vasetType 3
8539lineWidth 2
8540)
8541xt "21000,109000,51250,109000"
8542pts [
8543"51250,109000"
8544"21000,109000"
8545]
8546)
8547start &159
8548end &63
8549sat 32
8550eat 32
8551sty 1
8552stc 0
8553st 0
8554sf 1
8555si 0
8556tg (WTG
8557uid 1837,0
8558ps "ConnStartEndStrategy"
8559stg "STSignalDisplayStrategy"
8560f (Text
8561uid 1838,0
8562va (VaSet
8563isHidden 1
8564)
8565xt "22000,108000,24100,109000"
8566st "D_A"
8567blo "22000,108800"
8568tm "WireNameMgr"
8569)
8570)
8571on &64
8572)
8573*279 (Wire
8574uid 1841,0
8575shape (OrthoPolyLine
8576uid 1842,0
8577va (VaSet
8578vasetType 3
8579)
8580xt "21000,110000,51250,110000"
8581pts [
8582"51250,110000"
8583"21000,110000"
8584]
8585)
8586start &160
8587end &65
8588sat 32
8589eat 32
8590stc 0
8591st 0
8592sf 1
8593si 0
8594tg (WTG
8595uid 1845,0
8596ps "ConnStartEndStrategy"
8597stg "STSignalDisplayStrategy"
8598f (Text
8599uid 1846,0
8600va (VaSet
8601isHidden 1
8602)
8603xt "22000,109000,25800,110000"
8604st "DWRITE"
8605blo "22000,109800"
8606tm "WireNameMgr"
8607)
8608)
8609on &66
8610)
8611*280 (Wire
8612uid 1865,0
8613shape (OrthoPolyLine
8614uid 1866,0
8615va (VaSet
8616vasetType 3
8617)
8618xt "21000,105000,51250,105000"
8619pts [
8620"21000,105000"
8621"51250,105000"
8622]
8623)
8624start &55
8625end &161
8626sat 32
8627eat 32
8628stc 0
8629st 0
8630sf 1
8631si 0
8632tg (WTG
8633uid 1869,0
8634ps "ConnStartEndStrategy"
8635stg "STSignalDisplayStrategy"
8636f (Text
8637uid 1870,0
8638va (VaSet
8639isHidden 1
8640)
8641xt "22000,104000,26600,105000"
8642st "D0_SROUT"
8643blo "22000,104800"
8644tm "WireNameMgr"
8645)
8646)
8647on &59
8648)
8649*281 (Wire
8650uid 1873,0
8651shape (OrthoPolyLine
8652uid 1874,0
8653va (VaSet
8654vasetType 3
8655)
8656xt "21000,106000,51250,106000"
8657pts [
8658"21000,106000"
8659"51250,106000"
8660]
8661)
8662start &56
8663end &162
8664sat 32
8665eat 32
8666stc 0
8667st 0
8668sf 1
8669si 0
8670tg (WTG
8671uid 1877,0
8672ps "ConnStartEndStrategy"
8673stg "STSignalDisplayStrategy"
8674f (Text
8675uid 1878,0
8676va (VaSet
8677isHidden 1
8678)
8679xt "22000,105000,26600,106000"
8680st "D1_SROUT"
8681blo "22000,105800"
8682tm "WireNameMgr"
8683)
8684)
8685on &60
8686)
8687*282 (Wire
8688uid 1881,0
8689shape (OrthoPolyLine
8690uid 1882,0
8691va (VaSet
8692vasetType 3
8693)
8694xt "21000,107000,51250,107000"
8695pts [
8696"21000,107000"
8697"51250,107000"
8698]
8699)
8700start &57
8701end &163
8702sat 32
8703eat 32
8704stc 0
8705st 0
8706sf 1
8707si 0
8708tg (WTG
8709uid 1885,0
8710ps "ConnStartEndStrategy"
8711stg "STSignalDisplayStrategy"
8712f (Text
8713uid 1886,0
8714va (VaSet
8715isHidden 1
8716)
8717xt "22000,106000,26600,107000"
8718st "D2_SROUT"
8719blo "22000,106800"
8720tm "WireNameMgr"
8721)
8722)
8723on &61
8724)
8725*283 (Wire
8726uid 1889,0
8727shape (OrthoPolyLine
8728uid 1890,0
8729va (VaSet
8730vasetType 3
8731)
8732xt "21000,108000,51250,108000"
8733pts [
8734"21000,108000"
8735"51250,108000"
8736]
8737)
8738start &58
8739end &164
8740sat 32
8741eat 32
8742stc 0
8743st 0
8744sf 1
8745si 0
8746tg (WTG
8747uid 1893,0
8748ps "ConnStartEndStrategy"
8749stg "STSignalDisplayStrategy"
8750f (Text
8751uid 1894,0
8752va (VaSet
8753isHidden 1
8754)
8755xt "22000,107000,26600,108000"
8756st "D3_SROUT"
8757blo "22000,107800"
8758tm "WireNameMgr"
8759)
8760)
8761on &62
8762)
8763*284 (Wire
8764uid 2409,0
8765shape (OrthoPolyLine
8766uid 2410,0
8767va (VaSet
8768vasetType 3
8769)
8770xt "21000,111000,51250,111000"
8771pts [
8772"51250,111000"
8773"21000,111000"
8774]
8775)
8776start &165
8777end &29
8778sat 32
8779eat 32
8780stc 0
8781st 0
8782sf 1
8783si 0
8784tg (WTG
8785uid 2413,0
8786ps "ConnStartEndStrategy"
8787stg "STSignalDisplayStrategy"
8788f (Text
8789uid 2414,0
8790va (VaSet
8791isHidden 1
8792)
8793xt "22000,110000,26200,111000"
8794st "RSRLOAD"
8795blo "22000,110800"
8796tm "WireNameMgr"
8797)
8798)
8799on &28
8800)
8801*285 (Wire
8802uid 3009,0
8803shape (OrthoPolyLine
8804uid 3010,0
8805va (VaSet
8806vasetType 3
8807)
8808xt "86000,95000,99000,97000"
8809pts [
8810"86000,95000"
8811"99000,97000"
8812]
8813)
8814start &238
8815end &68
8816sat 32
8817eat 32
8818stc 0
8819st 0
8820sf 1
8821si 0
8822tg (WTG
8823uid 3011,0
8824ps "ConnStartEndStrategy"
8825stg "STSignalDisplayStrategy"
8826f (Text
8827uid 3012,0
8828va (VaSet
8829isHidden 1
8830)
8831xt "87000,94000,89900,95000"
8832st "S_CLK"
8833blo "87000,94800"
8834tm "WireNameMgr"
8835)
8836)
8837on &69
8838)
8839*286 (Wire
8840uid 3015,0
8841shape (OrthoPolyLine
8842uid 3016,0
8843va (VaSet
8844vasetType 3
8845)
8846xt "80750,99000,90000,99000"
8847pts [
8848"80750,99000"
8849"90000,99000"
8850]
8851)
8852start &168
8853end &77
8854sat 32
8855eat 32
8856stc 0
8857st 0
8858sf 1
8859si 0
8860tg (WTG
8861uid 3017,0
8862ps "ConnStartEndStrategy"
8863stg "STSignalDisplayStrategy"
8864f (Text
8865uid 3018,0
8866va (VaSet
8867isHidden 1
8868)
8869xt "82750,98000,85450,99000"
8870st "MISO"
8871blo "82750,98800"
8872tm "WireNameMgr"
8873)
8874)
8875on &80
8876)
8877*287 (Wire
8878uid 3027,0
8879shape (OrthoPolyLine
8880uid 3028,0
8881va (VaSet
8882vasetType 3
8883)
8884xt "85000,84000,97000,85000"
8885pts [
8886"85000,85000"
8887"97000,84000"
8888]
8889)
8890start &212
8891end &67
8892ss 0
8893sat 32
8894eat 32
8895stc 0
8896st 0
8897sf 1
8898si 0
8899tg (WTG
8900uid 3031,0
8901ps "ConnStartEndStrategy"
8902stg "STSignalDisplayStrategy"
8903f (Text
8904uid 3032,0
8905va (VaSet
8906isHidden 1
8907)
8908xt "86000,84000,89700,85000"
8909st "DAC_CS"
8910blo "86000,84800"
8911tm "WireNameMgr"
8912)
8913)
8914on &30
8915)
8916*288 (Wire
8917uid 3218,0
8918shape (OrthoPolyLine
8919uid 3219,0
8920va (VaSet
8921vasetType 3
8922)
8923xt "22000,78000,51250,78000"
8924pts [
8925"22000,78000"
8926"51250,78000"
8927]
8928)
8929start &12
8930end &144
8931sat 32
8932eat 32
8933stc 0
8934st 0
8935sf 1
8936si 0
8937tg (WTG
8938uid 3220,0
8939ps "ConnStartEndStrategy"
8940stg "STSignalDisplayStrategy"
8941f (Text
8942uid 3221,0
8943va (VaSet
8944isHidden 1
8945)
8946xt "33000,77000,34900,78000"
8947st "TRG"
8948blo "33000,77800"
8949tm "WireNameMgr"
8950)
8951)
8952on &33
8953)
8954*289 (Wire
8955uid 3260,0
8956shape (OrthoPolyLine
8957uid 3261,0
8958va (VaSet
8959vasetType 3
8960lineWidth 2
8961)
8962xt "-1000,71000,5000,71000"
8963pts [
8964"-1000,71000"
8965"5000,71000"
8966]
8967)
8968start &31
8969end &34
8970sat 32
8971eat 2
8972sty 1
8973stc 0
8974st 0
8975sf 1
8976si 0
8977tg (WTG
8978uid 3264,0
8979ps "ConnStartEndStrategy"
8980stg "STSignalDisplayStrategy"
8981f (Text
8982uid 3265,0
8983va (VaSet
8984isHidden 1
8985)
8986xt "-23000,70000,-20100,71000"
8987st "A_CLK"
8988blo "-23000,70800"
8989tm "WireNameMgr"
8990)
8991)
8992on &38
8993)
8994*290 (Wire
8995uid 3318,0
8996shape (OrthoPolyLine
8997uid 3319,0
8998va (VaSet
8999vasetType 3
9000lineWidth 2
9001)
9002xt "21000,95000,24000,95000"
9003pts [
9004"21000,95000"
9005"24000,95000"
9006]
9007)
9008start &47
9009end &43
9010sat 32
9011eat 1
9012sty 1
9013stc 0
9014st 0
9015sf 1
9016si 0
9017tg (WTG
9018uid 3322,0
9019ps "ConnStartEndStrategy"
9020stg "STSignalDisplayStrategy"
9021f (Text
9022uid 3323,0
9023va (VaSet
9024isHidden 1
9025)
9026xt "23000,94000,25300,95000"
9027st "A0_D"
9028blo "23000,94800"
9029tm "WireNameMgr"
9030)
9031)
9032on &51
9033)
9034*291 (Wire
9035uid 3352,0
9036shape (OrthoPolyLine
9037uid 3353,0
9038va (VaSet
9039vasetType 3
9040lineWidth 2
9041)
9042xt "21000,96000,24000,96000"
9043pts [
9044"21000,96000"
9045"24000,96000"
9046]
9047)
9048start &48
9049end &43
9050sat 32
9051eat 1
9052sty 1
9053stc 0
9054st 0
9055sf 1
9056si 0
9057tg (WTG
9058uid 3356,0
9059ps "ConnStartEndStrategy"
9060stg "STSignalDisplayStrategy"
9061f (Text
9062uid 3357,0
9063va (VaSet
9064isHidden 1
9065)
9066xt "23000,95000,25300,96000"
9067st "A1_D"
9068blo "23000,95800"
9069tm "WireNameMgr"
9070)
9071)
9072on &52
9073)
9074*292 (Wire
9075uid 3360,0
9076shape (OrthoPolyLine
9077uid 3361,0
9078va (VaSet
9079vasetType 3
9080lineWidth 2
9081)
9082xt "21000,97000,24000,97000"
9083pts [
9084"21000,97000"
9085"24000,97000"
9086]
9087)
9088start &49
9089end &43
9090sat 32
9091eat 1
9092sty 1
9093stc 0
9094st 0
9095sf 1
9096si 0
9097tg (WTG
9098uid 3364,0
9099ps "ConnStartEndStrategy"
9100stg "STSignalDisplayStrategy"
9101f (Text
9102uid 3365,0
9103va (VaSet
9104isHidden 1
9105)
9106xt "23000,96000,25300,97000"
9107st "A2_D"
9108blo "23000,96800"
9109tm "WireNameMgr"
9110)
9111)
9112on &53
9113)
9114*293 (Wire
9115uid 3368,0
9116shape (OrthoPolyLine
9117uid 3369,0
9118va (VaSet
9119vasetType 3
9120lineWidth 2
9121)
9122xt "21000,98000,24000,98000"
9123pts [
9124"21000,98000"
9125"24000,98000"
9126]
9127)
9128start &50
9129end &43
9130sat 32
9131eat 1
9132sty 1
9133stc 0
9134st 0
9135sf 1
9136si 0
9137tg (WTG
9138uid 3372,0
9139ps "ConnStartEndStrategy"
9140stg "STSignalDisplayStrategy"
9141f (Text
9142uid 3373,0
9143va (VaSet
9144isHidden 1
9145)
9146xt "23000,97000,25300,98000"
9147st "A3_D"
9148blo "23000,97800"
9149tm "WireNameMgr"
9150)
9151)
9152on &54
9153)
9154*294 (Wire
9155uid 3682,0
9156shape (OrthoPolyLine
9157uid 3683,0
9158va (VaSet
9159vasetType 3
9160)
9161xt "86000,100000,99000,102000"
9162pts [
9163"86000,102000"
9164"99000,100000"
9165]
9166)
9167start &251
9168end &79
9169sat 32
9170eat 32
9171stc 0
9172st 0
9173sf 1
9174si 0
9175tg (WTG
9176uid 3686,0
9177ps "ConnStartEndStrategy"
9178stg "STSignalDisplayStrategy"
9179f (Text
9180uid 3687,0
9181va (VaSet
9182isHidden 1
9183)
9184xt "87000,101000,89700,102000"
9185st "MOSI"
9186blo "87000,101800"
9187tm "WireNameMgr"
9188)
9189)
9190on &78
9191)
9192*295 (Wire
9193uid 3834,0
9194shape (OrthoPolyLine
9195uid 3835,0
9196va (VaSet
9197vasetType 3
9198)
9199xt "171000,136000,176000,136000"
9200pts [
9201"176000,136000"
9202"171000,136000"
9203]
9204)
9205start &86
9206end &102
9207sat 32
9208eat 2
9209stc 0
9210st 0
9211sf 1
9212si 0
9213tg (WTG
9214uid 3838,0
9215ps "ConnStartEndStrategy"
9216stg "STSignalDisplayStrategy"
9217f (Text
9218uid 3839,0
9219va (VaSet
9220isHidden 1
9221)
9222xt "171000,135000,174000,136000"
9223st "EE_CS"
9224blo "171000,135800"
9225tm "WireNameMgr"
9226)
9227)
9228on &92
9229)
9230*296 (Wire
9231uid 4942,0
9232shape (OrthoPolyLine
9233uid 4943,0
9234va (VaSet
9235vasetType 3
9236lineWidth 2
9237)
9238xt "171000,115000,176000,115000"
9239pts [
9240"171000,115000"
9241"176000,115000"
9242]
9243)
9244start &102
9245end &93
9246sat 2
9247eat 32
9248sty 1
9249stc 0
9250st 0
9251sf 1
9252si 0
9253tg (WTG
9254uid 4948,0
9255ps "ConnStartEndStrategy"
9256stg "STSignalDisplayStrategy"
9257f (Text
9258uid 4949,0
9259va (VaSet
9260isHidden 1
9261)
9262xt "172750,112000,174750,113000"
9263st "D_T"
9264blo "172750,112800"
9265tm "WireNameMgr"
9266)
9267)
9268on &94
9269)
9270*297 (Wire
9271uid 6431,0
9272shape (OrthoPolyLine
9273uid 6432,0
9274va (VaSet
9275vasetType 3
9276)
9277xt "80750,121000,82000,121000"
9278pts [
9279"80750,121000"
9280"82000,121000"
9281]
9282)
9283start &172
9284end &85
9285sat 32
9286eat 32
9287stc 0
9288st 0
9289sf 1
9290si 0
9291tg (WTG
9292uid 6435,0
9293ps "ConnStartEndStrategy"
9294stg "STSignalDisplayStrategy"
9295f (Text
9296uid 6436,0
9297va (VaSet
9298isHidden 1
9299)
9300xt "92000,120000,96100,121000"
9301st "DENABLE"
9302blo "92000,120800"
9303tm "WireNameMgr"
9304)
9305)
9306on &91
9307)
9308*298 (Wire
9309uid 7144,0
9310shape (OrthoPolyLine
9311uid 7145,0
9312va (VaSet
9313vasetType 3
9314lineWidth 2
9315)
9316xt "171000,118000,176000,118000"
9317pts [
9318"171000,118000"
9319"176000,118000"
9320]
9321)
9322start &102
9323end &97
9324sat 2
9325eat 32
9326sty 1
9327st 0
9328sf 1
9329si 0
9330tg (WTG
9331uid 7148,0
9332ps "ConnStartEndStrategy"
9333stg "STSignalDisplayStrategy"
9334f (Text
9335uid 7149,0
9336va (VaSet
9337isHidden 1
9338)
9339xt "176000,130000,181300,131000"
9340st "A1_T : (7:0)"
9341blo "176000,130800"
9342tm "WireNameMgr"
9343)
9344)
9345on &98
9346)
9347*299 (Wire
9348uid 9502,0
9349shape (OrthoPolyLine
9350uid 9503,0
9351va (VaSet
9352vasetType 3
9353)
9354xt "80750,116000,85000,116000"
9355pts [
9356"80750,116000"
9357"85000,116000"
9358]
9359)
9360start &155
9361sat 32
9362eat 16
9363st 0
9364sf 1
9365si 0
9366tg (WTG
9367uid 9506,0
9368ps "ConnStartEndStrategy"
9369stg "STSignalDisplayStrategy"
9370f (Text
9371uid 9507,0
9372va (VaSet
9373)
9374xt "86000,115000,89300,116000"
9375st "CLK_50"
9376blo "86000,115800"
9377tm "WireNameMgr"
9378)
9379)
9380on &99
9381)
9382*300 (Wire
9383uid 10302,0
9384shape (OrthoPolyLine
9385uid 10303,0
9386va (VaSet
9387vasetType 3
9388lineWidth 2
9389)
9390xt "171000,117000,176000,117000"
9391pts [
9392"171000,117000"
9393"176000,117000"
9394]
9395)
9396start &102
9397end &100
9398sat 2
9399eat 32
9400sty 1
9401st 0
9402sf 1
9403si 0
9404tg (WTG
9405uid 10306,0
9406ps "ConnStartEndStrategy"
9407stg "STSignalDisplayStrategy"
9408f (Text
9409uid 10307,0
9410va (VaSet
9411isHidden 1
9412)
9413xt "172000,136000,177400,137000"
9414st "A0_T : (7:0)"
9415blo "172000,136800"
9416tm "WireNameMgr"
9417)
9418)
9419on &101
9420)
9421*301 (Wire
9422uid 11514,0
9423shape (OrthoPolyLine
9424uid 11515,0
9425va (VaSet
9426vasetType 3
9427)
9428xt "80750,150000,85000,150000"
9429pts [
9430"85000,150000"
9431"80750,150000"
9432]
9433)
9434start &108
9435end &185
9436es 0
9437sat 32
9438eat 32
9439st 0
9440sf 1
9441si 0
9442tg (WTG
9443uid 11518,0
9444ps "ConnStartEndStrategy"
9445stg "STSignalDisplayStrategy"
9446f (Text
9447uid 11519,0
9448va (VaSet
9449isHidden 1
9450)
9451xt "86000,149000,92000,150000"
9452st "RS485_E_DI"
9453blo "86000,149800"
9454tm "WireNameMgr"
9455)
9456)
9457on &109
9458)
9459*302 (Wire
9460uid 11528,0
9461shape (OrthoPolyLine
9462uid 11529,0
9463va (VaSet
9464vasetType 3
9465)
9466xt "80750,149000,85000,149000"
9467pts [
9468"80750,149000"
9469"85000,149000"
9470]
9471)
9472start &187
9473end &126
9474ss 0
9475sat 32
9476eat 32
9477st 0
9478sf 1
9479si 0
9480tg (WTG
9481uid 11532,0
9482ps "ConnStartEndStrategy"
9483stg "STSignalDisplayStrategy"
9484f (Text
9485uid 11533,0
9486va (VaSet
9487isHidden 1
9488)
9489xt "107000,148000,113200,149000"
9490st "RS485_E_DO"
9491blo "107000,148800"
9492tm "WireNameMgr"
9493)
9494)
9495on &110
9496)
9497*303 (Wire
9498uid 12320,0
9499shape (OrthoPolyLine
9500uid 12321,0
9501va (VaSet
9502vasetType 3
9503)
9504xt "80750,140000,87000,140000"
9505pts [
9506"80750,140000"
9507"87000,140000"
9508]
9509)
9510start &173
9511end &111
9512sat 32
9513eat 32
9514stc 0
9515st 0
9516sf 1
9517si 0
9518tg (WTG
9519uid 12324,0
9520ps "ConnStartEndStrategy"
9521stg "STSignalDisplayStrategy"
9522f (Text
9523uid 12325,0
9524va (VaSet
9525isHidden 1
9526)
9527xt "82000,139000,84500,140000"
9528st "SRIN"
9529blo "82000,139800"
9530tm "WireNameMgr"
9531)
9532)
9533on &112
9534)
9535*304 (Wire
9536uid 12545,0
9537shape (OrthoPolyLine
9538uid 12546,0
9539va (VaSet
9540vasetType 3
9541)
9542xt "80750,141000,87000,141000"
9543pts [
9544"80750,141000"
9545"87000,141000"
9546]
9547)
9548start &175
9549end &113
9550sat 32
9551eat 32
9552st 0
9553sf 1
9554si 0
9555tg (WTG
9556uid 12549,0
9557ps "ConnStartEndStrategy"
9558stg "STSignalDisplayStrategy"
9559f (Text
9560uid 12550,0
9561va (VaSet
9562isHidden 1
9563)
9564xt "83000,140000,88200,141000"
9565st "AMBER_LED"
9566blo "83000,140800"
9567tm "WireNameMgr"
9568)
9569)
9570on &116
9571)
9572*305 (Wire
9573uid 12559,0
9574shape (OrthoPolyLine
9575uid 12560,0
9576va (VaSet
9577vasetType 3
9578)
9579xt "80750,142000,87000,143000"
9580pts [
9581"80750,143000"
9582"87000,142000"
9583]
9584)
9585start &176
9586end &114
9587sat 32
9588eat 32
9589st 0
9590sf 1
9591si 0
9592tg (WTG
9593uid 12563,0
9594ps "ConnStartEndStrategy"
9595stg "STSignalDisplayStrategy"
9596f (Text
9597uid 12564,0
9598va (VaSet
9599isHidden 1
9600)
9601xt "83000,142000,88000,143000"
9602st "GREEN_LED"
9603blo "83000,142800"
9604tm "WireNameMgr"
9605)
9606)
9607on &117
9608)
9609*306 (Wire
9610uid 12573,0
9611shape (OrthoPolyLine
9612uid 12574,0
9613va (VaSet
9614vasetType 3
9615)
9616xt "80750,142000,87000,143000"
9617pts [
9618"80750,142000"
9619"87000,143000"
9620]
9621)
9622start &174
9623end &115
9624sat 32
9625eat 32
9626st 0
9627sf 1
9628si 0
9629tg (WTG
9630uid 12577,0
9631ps "ConnStartEndStrategy"
9632stg "STSignalDisplayStrategy"
9633f (Text
9634uid 12578,0
9635va (VaSet
9636isHidden 1
9637)
9638xt "83000,141000,87000,142000"
9639st "RED_LED"
9640blo "83000,141800"
9641tm "WireNameMgr"
9642)
9643)
9644on &118
9645)
9646*307 (Wire
9647uid 13522,0
9648shape (OrthoPolyLine
9649uid 13523,0
9650va (VaSet
9651vasetType 3
9652lineWidth 2
9653)
9654xt "22000,81000,28000,81000"
9655pts [
9656"22000,81000"
9657"28000,81000"
9658]
9659)
9660start &119
9661end &14
9662sat 32
9663eat 1
9664sty 1
9665st 0
9666sf 1
9667si 0
9668tg (WTG
9669uid 13526,0
9670ps "ConnStartEndStrategy"
9671stg "STSignalDisplayStrategy"
9672f (Text
9673uid 13527,0
9674va (VaSet
9675)
9676xt "22000,80000,27200,81000"
9677st "LINE : (5:0)"
9678blo "22000,80800"
9679tm "WireNameMgr"
9680)
9681)
9682on &120
9683)
9684*308 (Wire
9685uid 13618,0
9686shape (OrthoPolyLine
9687uid 13619,0
9688va (VaSet
9689vasetType 3
9690lineWidth 2
9691)
9692xt "171000,125000,176000,125000"
9693pts [
9694"171000,125000"
9695"176000,125000"
9696]
9697)
9698start &102
9699end &95
9700sat 2
9701eat 32
9702sty 1
9703st 0
9704sf 1
9705si 0
9706tg (WTG
9707uid 13624,0
9708ps "ConnStartEndStrategy"
9709stg "STSignalDisplayStrategy"
9710f (Text
9711uid 13625,0
9712va (VaSet
9713isHidden 1
9714)
9715xt "173000,130000,178300,131000"
9716st "D_T2 : (1:0)"
9717blo "173000,130800"
9718tm "WireNameMgr"
9719)
9720)
9721on &96
9722)
9723*309 (Wire
9724uid 13634,0
9725shape (OrthoPolyLine
9726uid 13635,0
9727va (VaSet
9728vasetType 3
9729)
9730xt "49000,133000,51250,133000"
9731pts [
9732"49000,133000"
9733"51250,133000"
9734]
9735)
9736start &121
9737end &178
9738sat 32
9739eat 32
9740st 0
9741sf 1
9742si 0
9743tg (WTG
9744uid 13638,0
9745ps "ConnStartEndStrategy"
9746stg "STSignalDisplayStrategy"
9747f (Text
9748uid 13639,0
9749va (VaSet
9750isHidden 1
9751)
9752xt "51000,141000,54300,142000"
9753st "REFCLK"
9754blo "51000,141800"
9755tm "WireNameMgr"
9756)
9757)
9758on &122
9759)
9760*310 (Wire
9761uid 13658,0
9762shape (OrthoPolyLine
9763uid 13659,0
9764va (VaSet
9765vasetType 3
9766)
9767xt "80750,147000,85000,147000"
9768pts [
9769"80750,147000"
9770"85000,147000"
9771]
9772)
9773start &188
9774end &84
9775ss 0
9776sat 32
9777eat 32
9778st 0
9779sf 1
9780si 0
9781tg (WTG
9782uid 13664,0
9783ps "ConnStartEndStrategy"
9784stg "STSignalDisplayStrategy"
9785f (Text
9786uid 13665,0
9787va (VaSet
9788isHidden 1
9789)
9790xt "84000,145000,90100,146000"
9791st "RS485_E_DE"
9792blo "84000,145800"
9793tm "WireNameMgr"
9794)
9795)
9796on &90
9797)
9798*311 (Wire
9799uid 14328,0
9800shape (OrthoPolyLine
9801uid 14329,0
9802va (VaSet
9803vasetType 3
9804lineWidth 2
9805)
9806xt "49000,132000,51250,132000"
9807pts [
9808"49000,132000"
9809"51250,132000"
9810]
9811)
9812start &123
9813end &177
9814sat 32
9815eat 32
9816sty 1
9817st 0
9818sf 1
9819si 0
9820tg (WTG
9821uid 14332,0
9822ps "ConnStartEndStrategy"
9823stg "STSignalDisplayStrategy"
9824f (Text
9825uid 14333,0
9826va (VaSet
9827isHidden 1
9828)
9829xt "52000,138000,57900,139000"
9830st "D_T_in : (1:0)"
9831blo "52000,138800"
9832tm "WireNameMgr"
9833)
9834)
9835on &124
9836)
9837*312 (Wire
9838uid 15175,0
9839shape (OrthoPolyLine
9840uid 15176,0
9841va (VaSet
9842vasetType 3
9843lineWidth 2
9844)
9845xt "80750,120000,87000,120000"
9846pts [
9847"80750,120000"
9848"87000,120000"
9849]
9850)
9851start &143
9852sat 32
9853eat 16
9854sty 1
9855st 0
9856sf 1
9857si 0
9858tg (WTG
9859uid 15179,0
9860ps "ConnStartEndStrategy"
9861stg "STSignalDisplayStrategy"
9862f (Text
9863uid 15180,0
9864va (VaSet
9865)
9866xt "82000,119000,86400,120000"
9867st "led : (7:0)"
9868blo "82000,119800"
9869tm "WireNameMgr"
9870)
9871)
9872on &125
9873)
9874*313 (Wire
9875uid 15517,0
9876shape (OrthoPolyLine
9877uid 15518,0
9878va (VaSet
9879vasetType 3
9880)
9881xt "171000,128000,176000,128000"
9882pts [
9883"171000,128000"
9884"176000,128000"
9885]
9886)
9887start &102
9888end &81
9889sat 2
9890eat 32
9891st 0
9892sf 1
9893si 0
9894tg (WTG
9895uid 15523,0
9896ps "ConnStartEndStrategy"
9897stg "STSignalDisplayStrategy"
9898f (Text
9899uid 15524,0
9900va (VaSet
9901isHidden 1
9902)
9903xt "173000,127000,179100,128000"
9904st "RS485_C_DE"
9905blo "173000,127800"
9906tm "WireNameMgr"
9907)
9908)
9909on &88
9910)
9911*314 (Wire
9912uid 15525,0
9913shape (OrthoPolyLine
9914uid 15526,0
9915va (VaSet
9916vasetType 3
9917)
9918xt "171000,129000,176000,129000"
9919pts [
9920"171000,129000"
9921"176000,129000"
9922]
9923)
9924start &102
9925end &82
9926sat 2
9927eat 32
9928st 0
9929sf 1
9930si 0
9931tg (WTG
9932uid 15531,0
9933ps "ConnStartEndStrategy"
9934stg "STSignalDisplayStrategy"
9935f (Text
9936uid 15532,0
9937va (VaSet
9938isHidden 1
9939)
9940xt "173000,128000,179200,129000"
9941st "RS485_C_DO"
9942blo "173000,128800"
9943tm "WireNameMgr"
9944)
9945)
9946on &107
9947)
9948*315 (Wire
9949uid 15533,0
9950shape (OrthoPolyLine
9951uid 15534,0
9952va (VaSet
9953vasetType 3
9954)
9955xt "171000,130000,176000,130000"
9956pts [
9957"171000,130000"
9958"176000,130000"
9959]
9960)
9961start &102
9962end &106
9963sat 2
9964eat 32
9965st 0
9966sf 1
9967si 0
9968tg (WTG
9969uid 15539,0
9970ps "ConnStartEndStrategy"
9971stg "STSignalDisplayStrategy"
9972f (Text
9973uid 15540,0
9974va (VaSet
9975isHidden 1
9976)
9977xt "173000,129000,179000,130000"
9978st "RS485_C_RE"
9979blo "173000,129800"
9980tm "WireNameMgr"
9981)
9982)
9983on &87
9984)
9985*316 (Wire
9986uid 15563,0
9987shape (OrthoPolyLine
9988uid 15564,0
9989va (VaSet
9990vasetType 3
9991)
9992xt "80750,148000,85000,148000"
9993pts [
9994"80750,148000"
9995"85000,148000"
9996]
9997)
9998start &186
9999end &83
10000ss 0
10001sat 32
10002eat 32
10003st 0
10004sf 1
10005si 0
10006tg (WTG
10007uid 15569,0
10008ps "ConnStartEndStrategy"
10009stg "STSignalDisplayStrategy"
10010f (Text
10011uid 15570,0
10012va (VaSet
10013isHidden 1
10014)
10015xt "83000,147000,89000,148000"
10016st "RS485_E_RE"
10017blo "83000,147800"
10018tm "WireNameMgr"
10019)
10020)
10021on &89
10022)
10023*317 (Wire
10024uid 15712,0
10025shape (OrthoPolyLine
10026uid 15713,0
10027va (VaSet
10028vasetType 3
10029lineWidth 2
10030)
10031xt "49000,137000,51250,137000"
10032pts [
10033"49000,137000"
10034"51250,137000"
10035]
10036)
10037start &127
10038end &179
10039sat 32
10040eat 32
10041sty 1
10042st 0
10043sf 1
10044si 0
10045tg (WTG
10046uid 15716,0
10047ps "ConnStartEndStrategy"
10048stg "STSignalDisplayStrategy"
10049f (Text
10050uid 15717,0
10051va (VaSet
10052isHidden 1
10053)
10054xt "51000,136000,58000,137000"
10055st "D_PLLLCK : (3:0)"
10056blo "51000,136800"
10057tm "WireNameMgr"
10058)
10059)
10060on &128
10061)
10062*318 (Wire
10063uid 15851,0
10064shape (OrthoPolyLine
10065uid 15852,0
10066va (VaSet
10067vasetType 3
10068lineWidth 2
10069)
10070xt "85000,88000,95000,90000"
10071pts [
10072"85000,90000"
10073"95000,88000"
10074]
10075)
10076start &225
10077end &129
10078ss 0
10079sat 32
10080eat 32
10081sty 1
10082st 0
10083sf 1
10084si 0
10085tg (WTG
10086uid 15855,0
10087ps "ConnStartEndStrategy"
10088stg "STSignalDisplayStrategy"
10089f (Text
10090uid 15856,0
10091va (VaSet
10092isHidden 1
10093)
10094xt "87000,89000,91900,90000"
10095st "TCS : (3:0)"
10096blo "87000,89800"
10097tm "WireNameMgr"
10098)
10099)
10100on &130
10101)
10102*319 (Wire
10103uid 16063,0
10104shape (OrthoPolyLine
10105uid 16064,0
10106va (VaSet
10107vasetType 3
10108lineWidth 2
10109)
10110xt "21000,113000,30000,113000"
10111pts [
10112"30000,113000"
10113"21000,113000"
10114]
10115)
10116start &134
10117end &131
10118sat 2
10119eat 32
10120sty 1
10121st 0
10122sf 1
10123si 0
10124tg (WTG
10125uid 16067,0
10126ps "ConnStartEndStrategy"
10127stg "STSignalDisplayStrategy"
10128f (Text
10129uid 16068,0
10130va (VaSet
10131isHidden 1
10132)
10133xt "24000,112000,30400,113000"
10134st "DSRCLK : (3:0)"
10135blo "24000,112800"
10136tm "WireNameMgr"
10137)
10138)
10139on &132
10140)
10141*320 (Wire
10142uid 16247,0
10143shape (OrthoPolyLine
10144uid 16248,0
10145va (VaSet
10146vasetType 3
10147)
10148xt "34000,113000,51250,113000"
10149pts [
10150"51250,113000"
10151"34000,113000"
10152]
10153)
10154start &166
10155end &134
10156sat 32
10157eat 1
10158st 0
10159sf 1
10160si 0
10161tg (WTG
10162uid 16251,0
10163ps "ConnStartEndStrategy"
10164stg "STSignalDisplayStrategy"
10165f (Text
10166uid 16252,0
10167va (VaSet
10168)
10169xt "35000,112000,37900,113000"
10170st "SRCLK"
10171blo "35000,112800"
10172tm "WireNameMgr"
10173)
10174)
10175on &133
10176)
10177*321 (Wire
10178uid 16538,0
10179shape (OrthoPolyLine
10180uid 16539,0
10181va (VaSet
10182vasetType 3
10183)
10184xt "80750,130000,92000,130000"
10185pts [
10186"80750,130000"
10187"92000,130000"
10188]
10189)
10190start &181
10191sat 32
10192eat 16
10193st 0
10194sf 1
10195si 0
10196tg (WTG
10197uid 16542,0
10198ps "ConnStartEndStrategy"
10199stg "STSignalDisplayStrategy"
10200f (Text
10201uid 16543,0
10202va (VaSet
10203)
10204xt "82000,129000,92000,130000"
10205st "alarm_refclk_too_high"
10206blo "82000,129800"
10207tm "WireNameMgr"
10208)
10209)
10210on &138
10211)
10212*322 (Wire
10213uid 16546,0
10214shape (OrthoPolyLine
10215uid 16547,0
10216va (VaSet
10217vasetType 3
10218)
10219xt "80750,131000,91000,131000"
10220pts [
10221"80750,131000"
10222"91000,131000"
10223]
10224)
10225start &182
10226sat 32
10227eat 16
10228st 0
10229sf 1
10230si 0
10231tg (WTG
10232uid 16550,0
10233ps "ConnStartEndStrategy"
10234stg "STSignalDisplayStrategy"
10235f (Text
10236uid 16551,0
10237va (VaSet
10238)
10239xt "82000,130000,91600,131000"
10240st "alarm_refclk_too_low"
10241blo "82000,130800"
10242tm "WireNameMgr"
10243)
10244)
10245on &139
10246)
10247*323 (Wire
10248uid 16576,0
10249shape (OrthoPolyLine
10250uid 16577,0
10251va (VaSet
10252vasetType 3
10253lineWidth 2
10254)
10255xt "80750,132000,92000,132000"
10256pts [
10257"80750,132000"
10258"92000,132000"
10259]
10260)
10261start &180
10262sat 32
10263eat 16
10264sty 1
10265st 0
10266sf 1
10267si 0
10268tg (WTG
10269uid 16580,0
10270ps "ConnStartEndStrategy"
10271stg "STSignalDisplayStrategy"
10272f (Text
10273uid 16581,0
10274va (VaSet
10275)
10276xt "82000,131000,91600,132000"
10277st "counter_result : (11:0)"
10278blo "82000,131800"
10279tm "WireNameMgr"
10280)
10281)
10282on &140
10283)
10284*324 (Wire
10285uid 17296,0
10286shape (OrthoPolyLine
10287uid 17297,0
10288va (VaSet
10289vasetType 3
10290)
10291xt "13000,71000,51250,71000"
10292pts [
10293"51250,71000"
10294"13000,71000"
10295]
10296)
10297start &183
10298end &34
10299sat 32
10300eat 1
10301st 0
10302sf 1
10303si 0
10304tg (WTG
10305uid 17300,0
10306ps "ConnStartEndStrategy"
10307stg "STSignalDisplayStrategy"
10308f (Text
10309uid 17301,0
10310va (VaSet
10311)
10312xt "14000,70000,18000,71000"
10313st "ADC_CLK"
10314blo "14000,70800"
10315tm "WireNameMgr"
10316)
10317)
10318on &198
10319)
10320*325 (Wire
10321uid 17407,0
10322shape (OrthoPolyLine
10323uid 17408,0
10324va (VaSet
10325vasetType 3
10326)
10327xt "80750,144000,87000,144000"
10328pts [
10329"80750,144000"
10330"87000,144000"
10331]
10332)
10333start &184
10334end &199
10335sat 32
10336eat 32
10337st 0
10338sf 1
10339si 0
10340tg (WTG
10341uid 17411,0
10342ps "ConnStartEndStrategy"
10343stg "STSignalDisplayStrategy"
10344f (Text
10345uid 17412,0
10346va (VaSet
10347isHidden 1
10348)
10349xt "83000,143000,85900,144000"
10350st "TRG_V"
10351blo "83000,143800"
10352tm "WireNameMgr"
10353)
10354)
10355on &200
10356)
10357*326 (Wire
10358uid 17848,0
10359shape (OrthoPolyLine
10360uid 17849,0
10361va (VaSet
10362vasetType 3
10363lineWidth 2
10364)
10365xt "80750,106000,91000,106000"
10366pts [
10367"80750,106000"
10368"91000,106000"
10369]
10370)
10371start &189
10372sat 32
10373eat 16
10374sty 1
10375st 0
10376sf 1
10377si 0
10378tg (WTG
10379uid 17852,0
10380ps "ConnStartEndStrategy"
10381stg "STSignalDisplayStrategy"
10382f (Text
10383uid 17853,0
10384va (VaSet
10385)
10386xt "82000,105000,90400,106000"
10387st "w5300_state : (7:0)"
10388blo "82000,105800"
10389tm "WireNameMgr"
10390)
10391)
10392on &201
10393)
10394*327 (Wire
10395uid 17856,0
10396shape (OrthoPolyLine
10397uid 17857,0
10398va (VaSet
10399vasetType 3
10400lineWidth 2
10401)
10402xt "153000,115000,165000,115000"
10403pts [
10404"153000,115000"
10405"165000,115000"
10406]
10407)
10408end &102
10409sat 16
10410eat 1
10411sty 1
10412st 0
10413sf 1
10414si 0
10415tg (WTG
10416uid 17862,0
10417ps "ConnStartEndStrategy"
10418stg "STSignalDisplayStrategy"
10419f (Text
10420uid 17863,0
10421va (VaSet
10422)
10423xt "157000,114000,165400,115000"
10424st "w5300_state : (7:0)"
10425blo "157000,114800"
10426tm "WireNameMgr"
10427)
10428)
10429on &201
10430)
10431*328 (Wire
10432uid 18068,0
10433shape (OrthoPolyLine
10434uid 18069,0
10435va (VaSet
10436vasetType 3
10437)
10438xt "80750,107000,93000,107000"
10439pts [
10440"80750,107000"
10441"93000,107000"
10442]
10443)
10444start &190
10445sat 32
10446eat 16
10447st 0
10448sf 1
10449si 0
10450tg (WTG
10451uid 18072,0
10452ps "ConnStartEndStrategy"
10453stg "STSignalDisplayStrategy"
10454f (Text
10455uid 18073,0
10456va (VaSet
10457)
10458xt "82000,106000,92400,107000"
10459st "debug_data_ram_empty"
10460blo "82000,106800"
10461tm "WireNameMgr"
10462)
10463)
10464on &202
10465)
10466*329 (Wire
10467uid 18076,0
10468shape (OrthoPolyLine
10469uid 18077,0
10470va (VaSet
10471vasetType 3
10472)
10473xt "80750,108000,91000,108000"
10474pts [
10475"80750,108000"
10476"91000,108000"
10477]
10478)
10479start &191
10480sat 32
10481eat 16
10482st 0
10483sf 1
10484si 0
10485tg (WTG
10486uid 18080,0
10487ps "ConnStartEndStrategy"
10488stg "STSignalDisplayStrategy"
10489f (Text
10490uid 18081,0
10491va (VaSet
10492)
10493xt "82000,107000,89500,108000"
10494st "debug_data_valid"
10495blo "82000,107800"
10496tm "WireNameMgr"
10497)
10498)
10499on &203
10500)
10501*330 (Wire
10502uid 18207,0
10503shape (OrthoPolyLine
10504uid 18208,0
10505va (VaSet
10506vasetType 3
10507lineWidth 2
10508)
10509xt "80750,105000,94000,105000"
10510pts [
10511"80750,105000"
10512"94000,105000"
10513]
10514)
10515start &192
10516sat 32
10517eat 16
10518sty 1
10519st 0
10520sf 1
10521si 0
10522tg (WTG
10523uid 18211,0
10524ps "ConnStartEndStrategy"
10525stg "STSignalDisplayStrategy"
10526f (Text
10527uid 18212,0
10528va (VaSet
10529)
10530xt "82000,104000,93400,105000"
10531st "mem_manager_state : (3:0)"
10532blo "82000,104800"
10533tm "WireNameMgr"
10534)
10535)
10536on &204
10537)
10538*331 (Wire
10539uid 18328,0
10540shape (OrthoPolyLine
10541uid 18329,0
10542va (VaSet
10543vasetType 3
10544lineWidth 2
10545)
10546xt "80750,109000,90000,109000"
10547pts [
10548"80750,109000"
10549"90000,109000"
10550]
10551)
10552start &193
10553sat 32
10554eat 16
10555sty 1
10556st 0
10557sf 1
10558si 0
10559tg (WTG
10560uid 18332,0
10561ps "ConnStartEndStrategy"
10562stg "STSignalDisplayStrategy"
10563f (Text
10564uid 18333,0
10565va (VaSet
10566)
10567xt "82000,108000,88900,109000"
10568st "DG_state : (7:0)"
10569blo "82000,108800"
10570tm "WireNameMgr"
10571)
10572)
10573on &205
10574)
10575*332 (Wire
10576uid 18336,0
10577shape (OrthoPolyLine
10578uid 18337,0
10579va (VaSet
10580vasetType 3
10581lineWidth 2
10582)
10583xt "151000,125000,161000,125000"
10584pts [
10585"151000,125000"
10586"161000,125000"
10587]
10588)
10589sat 16
10590eat 16
10591sty 1
10592st 0
10593sf 1
10594si 0
10595tg (WTG
10596uid 18342,0
10597ps "ConnStartEndStrategy"
10598stg "STSignalDisplayStrategy"
10599f (Text
10600uid 18343,0
10601va (VaSet
10602)
10603xt "153000,124000,159900,125000"
10604st "DG_state : (7:0)"
10605blo "153000,124800"
10606tm "WireNameMgr"
10607)
10608)
10609on &205
10610)
10611*333 (Wire
10612uid 18352,0
10613shape (OrthoPolyLine
10614uid 18353,0
10615va (VaSet
10616vasetType 3
10617)
10618xt "149000,127000,159000,127000"
10619pts [
10620"149000,127000"
10621"159000,127000"
10622]
10623)
10624sat 16
10625eat 16
10626st 0
10627sf 1
10628si 0
10629tg (WTG
10630uid 18358,0
10631ps "ConnStartEndStrategy"
10632stg "STSignalDisplayStrategy"
10633f (Text
10634uid 18359,0
10635va (VaSet
10636)
10637xt "151000,126000,158500,127000"
10638st "debug_data_valid"
10639blo "151000,126800"
10640tm "WireNameMgr"
10641)
10642)
10643on &203
10644)
10645*334 (Wire
10646uid 18360,0
10647shape (OrthoPolyLine
10648uid 18361,0
10649va (VaSet
10650vasetType 3
10651)
10652xt "152000,119000,165000,119000"
10653pts [
10654"152000,119000"
10655"165000,119000"
10656]
10657)
10658end &102
10659sat 16
10660eat 1
10661st 0
10662sf 1
10663si 0
10664tg (WTG
10665uid 18366,0
10666ps "ConnStartEndStrategy"
10667stg "STSignalDisplayStrategy"
10668f (Text
10669uid 18367,0
10670va (VaSet
10671)
10672xt "154000,118000,165400,119000"
10673st "mem_manager_state : (3:0)"
10674blo "154000,118800"
10675tm "WireNameMgr"
10676)
10677)
10678on &204
10679)
10680*335 (Wire
10681uid 18477,0
10682shape (OrthoPolyLine
10683uid 18478,0
10684va (VaSet
10685vasetType 3
10686lineWidth 2
10687)
10688xt "80750,151000,95000,151000"
10689pts [
10690"80750,151000"
10691"95000,151000"
10692]
10693)
10694start &194
10695sat 32
10696eat 16
10697sty 1
10698st 0
10699sf 1
10700si 0
10701tg (WTG
10702uid 18481,0
10703ps "ConnStartEndStrategy"
10704stg "STSignalDisplayStrategy"
10705f (Text
10706uid 18482,0
10707va (VaSet
10708)
10709xt "82000,150000,93900,151000"
10710st "socket_tx_free_out : (16:0)"
10711blo "82000,150800"
10712tm "WireNameMgr"
10713)
10714)
10715on &206
10716)
10717*336 (Wire
10718uid 18808,0
10719shape (OrthoPolyLine
10720uid 18809,0
10721va (VaSet
10722vasetType 3
10723lineWidth 2
10724)
10725xt "171000,119000,176000,119000"
10726pts [
10727"171000,119000"
10728"176000,119000"
10729]
10730)
10731start &102
10732end &207
10733sat 2
10734eat 32
10735sty 1
10736st 0
10737sf 1
10738si 0
10739tg (WTG
10740uid 18812,0
10741ps "ConnStartEndStrategy"
10742stg "STSignalDisplayStrategy"
10743f (Text
10744uid 18813,0
10745va (VaSet
10746isHidden 1
10747)
10748xt "173000,118000,178200,119000"
10749st "W_T : (3:0)"
10750blo "173000,118800"
10751tm "WireNameMgr"
10752)
10753)
10754on &208
10755)
10756*337 (Wire
10757uid 18923,0
10758shape (OrthoPolyLine
10759uid 18924,0
10760va (VaSet
10761vasetType 3
10762)
10763xt "152000,117000,165000,117000"
10764pts [
10765"152000,117000"
10766"165000,117000"
10767]
10768)
10769end &102
10770sat 16
10771eat 1
10772st 0
10773sf 1
10774si 0
10775tg (WTG
10776uid 18929,0
10777ps "ConnStartEndStrategy"
10778stg "STSignalDisplayStrategy"
10779f (Text
10780uid 18930,0
10781va (VaSet
10782)
10783xt "153000,116000,164900,117000"
10784st "socket_tx_free_out : (16:0)"
10785blo "153000,116800"
10786tm "WireNameMgr"
10787)
10788)
10789on &206
10790)
10791*338 (Wire
10792uid 19161,0
10793shape (OrthoPolyLine
10794uid 19162,0
10795va (VaSet
10796vasetType 3
10797)
10798xt "155000,120000,165000,120000"
10799pts [
10800"155000,120000"
10801"165000,120000"
10802]
10803)
10804end &102
10805sat 16
10806eat 1
10807st 0
10808sf 1
10809si 0
10810tg (WTG
10811uid 19167,0
10812ps "ConnStartEndStrategy"
10813stg "STSignalDisplayStrategy"
10814f (Text
10815uid 19168,0
10816va (VaSet
10817)
10818xt "157000,119000,159900,120000"
10819st "TRG_V"
10820blo "157000,119800"
10821tm "WireNameMgr"
10822)
10823)
10824on &200
10825)
10826*339 (Wire
10827uid 19169,0
10828shape (OrthoPolyLine
10829uid 19170,0
10830va (VaSet
10831vasetType 3
10832)
10833xt "155000,121000,165000,121000"
10834pts [
10835"155000,121000"
10836"165000,121000"
10837]
10838)
10839end &102
10840sat 16
10841eat 1
10842st 0
10843sf 1
10844si 0
10845tg (WTG
10846uid 19175,0
10847ps "ConnStartEndStrategy"
10848stg "STSignalDisplayStrategy"
10849f (Text
10850uid 19176,0
10851va (VaSet
10852)
10853xt "157000,120000,167400,121000"
10854st "debug_data_ram_empty"
10855blo "157000,120800"
10856tm "WireNameMgr"
10857)
10858)
10859on &202
10860)
10861*340 (Wire
10862uid 19533,0
10863shape (OrthoPolyLine
10864uid 19534,0
10865va (VaSet
10866vasetType 3
10867)
10868xt "80750,85000,82000,87000"
10869pts [
10870"80750,87000"
10871"82000,87000"
10872"82000,85000"
10873]
10874)
10875start &169
10876end &210
10877sat 32
10878eat 32
10879st 0
10880sf 1
10881si 0
10882tg (WTG
10883uid 19535,0
10884ps "ConnStartEndStrategy"
10885stg "STSignalDisplayStrategy"
10886f (Text
10887uid 19536,0
10888va (VaSet
10889)
10890xt "82750,86000,86150,87000"
10891st "dac_cs1"
10892blo "82750,86800"
10893tm "WireNameMgr"
10894)
10895)
10896on &261
10897)
10898*341 (Wire
10899uid 19539,0
10900shape (OrthoPolyLine
10901uid 19540,0
10902va (VaSet
10903vasetType 3
10904)
10905xt "80750,89000,82000,90000"
10906pts [
10907"80750,89000"
10908"82000,89000"
10909"82000,90000"
10910]
10911)
10912start &170
10913end &223
10914sat 32
10915eat 32
10916st 0
10917sf 1
10918si 0
10919tg (WTG
10920uid 19541,0
10921ps "ConnStartEndStrategy"
10922stg "STSignalDisplayStrategy"
10923f (Text
10924uid 19542,0
10925va (VaSet
10926)
10927xt "82750,88000,89750,89000"
10928st "sensor_cs : (3:0)"
10929blo "82750,88800"
10930tm "WireNameMgr"
10931)
10932)
10933on &262
10934)
10935*342 (Wire
10936uid 19545,0
10937shape (OrthoPolyLine
10938uid 19546,0
10939va (VaSet
10940vasetType 3
10941)
10942xt "80750,95000,83000,98000"
10943pts [
10944"80750,98000"
10945"83000,98000"
10946"83000,95000"
10947]
10948)
10949start &167
10950end &236
10951sat 32
10952eat 32
10953st 0
10954sf 1
10955si 0
10956tg (WTG
10957uid 19547,0
10958ps "ConnStartEndStrategy"
10959stg "STSignalDisplayStrategy"
10960f (Text
10961uid 19548,0
10962va (VaSet
10963)
10964xt "82750,97000,84650,98000"
10965st "sclk"
10966blo "82750,97800"
10967tm "WireNameMgr"
10968)
10969)
10970on &263
10971)
10972*343 (Wire
10973uid 19551,0
10974shape (OrthoPolyLine
10975uid 19552,0
10976va (VaSet
10977vasetType 3
10978)
10979xt "80750,100000,83000,102000"
10980pts [
10981"83000,102000"
10982"80750,102000"
10983"80750,100000"
10984]
10985)
10986start &249
10987end &171
10988sat 32
10989eat 32
10990stc 0
10991st 0
10992sf 1
10993si 0
10994tg (WTG
10995uid 19553,0
10996ps "ConnStartEndStrategy"
10997stg "VerticalLayoutStrategy"
10998f (Text
10999uid 19554,0
11000va (VaSet
11001isHidden 1
11002)
11003xt "82000,101000,84400,102000"
11004st "mosi1"
11005blo "82000,101800"
11006tm "WireNameMgr"
11007)
11008)
11009on &264
11010)
11011]
11012bg "65535,65535,65535"
11013grid (Grid
11014origin "0,0"
11015isVisible 1
11016isActive 1
11017xSpacing 1000
11018xySpacing 1000
11019xShown 1
11020yShown 1
11021color "26368,26368,26368"
11022)
11023packageList *344 (PackageList
11024uid 41,0
11025stg "VerticalLayoutStrategy"
11026textVec [
11027*345 (Text
11028uid 42,0
11029va (VaSet
11030font "arial,8,1"
11031)
11032xt "0,0,5400,1000"
11033st "Package List"
11034blo "0,800"
11035)
11036*346 (MLText
11037uid 43,0
11038va (VaSet
11039)
11040xt "0,1000,16100,9000"
11041st "LIBRARY ieee;
11042USE ieee.std_logic_1164.all;
11043USE ieee.std_logic_arith.all;
11044USE IEEE.NUMERIC_STD.all;
11045USE ieee.std_logic_unsigned.all;
11046
11047LIBRARY FACT_FAD_lib;
11048USE FACT_FAD_lib.fad_definitions.all;"
11049tm "PackageList"
11050)
11051]
11052)
11053compDirBlock (MlTextGroup
11054uid 44,0
11055stg "VerticalLayoutStrategy"
11056textVec [
11057*347 (Text
11058uid 45,0
11059va (VaSet
11060isHidden 1
11061font "Arial,8,1"
11062)
11063xt "20000,0,28100,1000"
11064st "Compiler Directives"
11065blo "20000,800"
11066)
11067*348 (Text
11068uid 46,0
11069va (VaSet
11070isHidden 1
11071font "Arial,8,1"
11072)
11073xt "20000,1000,29600,2000"
11074st "Pre-module directives:"
11075blo "20000,1800"
11076)
11077*349 (MLText
11078uid 47,0
11079va (VaSet
11080isHidden 1
11081)
11082xt "20000,2000,28200,4000"
11083st "`resetall
11084`timescale 1ns/10ps"
11085tm "BdCompilerDirectivesTextMgr"
11086)
11087*350 (Text
11088uid 48,0
11089va (VaSet
11090isHidden 1
11091font "Arial,8,1"
11092)
11093xt "20000,4000,30100,5000"
11094st "Post-module directives:"
11095blo "20000,4800"
11096)
11097*351 (MLText
11098uid 49,0
11099va (VaSet
11100isHidden 1
11101)
11102xt "20000,0,20000,0"
11103tm "BdCompilerDirectivesTextMgr"
11104)
11105*352 (Text
11106uid 50,0
11107va (VaSet
11108isHidden 1
11109font "Arial,8,1"
11110)
11111xt "20000,5000,29900,6000"
11112st "End-module directives:"
11113blo "20000,5800"
11114)
11115*353 (MLText
11116uid 51,0
11117va (VaSet
11118isHidden 1
11119)
11120xt "20000,6000,20000,6000"
11121tm "BdCompilerDirectivesTextMgr"
11122)
11123]
11124associable 1
11125)
11126windowSize "0,22,1681,1050"
11127viewArea "49100,50668,141206,106486"
11128cachedDiagramExtent "-23000,0,477000,153000"
11129pageSetupInfo (PageSetupInfo
11130ptrCmd ""
11131toPrinter 1
11132exportedDirectories [
11133"$HDS_PROJECT_DIR/HTMLExport"
11134]
11135exportStdIncludeRefs 1
11136exportStdPackageRefs 1
11137)
11138hasePageBreakOrigin 1
11139pageBreakOrigin "-73000,0"
11140lastUid 20072,0
11141defaultCommentText (CommentText
11142shape (Rectangle
11143layer 0
11144va (VaSet
11145vasetType 1
11146fg "65280,65280,46080"
11147lineColor "0,0,32768"
11148)
11149xt "0,0,15000,5000"
11150)
11151text (MLText
11152va (VaSet
11153fg "0,0,32768"
11154)
11155xt "200,200,2400,1200"
11156st "
11157Text
11158"
11159tm "CommentText"
11160wrapOption 3
11161visibleHeight 4600
11162visibleWidth 14600
11163)
11164)
11165defaultPanel (Panel
11166shape (RectFrame
11167va (VaSet
11168vasetType 1
11169fg "65535,65535,65535"
11170lineColor "32768,0,0"
11171lineWidth 2
11172)
11173xt "0,0,20000,20000"
11174)
11175title (TextAssociate
11176ps "TopLeftStrategy"
11177text (Text
11178va (VaSet
11179font "Arial,8,1"
11180)
11181xt "1000,1000,3800,2000"
11182st "Panel0"
11183blo "1000,1800"
11184tm "PanelText"
11185)
11186)
11187)
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11191vasetType 1
11192fg "39936,56832,65280"
11193lineColor "0,0,32768"
11194lineWidth 2
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11196xt "0,0,8000,10000"
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11198ttg (MlTextGroup
11199ps "CenterOffsetStrategy"
11200stg "VerticalLayoutStrategy"
11201textVec [
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11203va (VaSet
11204font "Arial,8,1"
11205)
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11208blo "2200,4300"
11209tm "BdLibraryNameMgr"
11210)
11211*355 (Text
11212va (VaSet
11213font "Arial,8,1"
11214)
11215xt "2200,4500,5600,5500"
11216st "<block>"
11217blo "2200,5300"
11218tm "BlkNameMgr"
11219)
11220*356 (Text
11221va (VaSet
11222font "Arial,8,1"
11223)
11224xt "2200,5500,3200,6500"
11225st "I0"
11226blo "2200,6300"
11227tm "InstanceNameMgr"
11228)
11229]
11230)
11231ga (GenericAssociation
11232ps "EdgeToEdgeStrategy"
11233matrix (Matrix
11234text (MLText
11235va (VaSet
11236font "Courier New,8,0"
11237)
11238xt "2200,13500,2200,13500"
11239)
11240header ""
11241)
11242elements [
11243]
11244)
11245viewicon (ZoomableIcon
11246sl 0
11247va (VaSet
11248vasetType 1
11249fg "49152,49152,49152"
11250)
11251xt "0,0,1500,1500"
11252iconName "UnknownFile.png"
11253iconMaskName "UnknownFile.msk"
11254)
11255viewiconposition 0
11256)
11257defaultMWComponent (MWC
11258shape (Rectangle
11259va (VaSet
11260vasetType 1
11261fg "0,65535,0"
11262lineColor "0,32896,0"
11263lineWidth 2
11264)
11265xt "0,0,8000,10000"
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11267ttg (MlTextGroup
11268ps "CenterOffsetStrategy"
11269stg "VerticalLayoutStrategy"
11270textVec [
11271*357 (Text
11272va (VaSet
11273font "Arial,8,1"
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11277blo "550,4300"
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11279*358 (Text
11280va (VaSet
11281font "Arial,8,1"
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11284st "MWComponent"
11285blo "550,5300"
11286)
11287*359 (Text
11288va (VaSet
11289font "Arial,8,1"
11290)
11291xt "550,5500,1550,6500"
11292st "I0"
11293blo "550,6300"
11294tm "InstanceNameMgr"
11295)
11296]
11297)
11298ga (GenericAssociation
11299ps "EdgeToEdgeStrategy"
11300matrix (Matrix
11301text (MLText
11302va (VaSet
11303font "Courier New,8,0"
11304)
11305xt "-6450,1500,-6450,1500"
11306)
11307header ""
11308)
11309elements [
11310]
11311)
11312portVis (PortSigDisplay
11313)
11314prms (Property
11315pclass "params"
11316pname "params"
11317ptn "String"
11318)
11319visOptions (mwParamsVisibilityOptions
11320)
11321)
11322defaultSaComponent (SaComponent
11323shape (Rectangle
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11325vasetType 1
11326fg "0,65535,0"
11327lineColor "0,32896,0"
11328lineWidth 2
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11330xt "0,0,8000,10000"
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11332ttg (MlTextGroup
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11334stg "VerticalLayoutStrategy"
11335textVec [
11336*360 (Text
11337va (VaSet
11338font "Arial,8,1"
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11340xt "900,3500,3800,4500"
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11342blo "900,4300"
11343tm "BdLibraryNameMgr"
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11345*361 (Text
11346va (VaSet
11347font "Arial,8,1"
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11349xt "900,4500,7100,5500"
11350st "SaComponent"
11351blo "900,5300"
11352tm "CptNameMgr"
11353)
11354*362 (Text
11355va (VaSet
11356font "Arial,8,1"
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11358xt "900,5500,1900,6500"
11359st "I0"
11360blo "900,6300"
11361tm "InstanceNameMgr"
11362)
11363]
11364)
11365ga (GenericAssociation
11366ps "EdgeToEdgeStrategy"
11367matrix (Matrix
11368text (MLText
11369va (VaSet
11370font "Courier New,8,0"
11371)
11372xt "-6100,1500,-6100,1500"
11373)
11374header ""
11375)
11376elements [
11377]
11378)
11379viewicon (ZoomableIcon
11380sl 0
11381va (VaSet
11382vasetType 1
11383fg "49152,49152,49152"
11384)
11385xt "0,0,1500,1500"
11386iconName "UnknownFile.png"
11387iconMaskName "UnknownFile.msk"
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11389viewiconposition 0
11390portVis (PortSigDisplay
11391)
11392archFileType "UNKNOWN"
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11394defaultVhdlComponent (VhdlComponent
11395shape (Rectangle
11396va (VaSet
11397vasetType 1
11398fg "0,65535,0"
11399lineColor "0,32896,0"
11400lineWidth 2
11401)
11402xt "0,0,8000,10000"
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11404ttg (MlTextGroup
11405ps "CenterOffsetStrategy"
11406stg "VerticalLayoutStrategy"
11407textVec [
11408*363 (Text
11409va (VaSet
11410font "Arial,8,1"
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11414blo "500,4300"
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11416*364 (Text
11417va (VaSet
11418font "Arial,8,1"
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11420xt "500,4500,7500,5500"
11421st "VhdlComponent"
11422blo "500,5300"
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11424*365 (Text
11425va (VaSet
11426font "Arial,8,1"
11427)
11428xt "500,5500,1500,6500"
11429st "I0"
11430blo "500,6300"
11431tm "InstanceNameMgr"
11432)
11433]
11434)
11435ga (GenericAssociation
11436ps "EdgeToEdgeStrategy"
11437matrix (Matrix
11438text (MLText
11439va (VaSet
11440font "Courier New,8,0"
11441)
11442xt "-6500,1500,-6500,1500"
11443)
11444header ""
11445)
11446elements [
11447]
11448)
11449portVis (PortSigDisplay
11450)
11451entityPath ""
11452archName ""
11453archPath ""
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11455defaultVerilogComponent (VerilogComponent
11456shape (Rectangle
11457va (VaSet
11458vasetType 1
11459fg "0,65535,0"
11460lineColor "0,32896,0"
11461lineWidth 2
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11463xt "-450,0,8450,10000"
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11465ttg (MlTextGroup
11466ps "CenterOffsetStrategy"
11467stg "VerticalLayoutStrategy"
11468textVec [
11469*366 (Text
11470va (VaSet
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11475blo "50,4300"
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11477*367 (Text
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11479font "Arial,8,1"
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11481xt "50,4500,7950,5500"
11482st "VerilogComponent"
11483blo "50,5300"
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11485*368 (Text
11486va (VaSet
11487font "Arial,8,1"
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11489xt "50,5500,1050,6500"
11490st "I0"
11491blo "50,6300"
11492tm "InstanceNameMgr"
11493)
11494]
11495)
11496ga (GenericAssociation
11497ps "EdgeToEdgeStrategy"
11498matrix (Matrix
11499text (MLText
11500va (VaSet
11501font "Courier New,8,0"
11502)
11503xt "-6950,1500,-6950,1500"
11504)
11505header ""
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11507elements [
11508]
11509)
11510entityPath ""
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11512defaultHdlText (HdlText
11513shape (Rectangle
11514va (VaSet
11515vasetType 1
11516fg "65535,65535,37120"
11517lineColor "0,0,32768"
11518lineWidth 2
11519)
11520xt "0,0,8000,10000"
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11522ttg (MlTextGroup
11523ps "CenterOffsetStrategy"
11524stg "VerticalLayoutStrategy"
11525textVec [
11526*369 (Text
11527va (VaSet
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11530xt "3150,4000,4850,5000"
11531st "eb1"
11532blo "3150,4800"
11533tm "HdlTextNameMgr"
11534)
11535*370 (Text
11536va (VaSet
11537font "Arial,8,1"
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11539xt "3150,5000,3950,6000"
11540st "1"
11541blo "3150,5800"
11542tm "HdlTextNumberMgr"
11543)
11544]
11545)
11546viewicon (ZoomableIcon
11547sl 0
11548va (VaSet
11549vasetType 1
11550fg "49152,49152,49152"
11551)
11552xt "0,0,1500,1500"
11553iconName "UnknownFile.png"
11554iconMaskName "UnknownFile.msk"
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11556viewiconposition 0
11557)
11558defaultEmbeddedText (EmbeddedText
11559commentText (CommentText
11560ps "CenterOffsetStrategy"
11561shape (Rectangle
11562va (VaSet
11563vasetType 1
11564fg "65535,65535,65535"
11565lineColor "0,0,32768"
11566lineWidth 2
11567)
11568xt "0,0,18000,5000"
11569)
11570text (MLText
11571va (VaSet
11572)
11573xt "200,200,2400,1200"
11574st "
11575Text
11576"
11577tm "HdlTextMgr"
11578wrapOption 3
11579visibleHeight 4600
11580visibleWidth 17600
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11582)
11583)
11584defaultGlobalConnector (GlobalConnector
11585shape (Circle
11586va (VaSet
11587vasetType 1
11588fg "65535,65535,0"
11589)
11590xt "-1000,-1000,1000,1000"
11591radius 1000
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11593name (Text
11594va (VaSet
11595font "Arial,8,1"
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11597xt "-500,-500,500,500"
11598st "G"
11599blo "-500,300"
11600)
11601)
11602defaultRipper (Ripper
11603ps "OnConnectorStrategy"
11604shape (Line2D
11605pts [
11606"0,0"
11607"1000,1000"
11608]
11609va (VaSet
11610vasetType 1
11611)
11612xt "0,0,1000,1000"
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11614)
11615defaultBdJunction (BdJunction
11616ps "OnConnectorStrategy"
11617shape (Circle
11618va (VaSet
11619vasetType 1
11620)
11621xt "-400,-400,400,400"
11622radius 400
11623)
11624)
11625defaultPortIoIn (PortIoIn
11626shape (CompositeShape
11627va (VaSet
11628vasetType 1
11629fg "0,0,32768"
11630)
11631optionalChildren [
11632(Pentagon
11633sl 0
11634ro 270
11635xt "-2000,-375,-500,375"
11636)
11637(Line
11638sl 0
11639ro 270
11640xt "-500,0,0,0"
11641pts [
11642"-500,0"
11643"0,0"
11644]
11645)
11646]
11647)
11648stc 0
11649sf 1
11650tg (WTG
11651ps "PortIoTextPlaceStrategy"
11652stg "STSignalDisplayStrategy"
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11654va (VaSet
11655)
11656xt "-1375,-1000,-1375,-1000"
11657ju 2
11658blo "-1375,-1000"
11659tm "WireNameMgr"
11660)
11661)
11662)
11663defaultPortIoOut (PortIoOut
11664shape (CompositeShape
11665va (VaSet
11666vasetType 1
11667fg "0,0,32768"
11668)
11669optionalChildren [
11670(Pentagon
11671sl 0
11672ro 270
11673xt "500,-375,2000,375"
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11675(Line
11676sl 0
11677ro 270
11678xt "0,0,500,0"
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11680"0,0"
11681"500,0"
11682]
11683)
11684]
11685)
11686stc 0
11687sf 1
11688tg (WTG
11689ps "PortIoTextPlaceStrategy"
11690stg "STSignalDisplayStrategy"
11691f (Text
11692va (VaSet
11693)
11694xt "625,-1000,625,-1000"
11695blo "625,-1000"
11696tm "WireNameMgr"
11697)
11698)
11699)
11700defaultPortIoInOut (PortIoInOut
11701shape (CompositeShape
11702va (VaSet
11703vasetType 1
11704fg "0,0,32768"
11705)
11706optionalChildren [
11707(Hexagon
11708sl 0
11709xt "500,-375,2000,375"
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11711(Line
11712sl 0
11713xt "0,0,500,0"
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11715"0,0"
11716"500,0"
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11718)
11719]
11720)
11721stc 0
11722sf 1
11723tg (WTG
11724ps "PortIoTextPlaceStrategy"
11725stg "STSignalDisplayStrategy"
11726f (Text
11727va (VaSet
11728)
11729xt "0,-375,0,-375"
11730blo "0,-375"
11731tm "WireNameMgr"
11732)
11733)
11734)
11735defaultPortIoBuffer (PortIoBuffer
11736shape (CompositeShape
11737va (VaSet
11738vasetType 1
11739fg "65535,65535,65535"
11740lineColor "0,0,32768"
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11742optionalChildren [
11743(Hexagon
11744sl 0
11745xt "500,-375,2000,375"
11746)
11747(Line
11748sl 0
11749xt "0,0,500,0"
11750pts [
11751"0,0"
11752"500,0"
11753]
11754)
11755]
11756)
11757stc 0
11758sf 1
11759tg (WTG
11760ps "PortIoTextPlaceStrategy"
11761stg "STSignalDisplayStrategy"
11762f (Text
11763va (VaSet
11764)
11765xt "0,-375,0,-375"
11766blo "0,-375"
11767tm "WireNameMgr"
11768)
11769)
11770)
11771defaultSignal (Wire
11772shape (OrthoPolyLine
11773va (VaSet
11774vasetType 3
11775)
11776pts [
11777"0,0"
11778"0,0"
11779]
11780)
11781ss 0
11782es 0
11783sat 32
11784eat 32
11785st 0
11786sf 1
11787si 0
11788tg (WTG
11789ps "ConnStartEndStrategy"
11790stg "STSignalDisplayStrategy"
11791f (Text
11792va (VaSet
11793)
11794xt "0,0,1900,1000"
11795st "sig0"
11796blo "0,800"
11797tm "WireNameMgr"
11798)
11799)
11800)
11801defaultBus (Wire
11802shape (OrthoPolyLine
11803va (VaSet
11804vasetType 3
11805lineWidth 2
11806)
11807pts [
11808"0,0"
11809"0,0"
11810]
11811)
11812ss 0
11813es 0
11814sat 32
11815eat 32
11816sty 1
11817st 0
11818sf 1
11819si 0
11820tg (WTG
11821ps "ConnStartEndStrategy"
11822stg "STSignalDisplayStrategy"
11823f (Text
11824va (VaSet
11825)
11826xt "0,0,2400,1000"
11827st "dbus0"
11828blo "0,800"
11829tm "WireNameMgr"
11830)
11831)
11832)
11833defaultBundle (Bundle
11834shape (OrthoPolyLine
11835va (VaSet
11836vasetType 3
11837lineColor "32768,0,0"
11838lineWidth 2
11839)
11840pts [
11841"0,0"
11842"0,0"
11843]
11844)
11845ss 0
11846es 0
11847sat 32
11848eat 32
11849textGroup (BiTextGroup
11850ps "ConnStartEndStrategy"
11851stg "VerticalLayoutStrategy"
11852first (Text
11853va (VaSet
11854)
11855xt "0,0,3000,1000"
11856st "bundle0"
11857blo "0,800"
11858tm "BundleNameMgr"
11859)
11860second (MLText
11861va (VaSet
11862)
11863xt "0,1000,1000,2000"
11864st "()"
11865tm "BundleContentsMgr"
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11867)
11868bundleNet &0
11869)
11870defaultPortMapFrame (PortMapFrame
11871ps "PortMapFrameStrategy"
11872shape (RectFrame
11873va (VaSet
11874vasetType 1
11875fg "65535,65535,65535"
11876lineColor "0,0,32768"
11877lineWidth 2
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11879xt "0,0,10000,12000"
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11881portMapText (BiTextGroup
11882ps "BottomRightOffsetStrategy"
11883stg "VerticalLayoutStrategy"
11884first (MLText
11885va (VaSet
11886)
11887)
11888second (MLText
11889va (VaSet
11890)
11891tm "PortMapTextMgr"
11892)
11893)
11894)
11895defaultGenFrame (Frame
11896shape (RectFrame
11897va (VaSet
11898vasetType 1
11899fg "65535,65535,65535"
11900lineColor "26368,26368,26368"
11901lineStyle 2
11902lineWidth 2
11903)
11904xt "0,0,20000,20000"
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11906title (TextAssociate
11907ps "TopLeftStrategy"
11908text (MLText
11909va (VaSet
11910)
11911xt "0,-1100,12900,-100"
11912st "g0: FOR i IN 0 TO n GENERATE"
11913tm "FrameTitleTextMgr"
11914)
11915)
11916seqNum (FrameSequenceNumber
11917ps "TopLeftStrategy"
11918shape (Rectangle
11919va (VaSet
11920vasetType 1
11921fg "65535,65535,65535"
11922)
11923xt "50,50,1250,1450"
11924)
11925num (Text
11926va (VaSet
11927)
11928xt "250,250,1050,1250"
11929st "1"
11930blo "250,1050"
11931tm "FrameSeqNumMgr"
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11933)
11934decls (MlTextGroup
11935ps "BottomRightOffsetStrategy"
11936stg "VerticalLayoutStrategy"
11937textVec [
11938*371 (Text
11939va (VaSet
11940font "Arial,8,1"
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11942xt "14100,20000,22000,21000"
11943st "Frame Declarations"
11944blo "14100,20800"
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11946*372 (MLText
11947va (VaSet
11948)
11949xt "14100,21000,14100,21000"
11950tm "BdFrameDeclTextMgr"
11951)
11952]
11953)
11954)
11955defaultBlockFrame (Frame
11956shape (RectFrame
11957va (VaSet
11958vasetType 1
11959fg "65535,65535,65535"
11960lineColor "26368,26368,26368"
11961lineStyle 1
11962lineWidth 2
11963)
11964xt "0,0,20000,20000"
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11966title (TextAssociate
11967ps "TopLeftStrategy"
11968text (MLText
11969va (VaSet
11970)
11971xt "0,-1100,7700,-100"
11972st "b0: BLOCK (guard)"
11973tm "FrameTitleTextMgr"
11974)
11975)
11976seqNum (FrameSequenceNumber
11977ps "TopLeftStrategy"
11978shape (Rectangle
11979va (VaSet
11980vasetType 1
11981fg "65535,65535,65535"
11982)
11983xt "50,50,1250,1450"
11984)
11985num (Text
11986va (VaSet
11987)
11988xt "250,250,1050,1250"
11989st "1"
11990blo "250,1050"
11991tm "FrameSeqNumMgr"
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11993)
11994decls (MlTextGroup
11995ps "BottomRightOffsetStrategy"
11996stg "VerticalLayoutStrategy"
11997textVec [
11998*373 (Text
11999va (VaSet
12000font "Arial,8,1"
12001)
12002xt "14100,20000,22000,21000"
12003st "Frame Declarations"
12004blo "14100,20800"
12005)
12006*374 (MLText
12007va (VaSet
12008)
12009xt "14100,21000,14100,21000"
12010tm "BdFrameDeclTextMgr"
12011)
12012]
12013)
12014style 3
12015)
12016defaultSaCptPort (CptPort
12017ps "OnEdgeStrategy"
12018shape (Triangle
12019ro 90
12020va (VaSet
12021vasetType 1
12022fg "0,65535,0"
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12024xt "0,0,750,750"
12025)
12026tg (CPTG
12027ps "CptPortTextPlaceStrategy"
12028stg "VerticalLayoutStrategy"
12029f (Text
12030va (VaSet
12031)
12032xt "0,750,1800,1750"
12033st "Port"
12034blo "0,1550"
12035)
12036)
12037thePort (LogicalPort
12038decl (Decl
12039n "Port"
12040t ""
12041o 0
12042)
12043)
12044)
12045defaultSaCptPortBuffer (CptPort
12046ps "OnEdgeStrategy"
12047shape (Diamond
12048va (VaSet
12049vasetType 1
12050fg "65535,65535,65535"
12051)
12052xt "0,0,750,750"
12053)
12054tg (CPTG
12055ps "CptPortTextPlaceStrategy"
12056stg "VerticalLayoutStrategy"
12057f (Text
12058va (VaSet
12059)
12060xt "0,750,1800,1750"
12061st "Port"
12062blo "0,1550"
12063)
12064)
12065thePort (LogicalPort
12066m 3
12067decl (Decl
12068n "Port"
12069t ""
12070o 0
12071)
12072)
12073)
12074defaultDeclText (MLText
12075va (VaSet
12076font "Courier New,8,0"
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12078)
12079archDeclarativeBlock (BdArchDeclBlock
12080uid 1,0
12081stg "BdArchDeclBlockLS"
12082declLabel (Text
12083uid 2,0
12084va (VaSet
12085font "Arial,8,1"
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12087xt "37000,1800,42400,2800"
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12089blo "37000,2600"
12090)
12091portLabel (Text
12092uid 3,0
12093va (VaSet
12094font "Arial,8,1"
12095)
12096xt "37000,2800,39700,3800"
12097st "Ports:"
12098blo "37000,3600"
12099)
12100preUserLabel (Text
12101uid 4,0
12102va (VaSet
12103isHidden 1
12104font "Arial,8,1"
12105)
12106xt "37000,1800,40800,2800"
12107st "Pre User:"
12108blo "37000,2600"
12109)
12110preUserText (MLText
12111uid 5,0
12112va (VaSet
12113isHidden 1
12114font "Courier New,8,0"
12115)
12116xt "37000,1800,37000,1800"
12117tm "BdDeclarativeTextMgr"
12118)
12119diagSignalLabel (Text
12120uid 6,0
12121va (VaSet
12122font "Arial,8,1"
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12124xt "37000,45400,44100,46400"
12125st "Diagram Signals:"
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12127)
12128postUserLabel (Text
12129uid 7,0
12130va (VaSet
12131isHidden 1
12132font "Arial,8,1"
12133)
12134xt "37000,1800,41700,2800"
12135st "Post User:"
12136blo "37000,2600"
12137)
12138postUserText (MLText
12139uid 8,0
12140va (VaSet
12141isHidden 1
12142font "Courier New,8,0"
12143)
12144xt "37000,1800,37000,1800"
12145tm "BdDeclarativeTextMgr"
12146)
12147)
12148commonDM (CommonDM
12149ldm (LogicalDM
12150suid 248,0
12151usingSuid 1
12152emptyRow *375 (LEmptyRow
12153)
12154uid 54,0
12155optionalChildren [
12156*376 (RefLabelRowHdr
12157)
12158*377 (TitleRowHdr
12159)
12160*378 (FilterRowHdr
12161)
12162*379 (RefLabelColHdr
12163tm "RefLabelColHdrMgr"
12164)
12165*380 (RowExpandColHdr
12166tm "RowExpandColHdrMgr"
12167)
12168*381 (GroupColHdr
12169tm "GroupColHdrMgr"
12170)
12171*382 (NameColHdr
12172tm "BlockDiagramNameColHdrMgr"
12173)
12174*383 (ModeColHdr
12175tm "BlockDiagramModeColHdrMgr"
12176)
12177*384 (TypeColHdr
12178tm "BlockDiagramTypeColHdrMgr"
12179)
12180*385 (BoundsColHdr
12181tm "BlockDiagramBoundsColHdrMgr"
12182)
12183*386 (InitColHdr
12184tm "BlockDiagramInitColHdrMgr"
12185)
12186*387 (EolColHdr
12187tm "BlockDiagramEolColHdrMgr"
12188)
12189*388 (LeafLogPort
12190port (LogicalPort
12191m 4
12192decl (Decl
12193n "board_id"
12194t "std_logic_vector"
12195b "(3 downto 0)"
12196preAdd 0
12197posAdd 0
12198o 60
12199suid 5,0
12200)
12201)
12202uid 327,0
12203)
12204*389 (LeafLogPort
12205port (LogicalPort
12206m 4
12207decl (Decl
12208n "crate_id"
12209t "std_logic_vector"
12210b "(1 downto 0)"
12211o 62
12212suid 6,0
12213)
12214)
12215uid 329,0
12216)
12217*390 (LeafLogPort
12218port (LogicalPort
12219m 4
12220decl (Decl
12221n "adc_data_array"
12222t "adc_data_array_type"
12223o 57
12224suid 29,0
12225)
12226)
12227uid 1491,0
12228)
12229*391 (LeafLogPort
12230port (LogicalPort
12231m 1
12232decl (Decl
12233n "RSRLOAD"
12234t "std_logic"
12235o 40
12236suid 57,0
12237i "'0'"
12238)
12239)
12240uid 2435,0
12241)
12242*392 (LeafLogPort
12243port (LogicalPort
12244m 1
12245decl (Decl
12246n "DAC_CS"
12247t "std_logic"
12248o 22
12249suid 66,0
12250)
12251)
12252uid 3039,0
12253)
12254*393 (LeafLogPort
12255port (LogicalPort
12256decl (Decl
12257n "X_50M"
12258t "STD_LOGIC"
12259preAdd 0
12260posAdd 0
12261o 17
12262suid 67,0
12263)
12264)
12265uid 3276,0
12266)
12267*394 (LeafLogPort
12268port (LogicalPort
12269decl (Decl
12270n "TRG"
12271t "STD_LOGIC"
12272o 15
12273suid 68,0
12274)
12275)
12276uid 3278,0
12277)
12278*395 (LeafLogPort
12279port (LogicalPort
12280m 1
12281decl (Decl
12282n "A_CLK"
12283t "std_logic_vector"
12284b "(3 downto 0)"
12285o 21
12286suid 71,0
12287)
12288)
12289uid 3280,0
12290)
12291*396 (LeafLogPort
12292port (LogicalPort
12293m 1
12294decl (Decl
12295n "OE_ADC"
12296t "STD_LOGIC"
12297preAdd 0
12298posAdd 0
12299o 32
12300suid 73,0
12301)
12302)
12303uid 3382,0
12304)
12305*397 (LeafLogPort
12306port (LogicalPort
12307decl (Decl
12308n "A_OTR"
12309t "std_logic_vector"
12310b "(3 DOWNTO 0)"
12311o 5
12312suid 74,0
12313)
12314)
12315uid 3384,0
12316)
12317*398 (LeafLogPort
12318port (LogicalPort
12319decl (Decl
12320n "A0_D"
12321t "std_logic_vector"
12322b "(11 DOWNTO 0)"
12323o 1
12324suid 79,0
12325)
12326)
12327uid 3386,0
12328)
12329*399 (LeafLogPort
12330port (LogicalPort
12331decl (Decl
12332n "A1_D"
12333t "std_logic_vector"
12334b "(11 DOWNTO 0)"
12335o 2
12336suid 80,0
12337)
12338)
12339uid 3388,0
12340)
12341*400 (LeafLogPort
12342port (LogicalPort
12343decl (Decl
12344n "A2_D"
12345t "std_logic_vector"
12346b "(11 DOWNTO 0)"
12347o 3
12348suid 81,0
12349)
12350)
12351uid 3390,0
12352)
12353*401 (LeafLogPort
12354port (LogicalPort
12355decl (Decl
12356n "A3_D"
12357t "std_logic_vector"
12358b "(11 DOWNTO 0)"
12359o 4
12360suid 82,0
12361)
12362)
12363uid 3392,0
12364)
12365*402 (LeafLogPort
12366port (LogicalPort
12367decl (Decl
12368n "D0_SROUT"
12369t "std_logic"
12370o 6
12371suid 91,0
12372)
12373)
12374uid 3524,0
12375)
12376*403 (LeafLogPort
12377port (LogicalPort
12378decl (Decl
12379n "D1_SROUT"
12380t "std_logic"
12381o 7
12382suid 92,0
12383)
12384)
12385uid 3526,0
12386)
12387*404 (LeafLogPort
12388port (LogicalPort
12389decl (Decl
12390n "D2_SROUT"
12391t "std_logic"
12392o 8
12393suid 93,0
12394)
12395)
12396uid 3528,0
12397)
12398*405 (LeafLogPort
12399port (LogicalPort
12400decl (Decl
12401n "D3_SROUT"
12402t "std_logic"
12403o 9
12404suid 94,0
12405)
12406)
12407uid 3530,0
12408)
12409*406 (LeafLogPort
12410port (LogicalPort
12411m 1
12412decl (Decl
12413n "D_A"
12414t "std_logic_vector"
12415b "(3 DOWNTO 0)"
12416o 26
12417suid 95,0
12418i "(others => '0')"
12419)
12420)
12421uid 3532,0
12422)
12423*407 (LeafLogPort
12424port (LogicalPort
12425m 1
12426decl (Decl
12427n "DWRITE"
12428t "std_logic"
12429o 25
12430suid 96,0
12431i "'0'"
12432)
12433)
12434uid 3534,0
12435)
12436*408 (LeafLogPort
12437port (LogicalPort
12438m 1
12439decl (Decl
12440n "S_CLK"
12441t "std_logic"
12442o 42
12443suid 105,0
12444)
12445)
12446uid 3654,0
12447)
12448*409 (LeafLogPort
12449port (LogicalPort
12450m 1
12451decl (Decl
12452n "W_A"
12453t "std_logic_vector"
12454b "(9 DOWNTO 0)"
12455o 45
12456suid 106,0
12457)
12458)
12459uid 3656,0
12460)
12461*410 (LeafLogPort
12462port (LogicalPort
12463m 2
12464decl (Decl
12465n "W_D"
12466t "std_logic_vector"
12467b "(15 DOWNTO 0)"
12468o 52
12469suid 107,0
12470)
12471)
12472uid 3658,0
12473)
12474*411 (LeafLogPort
12475port (LogicalPort
12476m 1
12477decl (Decl
12478n "W_RES"
12479t "std_logic"
12480o 48
12481suid 108,0
12482i "'1'"
12483)
12484)
12485uid 3660,0
12486)
12487*412 (LeafLogPort
12488port (LogicalPort
12489m 1
12490decl (Decl
12491n "W_RD"
12492t "std_logic"
12493o 47
12494suid 109,0
12495i "'1'"
12496)
12497)
12498uid 3662,0
12499)
12500*413 (LeafLogPort
12501port (LogicalPort
12502m 1
12503decl (Decl
12504n "W_WR"
12505t "std_logic"
12506o 50
12507suid 110,0
12508i "'1'"
12509)
12510)
12511uid 3664,0
12512)
12513*414 (LeafLogPort
12514port (LogicalPort
12515decl (Decl
12516n "W_INT"
12517t "std_logic"
12518o 16
12519suid 111,0
12520)
12521)
12522uid 3666,0
12523)
12524*415 (LeafLogPort
12525port (LogicalPort
12526m 1
12527decl (Decl
12528n "W_CS"
12529t "std_logic"
12530o 46
12531suid 112,0
12532i "'1'"
12533)
12534)
12535uid 3668,0
12536)
12537*416 (LeafLogPort
12538port (LogicalPort
12539m 1
12540decl (Decl
12541n "MOSI"
12542t "std_logic"
12543o 31
12544suid 113,0
12545i "'0'"
12546)
12547)
12548uid 3696,0
12549)
12550*417 (LeafLogPort
12551port (LogicalPort
12552m 2
12553decl (Decl
12554n "MISO"
12555t "std_logic"
12556preAdd 0
12557posAdd 0
12558o 51
12559suid 114,0
12560)
12561)
12562uid 3698,0
12563)
12564*418 (LeafLogPort
12565port (LogicalPort
12566m 1
12567decl (Decl
12568n "RS485_C_RE"
12569t "std_logic"
12570o 36
12571suid 127,0
12572)
12573)
12574uid 3888,0
12575)
12576*419 (LeafLogPort
12577port (LogicalPort
12578m 1
12579decl (Decl
12580n "RS485_C_DE"
12581t "std_logic"
12582o 34
12583suid 128,0
12584)
12585)
12586uid 3890,0
12587)
12588*420 (LeafLogPort
12589port (LogicalPort
12590m 1
12591decl (Decl
12592n "RS485_E_RE"
12593t "std_logic"
12594o 39
12595suid 129,0
12596)
12597)
12598uid 3892,0
12599)
12600*421 (LeafLogPort
12601port (LogicalPort
12602m 1
12603decl (Decl
12604n "RS485_E_DE"
12605t "std_logic"
12606o 37
12607suid 130,0
12608)
12609)
12610uid 3894,0
12611)
12612*422 (LeafLogPort
12613port (LogicalPort
12614m 1
12615decl (Decl
12616n "DENABLE"
12617t "std_logic"
12618o 23
12619suid 131,0
12620i "'0'"
12621)
12622)
12623uid 3896,0
12624)
12625*423 (LeafLogPort
12626port (LogicalPort
12627m 1
12628decl (Decl
12629n "EE_CS"
12630t "std_logic"
12631o 29
12632suid 133,0
12633)
12634)
12635uid 3900,0
12636)
12637*424 (LeafLogPort
12638port (LogicalPort
12639m 1
12640decl (Decl
12641n "D_T"
12642t "std_logic_vector"
12643b "(7 DOWNTO 0)"
12644o 27
12645suid 141,0
12646i "(OTHERS => '0')"
12647)
12648)
12649uid 5322,0
12650)
12651*425 (LeafLogPort
12652port (LogicalPort
12653m 1
12654decl (Decl
12655n "D_T2"
12656t "std_logic_vector"
12657b "(1 DOWNTO 0)"
12658o 28
12659suid 154,0
12660i "(others => '0')"
12661)
12662)
12663uid 6872,0
12664scheme 0
12665)
12666*426 (LeafLogPort
12667port (LogicalPort
12668m 1
12669decl (Decl
12670n "A1_T"
12671t "std_logic_vector"
12672b "(7 DOWNTO 0)"
12673o 19
12674suid 155,0
12675i "(OTHERS => '0')"
12676)
12677)
12678uid 7134,0
12679scheme 0
12680)
12681*427 (LeafLogPort
12682port (LogicalPort
12683m 4
12684decl (Decl
12685n "CLK_50"
12686t "std_logic"
12687o 54
12688suid 163,0
12689)
12690)
12691uid 9516,0
12692)
12693*428 (LeafLogPort
12694port (LogicalPort
12695m 1
12696decl (Decl
12697n "A0_T"
12698t "std_logic_vector"
12699b "(7 DOWNTO 0)"
12700o 18
12701suid 166,0
12702i "(others => '0')"
12703)
12704)
12705uid 10294,0
12706scheme 0
12707)
12708*429 (LeafLogPort
12709port (LogicalPort
12710m 1
12711decl (Decl
12712n "RS485_C_DO"
12713t "std_logic"
12714o 35
12715suid 198,0
12716)
12717)
12718uid 11086,0
12719scheme 0
12720)
12721*430 (LeafLogPort
12722port (LogicalPort
12723decl (Decl
12724n "RS485_E_DI"
12725t "std_logic"
12726o 14
12727suid 200,0
12728)
12729)
12730uid 11504,0
12731scheme 0
12732)
12733*431 (LeafLogPort
12734port (LogicalPort
12735m 1
12736decl (Decl
12737n "RS485_E_DO"
12738t "std_logic"
12739o 38
12740suid 201,0
12741)
12742)
12743uid 11506,0
12744scheme 0
12745)
12746*432 (LeafLogPort
12747port (LogicalPort
12748m 1
12749decl (Decl
12750n "SRIN"
12751t "std_logic"
12752o 41
12753suid 203,0
12754i "'0'"
12755)
12756)
12757uid 12336,0
12758)
12759*433 (LeafLogPort
12760port (LogicalPort
12761m 1
12762decl (Decl
12763n "AMBER_LED"
12764t "std_logic"
12765o 20
12766suid 207,0
12767)
12768)
12769uid 12768,0
12770)
12771*434 (LeafLogPort
12772port (LogicalPort
12773m 1
12774decl (Decl
12775n "GREEN_LED"
12776t "std_logic"
12777o 30
12778suid 208,0
12779)
12780)
12781uid 12770,0
12782)
12783*435 (LeafLogPort
12784port (LogicalPort
12785m 1
12786decl (Decl
12787n "RED_LED"
12788t "std_logic"
12789o 33
12790suid 209,0
12791)
12792)
12793uid 12772,0
12794)
12795*436 (LeafLogPort
12796port (LogicalPort
12797decl (Decl
12798n "LINE"
12799t "std_logic_vector"
12800b "( 5 DOWNTO 0 )"
12801o 12
12802suid 210,0
12803)
12804)
12805uid 13514,0
12806scheme 0
12807)
12808*437 (LeafLogPort
12809port (LogicalPort
12810decl (Decl
12811n "REFCLK"
12812t "std_logic"
12813o 13
12814suid 211,0
12815)
12816)
12817uid 13626,0
12818scheme 0
12819)
12820*438 (LeafLogPort
12821port (LogicalPort
12822decl (Decl
12823n "D_T_in"
12824t "std_logic_vector"
12825b "(1 DOWNTO 0)"
12826o 11
12827suid 213,0
12828)
12829)
12830uid 14320,0
12831scheme 0
12832)
12833*439 (LeafLogPort
12834port (LogicalPort
12835m 4
12836decl (Decl
12837n "led"
12838t "std_logic_vector"
12839b "(7 DOWNTO 0)"
12840posAdd 0
12841o 65
12842suid 215,0
12843i "(OTHERS => '0')"
12844)
12845)
12846uid 15181,0
12847)
12848*440 (LeafLogPort
12849port (LogicalPort
12850decl (Decl
12851n "D_PLLLCK"
12852t "std_logic_vector"
12853b "(3 DOWNTO 0)"
12854o 10
12855suid 216,0
12856)
12857)
12858uid 15704,0
12859scheme 0
12860)
12861*441 (LeafLogPort
12862port (LogicalPort
12863m 1
12864decl (Decl
12865n "TCS"
12866t "std_logic_vector"
12867b "(3 DOWNTO 0)"
12868o 43
12869suid 217,0
12870)
12871)
12872uid 15843,0
12873scheme 0
12874)
12875*442 (LeafLogPort
12876port (LogicalPort
12877m 1
12878decl (Decl
12879n "DSRCLK"
12880t "std_logic_vector"
12881b "(3 DOWNTO 0)"
12882o 24
12883suid 222,0
12884i "(others => '0')"
12885)
12886)
12887uid 16055,0
12888scheme 0
12889)
12890*443 (LeafLogPort
12891port (LogicalPort
12892m 4
12893decl (Decl
12894n "SRCLK"
12895t "std_logic"
12896o 56
12897suid 225,0
12898i "'0'"
12899)
12900)
12901uid 16253,0
12902)
12903*444 (LeafLogPort
12904port (LogicalPort
12905m 4
12906decl (Decl
12907n "alarm_refclk_too_high"
12908t "std_logic"
12909o 58
12910suid 226,0
12911i "'0'"
12912)
12913)
12914uid 16582,0
12915)
12916*445 (LeafLogPort
12917port (LogicalPort
12918m 4
12919decl (Decl
12920n "alarm_refclk_too_low"
12921t "std_logic"
12922o 59
12923suid 227,0
12924i "'0'"
12925)
12926)
12927uid 16584,0
12928)
12929*446 (LeafLogPort
12930port (LogicalPort
12931m 4
12932decl (Decl
12933n "counter_result"
12934t "std_logic_vector"
12935b "(11 downto 0)"
12936o 61
12937suid 230,0
12938i "(others => '0')"
12939)
12940)
12941uid 16586,0
12942)
12943*447 (LeafLogPort
12944port (LogicalPort
12945lang 2
12946m 4
12947decl (Decl
12948n "ADC_CLK"
12949t "std_logic"
12950o 53
12951suid 231,0
12952)
12953)
12954uid 17310,0
12955)
12956*448 (LeafLogPort
12957port (LogicalPort
12958lang 2
12959m 1
12960decl (Decl
12961n "TRG_V"
12962t "std_logic"
12963o 44
12964suid 232,0
12965i "'0'"
12966)
12967)
12968uid 17399,0
12969scheme 0
12970)
12971*449 (LeafLogPort
12972port (LogicalPort
12973m 4
12974decl (Decl
12975n "w5300_state"
12976t "std_logic_vector"
12977b "(7 DOWNTO 0)"
12978eolc "-- state is encoded here ... useful for debugging."
12979posAdd 0
12980o 68
12981suid 233,0
12982)
12983)
12984uid 17854,0
12985)
12986*450 (LeafLogPort
12987port (LogicalPort
12988m 4
12989decl (Decl
12990n "debug_data_ram_empty"
12991t "std_logic"
12992o 63
12993suid 234,0
12994)
12995)
12996uid 18082,0
12997)
12998*451 (LeafLogPort
12999port (LogicalPort
13000m 4
13001decl (Decl
13002n "debug_data_valid"
13003t "std_logic"
13004o 64
13005suid 235,0
13006)
13007)
13008uid 18084,0
13009)
13010*452 (LeafLogPort
13011port (LogicalPort
13012lang 2
13013m 4
13014decl (Decl
13015n "mem_manager_state"
13016t "std_logic_vector"
13017b "(3 DOWNTO 0)"
13018eolc "-- state is encoded here ... useful for debugging."
13019posAdd 0
13020o 66
13021suid 237,0
13022)
13023)
13024uid 18213,0
13025)
13026*453 (LeafLogPort
13027port (LogicalPort
13028m 4
13029decl (Decl
13030n "DG_state"
13031t "std_logic_vector"
13032b "(7 downto 0)"
13033prec "-- for debugging"
13034preAdd 0
13035o 55
13036suid 238,0
13037)
13038)
13039uid 18334,0
13040)
13041*454 (LeafLogPort
13042port (LogicalPort
13043m 4
13044decl (Decl
13045n "socket_tx_free_out"
13046t "std_logic_vector"
13047b "(16 DOWNTO 0)"
13048eolc "-- 17bit value .. that's true"
13049posAdd 0
13050o 67
13051suid 239,0
13052)
13053)
13054uid 18483,0
13055)
13056*455 (LeafLogPort
13057port (LogicalPort
13058m 1
13059decl (Decl
13060n "W_T"
13061t "std_logic_vector"
13062b "( 3 DOWNTO 0 )"
13063o 49
13064suid 240,0
13065i "(others => '0')"
13066)
13067)
13068uid 18800,0
13069scheme 0
13070)
13071*456 (LeafLogPort
13072port (LogicalPort
13073m 4
13074decl (Decl
13075n "dac_cs1"
13076t "std_logic"
13077o 69
13078suid 241,0
13079)
13080)
13081uid 19557,0
13082)
13083*457 (LeafLogPort
13084port (LogicalPort
13085m 4
13086decl (Decl
13087n "sensor_cs"
13088t "std_logic_vector"
13089b "(3 DOWNTO 0)"
13090o 70
13091suid 242,0
13092)
13093)
13094uid 19559,0
13095)
13096*458 (LeafLogPort
13097port (LogicalPort
13098m 4
13099decl (Decl
13100n "sclk"
13101t "std_logic"
13102o 71
13103suid 243,0
13104)
13105)
13106uid 19561,0
13107)
13108*459 (LeafLogPort
13109port (LogicalPort
13110m 4
13111decl (Decl
13112n "mosi1"
13113t "std_logic"
13114o 72
13115suid 245,0
13116)
13117)
13118uid 19563,0
13119)
13120]
13121)
13122pdm (PhysicalDM
13123displayShortBounds 1
13124editShortBounds 1
13125uid 67,0
13126optionalChildren [
13127*460 (Sheet
13128sheetRow (SheetRow
13129headerVa (MVa
13130cellColor "49152,49152,49152"
13131fontColor "0,0,0"
13132font "Tahoma,10,0"
13133)
13134cellVa (MVa
13135cellColor "65535,65535,65535"
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13137font "Tahoma,10,0"
13138)
13139groupVa (MVa
13140cellColor "39936,56832,65280"
13141fontColor "0,0,0"
13142font "Tahoma,10,0"
13143)
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13147dimension 20
13148)
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13153pos 0
13154dimension 20
13155uid 70,0
13156)
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13161uid 71,0
13162)
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13173dimension 20
13174uid 328,0
13175)
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13179dimension 20
13180uid 330,0
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13185dimension 20
13186uid 1492,0
13187)
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13190pos 0
13191dimension 20
13192uid 2436,0
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13196pos 1
13197dimension 20
13198uid 3040,0
13199)
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13202pos 2
13203dimension 20
13204uid 3277,0
13205)
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13208pos 3
13209dimension 20
13210uid 3279,0
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13214pos 4
13215dimension 20
13216uid 3281,0
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13220pos 5
13221dimension 20
13222uid 3383,0
13223)
13224*474 (MRCItem
13225litem &397
13226pos 6
13227dimension 20
13228uid 3385,0
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13230*475 (MRCItem
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13232pos 7
13233dimension 20
13234uid 3387,0
13235)
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13238pos 8
13239dimension 20
13240uid 3389,0
13241)
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13243litem &400
13244pos 9
13245dimension 20
13246uid 3391,0
13247)
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13249litem &401
13250pos 10
13251dimension 20
13252uid 3393,0
13253)
13254*479 (MRCItem
13255litem &402
13256pos 11
13257dimension 20
13258uid 3525,0
13259)
13260*480 (MRCItem
13261litem &403
13262pos 12
13263dimension 20
13264uid 3527,0
13265)
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13268pos 13
13269dimension 20
13270uid 3529,0
13271)
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13274pos 14
13275dimension 20
13276uid 3531,0
13277)
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13280pos 15
13281dimension 20
13282uid 3533,0
13283)
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13286pos 16
13287dimension 20
13288uid 3535,0
13289)
13290*485 (MRCItem
13291litem &408
13292pos 17
13293dimension 20
13294uid 3655,0
13295)
13296*486 (MRCItem
13297litem &409
13298pos 18
13299dimension 20
13300uid 3657,0
13301)
13302*487 (MRCItem
13303litem &410
13304pos 19
13305dimension 20
13306uid 3659,0
13307)
13308*488 (MRCItem
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13310pos 20
13311dimension 20
13312uid 3661,0
13313)
13314*489 (MRCItem
13315litem &412
13316pos 21
13317dimension 20
13318uid 3663,0
13319)
13320*490 (MRCItem
13321litem &413
13322pos 22
13323dimension 20
13324uid 3665,0
13325)
13326*491 (MRCItem
13327litem &414
13328pos 23
13329dimension 20
13330uid 3667,0
13331)
13332*492 (MRCItem
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13334pos 24
13335dimension 20
13336uid 3669,0
13337)
13338*493 (MRCItem
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13340pos 25
13341dimension 20
13342uid 3697,0
13343)
13344*494 (MRCItem
13345litem &417
13346pos 26
13347dimension 20
13348uid 3699,0
13349)
13350*495 (MRCItem
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13352pos 27
13353dimension 20
13354uid 3889,0
13355)
13356*496 (MRCItem
13357litem &419
13358pos 28
13359dimension 20
13360uid 3891,0
13361)
13362*497 (MRCItem
13363litem &420
13364pos 29
13365dimension 20
13366uid 3893,0
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13370pos 30
13371dimension 20
13372uid 3895,0
13373)
13374*499 (MRCItem
13375litem &422
13376pos 31
13377dimension 20
13378uid 3897,0
13379)
13380*500 (MRCItem
13381litem &423
13382pos 32
13383dimension 20
13384uid 3901,0
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13386*501 (MRCItem
13387litem &424
13388pos 33
13389dimension 20
13390uid 5323,0
13391)
13392*502 (MRCItem
13393litem &425
13394pos 34
13395dimension 20
13396uid 6873,0
13397)
13398*503 (MRCItem
13399litem &426
13400pos 35
13401dimension 20
13402uid 7135,0
13403)
13404*504 (MRCItem
13405litem &427
13406pos 55
13407dimension 20
13408uid 9517,0
13409)
13410*505 (MRCItem
13411litem &428
13412pos 36
13413dimension 20
13414uid 10295,0
13415)
13416*506 (MRCItem
13417litem &429
13418pos 37
13419dimension 20
13420uid 11087,0
13421)
13422*507 (MRCItem
13423litem &430
13424pos 38
13425dimension 20
13426uid 11505,0
13427)
13428*508 (MRCItem
13429litem &431
13430pos 39
13431dimension 20
13432uid 11507,0
13433)
13434*509 (MRCItem
13435litem &432
13436pos 40
13437dimension 20
13438uid 12337,0
13439)
13440*510 (MRCItem
13441litem &433
13442pos 41
13443dimension 20
13444uid 12769,0
13445)
13446*511 (MRCItem
13447litem &434
13448pos 42
13449dimension 20
13450uid 12771,0
13451)
13452*512 (MRCItem
13453litem &435
13454pos 43
13455dimension 20
13456uid 12773,0
13457)
13458*513 (MRCItem
13459litem &436
13460pos 44
13461dimension 20
13462uid 13515,0
13463)
13464*514 (MRCItem
13465litem &437
13466pos 45
13467dimension 20
13468uid 13627,0
13469)
13470*515 (MRCItem
13471litem &438
13472pos 46
13473dimension 20
13474uid 14321,0
13475)
13476*516 (MRCItem
13477litem &439
13478pos 56
13479dimension 20
13480uid 15182,0
13481)
13482*517 (MRCItem
13483litem &440
13484pos 47
13485dimension 20
13486uid 15705,0
13487)
13488*518 (MRCItem
13489litem &441
13490pos 48
13491dimension 20
13492uid 15844,0
13493)
13494*519 (MRCItem
13495litem &442
13496pos 49
13497dimension 20
13498uid 16056,0
13499)
13500*520 (MRCItem
13501litem &443
13502pos 57
13503dimension 20
13504uid 16254,0
13505)
13506*521 (MRCItem
13507litem &444
13508pos 58
13509dimension 20
13510uid 16583,0
13511)
13512*522 (MRCItem
13513litem &445
13514pos 59
13515dimension 20
13516uid 16585,0
13517)
13518*523 (MRCItem
13519litem &446
13520pos 60
13521dimension 20
13522uid 16587,0
13523)
13524*524 (MRCItem
13525litem &447
13526pos 61
13527dimension 20
13528uid 17311,0
13529)
13530*525 (MRCItem
13531litem &448
13532pos 50
13533dimension 20
13534uid 17400,0
13535)
13536*526 (MRCItem
13537litem &449
13538pos 62
13539dimension 20
13540uid 17855,0
13541)
13542*527 (MRCItem
13543litem &450
13544pos 63
13545dimension 20
13546uid 18083,0
13547)
13548*528 (MRCItem
13549litem &451
13550pos 64
13551dimension 20
13552uid 18085,0
13553)
13554*529 (MRCItem
13555litem &452
13556pos 65
13557dimension 20
13558uid 18214,0
13559)
13560*530 (MRCItem
13561litem &453
13562pos 66
13563dimension 20
13564uid 18335,0
13565)
13566*531 (MRCItem
13567litem &454
13568pos 67
13569dimension 20
13570uid 18484,0
13571)
13572*532 (MRCItem
13573litem &455
13574pos 51
13575dimension 20
13576uid 18801,0
13577)
13578*533 (MRCItem
13579litem &456
13580pos 68
13581dimension 20
13582uid 19558,0
13583)
13584*534 (MRCItem
13585litem &457
13586pos 69
13587dimension 20
13588uid 19560,0
13589)
13590*535 (MRCItem
13591litem &458
13592pos 70
13593dimension 20
13594uid 19562,0
13595)
13596*536 (MRCItem
13597litem &459
13598pos 71
13599dimension 20
13600uid 19564,0
13601)
13602]
13603)
13604sheetCol (SheetCol
13605propVa (MVa
13606cellColor "0,49152,49152"
13607fontColor "0,0,0"
13608font "Tahoma,10,0"
13609textAngle 90
13610)
13611uid 73,0
13612optionalChildren [
13613*537 (MRCItem
13614litem &379
13615pos 0
13616dimension 20
13617uid 74,0
13618)
13619*538 (MRCItem
13620litem &381
13621pos 1
13622dimension 50
13623uid 75,0
13624)
13625*539 (MRCItem
13626litem &382
13627pos 2
13628dimension 100
13629uid 76,0
13630)
13631*540 (MRCItem
13632litem &383
13633pos 3
13634dimension 50
13635uid 77,0
13636)
13637*541 (MRCItem
13638litem &384
13639pos 4
13640dimension 100
13641uid 78,0
13642)
13643*542 (MRCItem
13644litem &385
13645pos 5
13646dimension 100
13647uid 79,0
13648)
13649*543 (MRCItem
13650litem &386
13651pos 6
13652dimension 182
13653uid 80,0
13654)
13655*544 (MRCItem
13656litem &387
13657pos 7
13658dimension 80
13659uid 81,0
13660)
13661]
13662)
13663fixedCol 4
13664fixedRow 2
13665name "Ports"
13666uid 68,0
13667vaOverrides [
13668]
13669)
13670]
13671)
13672uid 53,0
13673)
13674genericsCommonDM (CommonDM
13675ldm (LogicalDM
13676emptyRow *545 (LEmptyRow
13677)
13678uid 83,0
13679optionalChildren [
13680*546 (RefLabelRowHdr
13681)
13682*547 (TitleRowHdr
13683)
13684*548 (FilterRowHdr
13685)
13686*549 (RefLabelColHdr
13687tm "RefLabelColHdrMgr"
13688)
13689*550 (RowExpandColHdr
13690tm "RowExpandColHdrMgr"
13691)
13692*551 (GroupColHdr
13693tm "GroupColHdrMgr"
13694)
13695*552 (NameColHdr
13696tm "GenericNameColHdrMgr"
13697)
13698*553 (TypeColHdr
13699tm "GenericTypeColHdrMgr"
13700)
13701*554 (InitColHdr
13702tm "GenericValueColHdrMgr"
13703)
13704*555 (PragmaColHdr
13705tm "GenericPragmaColHdrMgr"
13706)
13707*556 (EolColHdr
13708tm "GenericEolColHdrMgr"
13709)
13710]
13711)
13712pdm (PhysicalDM
13713displayShortBounds 1
13714editShortBounds 1
13715uid 95,0
13716optionalChildren [
13717*557 (Sheet
13718sheetRow (SheetRow
13719headerVa (MVa
13720cellColor "49152,49152,49152"
13721fontColor "0,0,0"
13722font "Tahoma,10,0"
13723)
13724cellVa (MVa
13725cellColor "65535,65535,65535"
13726fontColor "0,0,0"
13727font "Tahoma,10,0"
13728)
13729groupVa (MVa
13730cellColor "39936,56832,65280"
13731fontColor "0,0,0"
13732font "Tahoma,10,0"
13733)
13734emptyMRCItem *558 (MRCItem
13735litem &545
13736pos 0
13737dimension 20
13738)
13739uid 97,0
13740optionalChildren [
13741*559 (MRCItem
13742litem &546
13743pos 0
13744dimension 20
13745uid 98,0
13746)
13747*560 (MRCItem
13748litem &547
13749pos 1
13750dimension 23
13751uid 99,0
13752)
13753*561 (MRCItem
13754litem &548
13755pos 2
13756hidden 1
13757dimension 20
13758uid 100,0
13759)
13760]
13761)
13762sheetCol (SheetCol
13763propVa (MVa
13764cellColor "0,49152,49152"
13765fontColor "0,0,0"
13766font "Tahoma,10,0"
13767textAngle 90
13768)
13769uid 101,0
13770optionalChildren [
13771*562 (MRCItem
13772litem &549
13773pos 0
13774dimension 20
13775uid 102,0
13776)
13777*563 (MRCItem
13778litem &551
13779pos 1
13780dimension 50
13781uid 103,0
13782)
13783*564 (MRCItem
13784litem &552
13785pos 2
13786dimension 100
13787uid 104,0
13788)
13789*565 (MRCItem
13790litem &553
13791pos 3
13792dimension 100
13793uid 105,0
13794)
13795*566 (MRCItem
13796litem &554
13797pos 4
13798dimension 50
13799uid 106,0
13800)
13801*567 (MRCItem
13802litem &555
13803pos 5
13804dimension 50
13805uid 107,0
13806)
13807*568 (MRCItem
13808litem &556
13809pos 6
13810dimension 80
13811uid 108,0
13812)
13813]
13814)
13815fixedCol 3
13816fixedRow 2
13817name "Ports"
13818uid 96,0
13819vaOverrides [
13820]
13821)
13822]
13823)
13824uid 82,0
13825type 1
13826)
13827activeModelName "BlockDiag"
13828)
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