source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.hdlsidedata/dataRM_64b_16b_width14_dataRM_64b_16b_width14_a.vhd.info/Coregen/dataRM_64b_16b_width14.xco @ 9912

Last change on this file since 9912 was 9912, checked in by neise, 10 years ago
most recent version quasi initial commit
File size: 2.2 KB
Line 
1##############################################################
2#
3# Xilinx Core Generator version K.39
4# Date: Mon Jun 21 14:05:42 2010
5#
6##############################################################
7#
8#  This file contains the customisation parameters for a
9#  Xilinx CORE Generator IP GUI. It is strongly recommended
10#  that you do not manually alter this file as it may cause
11#  unexpected and unsupported behavior.
12#
13##############################################################
14#
15# BEGIN Project Options
16SET addpads = False
17SET asysymbol = False
18SET busformat = BusFormatParenNotRipped
19SET createndf = False
20SET designentry = VHDL
21SET device = xc3sd3400a
22SET devicefamily = spartan3adsp
23SET flowvendor = MentorHDL
24SET formalverification = False
25SET foundationsym = False
26SET implementationfiletype = Ngc
27SET package = fg676
28SET removerpms = False
29SET simulationfiles = Behavioral
30SET speedgrade = -4
31SET verilogsim = False
32SET vhdlsim = True
33# END Project Options
34# BEGIN Select
35SELECT Block_Memory_Generator family Xilinx,_Inc. 2.8
36# END Select
37# BEGIN Parameters
38CSET algorithm=Minimum_Area
39CSET assume_synchronous_clk=false
40CSET byte_size=9
41CSET coe_file=no_coe_file_loaded
42CSET collision_warnings=ALL
43CSET component_name=dataRM_64b_16b_width14
44CSET disable_collision_warnings=false
45CSET disable_out_of_range_warnings=false
46CSET ecc=false
47CSET enable_a=Always_Enabled
48CSET enable_b=Always_Enabled
49CSET fill_remaining_memory_locations=false
50CSET load_init_file=false
51CSET memory_type=Simple_Dual_Port_RAM
52CSET operating_mode_a=READ_FIRST
53CSET operating_mode_b=READ_FIRST
54CSET output_reset_value_a=0
55CSET output_reset_value_b=0
56CSET pipeline_stages=0
57CSET primitive=8kx2
58CSET read_width_a=64
59CSET read_width_b=16
60CSET register_porta_output_of_memory_core=false
61CSET register_porta_output_of_memory_primitives=false
62CSET register_portb_output_of_memory_core=false
63CSET register_portb_output_of_memory_primitives=false
64CSET remaining_memory_locations=0
65CSET single_bit_ecc=false
66CSET use_byte_write_enable=false
67CSET use_ramb16bwer_reset_behavior=false
68CSET use_regcea_pin=false
69CSET use_regceb_pin=false
70CSET use_ssra_pin=false
71CSET use_ssrb_pin=false
72CSET write_depth_a=16384
73CSET write_width_a=64
74CSET write_width_b=16
75# END Parameters
76GENERATE
77# CRC: cf33c7a5
78
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