source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/clock_generator_var_ps/struct.bd@ 10121

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uid 409,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 410,0
text (MLText
uid 411,0
va (VaSet
font "Courier New,8,0"
)
xt "24500,13000,24500,13000"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 412,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "17250,16250,18750,17750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*32 (SaComponent
uid 514,0
optionalChildren [
*33 (CptPort
uid 482,0
ps "OnEdgeStrategy"
shape (Triangle
uid 483,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "39250,33625,40000,34375"
)
tg (CPTG
uid 484,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 485,0
va (VaSet
font "arial,8,0"
)
xt "41000,33500,44900,34500"
st "CLKIN_IN"
blo "41000,34300"
)
)
thePort (LogicalPort
decl (Decl
n "CLKIN_IN"
t "std_logic"
o 1
)
)
)
*34 (CptPort
uid 486,0
ps "OnEdgeStrategy"
shape (Triangle
uid 487,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "39250,34625,40000,35375"
)
tg (CPTG
uid 488,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 489,0
va (VaSet
font "arial,8,0"
)
xt "41000,34500,45100,35500"
st "PSCLK_IN"
blo "41000,35300"
)
)
thePort (LogicalPort
decl (Decl
n "PSCLK_IN"
t "std_logic"
o 2
)
)
)
*35 (CptPort
uid 490,0
ps "OnEdgeStrategy"
shape (Triangle
uid 491,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "39250,35625,40000,36375"
)
tg (CPTG
uid 492,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 493,0
va (VaSet
font "arial,8,0"
)
xt "41000,35500,44700,36500"
st "PSEN_IN"
blo "41000,36300"
)
)
thePort (LogicalPort
decl (Decl
n "PSEN_IN"
t "std_logic"
o 3
)
)
)
*36 (CptPort
uid 494,0
ps "OnEdgeStrategy"
shape (Triangle
uid 495,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "39250,36625,40000,37375"
)
tg (CPTG
uid 496,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 497,0
va (VaSet
font "arial,8,0"
)
xt "41000,36500,47100,37500"
st "PSINCDEC_IN"
blo "41000,37300"
)
)
thePort (LogicalPort
decl (Decl
n "PSINCDEC_IN"
t "std_logic"
o 4
)
)
)
*37 (CptPort
uid 502,0
ps "OnEdgeStrategy"
shape (Triangle
uid 503,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "55000,33625,55750,34375"
)
tg (CPTG
uid 504,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 505,0
va (VaSet
font "arial,8,0"
)
xt "49600,33500,54000,34500"
st "CLK0_OUT"
ju 2
blo "54000,34300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "CLK0_OUT"
t "std_logic"
o 6
)
)
)
*38 (CptPort
uid 506,0
ps "OnEdgeStrategy"
shape (Triangle
uid 507,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "55000,34625,55750,35375"
)
tg (CPTG
uid 508,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 509,0
va (VaSet
font "arial,8,0"
)
xt "47900,34500,54000,35500"
st "LOCKED_OUT"
ju 2
blo "54000,35300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "LOCKED_OUT"
t "std_logic"
o 7
)
)
)
*39 (CptPort
uid 510,0
ps "OnEdgeStrategy"
shape (Triangle
uid 511,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "55000,35625,55750,36375"
)
tg (CPTG
uid 512,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 513,0
va (VaSet
font "arial,8,0"
)
xt "47800,35500,54000,36500"
st "PSDONE_OUT"
ju 2
blo "54000,36300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "PSDONE_OUT"
t "std_logic"
o 8
)
)
)
*40 (CptPort
uid 1487,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1488,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "39250,37625,40000,38375"
)
tg (CPTG
uid 1489,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1490,0
va (VaSet
font "arial,8,0"
)
xt "41000,37500,44200,38500"
st "RST_IN"
blo "41000,38300"
)
)
thePort (LogicalPort
decl (Decl
n "RST_IN"
t "std_logic"
o 5
)
)
)
]
shape (Rectangle
uid 515,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "40000,33000,55000,40000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 516,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*41 (Text
uid 517,0
va (VaSet
font "arial,8,1"
)
xt "40800,40000,47000,41000"
st "FACT_FAD_lib"
blo "40800,40800"
tm "BdLibraryNameMgr"
)
*42 (Text
uid 518,0
va (VaSet
font "arial,8,1"
)
xt "40800,41000,48200,42000"
st "dcm_var_ps_38ns"
blo "40800,41800"
tm "CptNameMgr"
)
*43 (Text
uid 519,0
va (VaSet
font "arial,8,1"
)
xt "40800,42000,42600,43000"
st "U_2"
blo "40800,42800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 520,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 521,0
text (MLText
uid 522,0
va (VaSet
font "Courier New,8,0"
)
xt "47500,33000,47500,33000"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 523,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "40250,38250,41750,39750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*44 (Net
uid 524,0
decl (Decl
n "CLK0_OUT"
t "std_logic"
o 14
suid 14,0
)
declText (MLText
uid 525,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,15800,40500,16600"
st "SIGNAL CLK0_OUT        : std_logic
"
)
)
*45 (Net
uid 530,0
decl (Decl
n "PSCLK_IN"
t "std_logic"
o 16
suid 15,0
)
declText (MLText
uid 531,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,17400,40500,18200"
st "SIGNAL PSCLK_IN        : std_logic
"
)
)
*46 (Net
uid 544,0
decl (Decl
n "PSEN_IN"
t "std_logic"
o 18
suid 16,0
)
declText (MLText
uid 545,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,19000,40500,19800"
st "SIGNAL PSEN_IN         : std_logic
"
)
)
*47 (Net
uid 558,0
decl (Decl
n "PSINCDEC_IN"
t "std_logic"
o 19
suid 17,0
)
declText (MLText
uid 559,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,19800,40500,20600"
st "SIGNAL PSINCDEC_IN     : std_logic
"
)
)
*48 (Net
uid 586,0
decl (Decl
n "PSDONE_OUT"
t "std_logic"
o 17
suid 19,0
)
declText (MLText
uid 587,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,18200,40500,19000"
st "SIGNAL PSDONE_OUT      : std_logic
"
)
)
*49 (Net
uid 600,0
decl (Decl
n "LOCKED_OUT"
t "std_logic"
o 15
suid 20,0
)
declText (MLText
uid 601,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,16600,40500,17400"
st "SIGNAL LOCKED_OUT      : std_logic
"
)
)
*50 (SaComponent
uid 826,0
optionalChildren [
*51 (CptPort
uid 767,0
ps "OnEdgeStrategy"
shape (Triangle
uid 768,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "63250,30625,64000,31375"
)
tg (CPTG
uid 769,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 770,0
va (VaSet
)
xt "65000,30500,66900,31500"
st "CLK"
blo "65000,31300"
)
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_logic"
preAdd 0
posAdd 0
o 1
suid 1,0
)
)
)
*52 (CptPort
uid 771,0
ps "OnEdgeStrategy"
shape (Triangle
uid 772,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "90000,39625,90750,40375"
)
tg (CPTG
uid 773,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 774,0
va (VaSet
)
xt "86100,39500,89000,40500"
st "PSCLK"
ju 2
blo "89000,40300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "PSCLK"
t "std_logic"
prec "-- interface to: clock_generator_variable_PS_struct.vhd"
preAdd 0
posAdd 0
o 2
suid 2,0
)
)
)
*53 (CptPort
uid 775,0
ps "OnEdgeStrategy"
shape (Triangle
uid 776,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "90000,40625,90750,41375"
)
tg (CPTG
uid 777,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 778,0
va (VaSet
)
xt "86500,40500,89000,41500"
st "PSEN"
ju 2
blo "89000,41300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "PSEN"
t "std_logic"
preAdd 0
posAdd 0
o 3
suid 3,0
i "'0'"
)
)
)
*54 (CptPort
uid 779,0
ps "OnEdgeStrategy"
shape (Triangle
uid 780,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "90000,41625,90750,42375"
)
tg (CPTG
uid 781,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 782,0
va (VaSet
)
xt "84500,41500,89000,42500"
st "PSINCDEC"
ju 2
blo "89000,42300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "PSINCDEC"
t "std_logic"
eolc "-- default is 'incrementing'"
preAdd 0
posAdd 0
o 4
suid 4,0
i "'1'"
)
)
)
*55 (CptPort
uid 783,0
ps "OnEdgeStrategy"
shape (Triangle
uid 784,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "63250,35625,64000,36375"
)
tg (CPTG
uid 785,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 786,0
va (VaSet
)
xt "65000,35500,68700,36500"
st "PSDONE"
blo "65000,36300"
)
)
thePort (LogicalPort
decl (Decl
n "PSDONE"
t "std_logic"
eolc "-- will pulse once, if phase shifting was done."
preAdd 0
posAdd 0
o 5
suid 5,0
)
)
)
*56 (CptPort
uid 787,0
ps "OnEdgeStrategy"
shape (Triangle
uid 788,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "63250,34625,64000,35375"
)
tg (CPTG
uid 789,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 790,0
va (VaSet
)
xt "65000,34500,68600,35500"
st "LOCKED"
blo "65000,35300"
)
)
thePort (LogicalPort
decl (Decl
n "LOCKED"
t "std_logic"
preAdd 0
posAdd 0
o 6
suid 6,0
)
)
)
*57 (CptPort
uid 795,0
ps "OnEdgeStrategy"
shape (Triangle
uid 796,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "63250,40625,64000,41375"
)
tg (CPTG
uid 797,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 798,0
va (VaSet
)
xt "65000,40500,69600,41500"
st "shift_phase"
blo "65000,41300"
)
)
thePort (LogicalPort
decl (Decl
n "shift_phase"
t "std_logic"
prec "-- interface to: w5300_modul.vhd"
preAdd 0
posAdd 0
o 7
suid 8,0
)
)
)
*58 (CptPort
uid 799,0
ps "OnEdgeStrategy"
shape (Triangle
uid 800,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "63250,41625,64000,42375"
)
tg (CPTG
uid 801,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 802,0
va (VaSet
)
xt "65000,41500,68300,42500"
st "direction"
blo "65000,42300"
)
)
thePort (LogicalPort
decl (Decl
n "direction"
t "std_logic"
eolc "-- corresponds to 'PSINCDEC'"
preAdd 0
posAdd 0
o 8
suid 9,0
)
)
)
*59 (CptPort
uid 803,0
ps "OnEdgeStrategy"
shape (Triangle
uid 804,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "90000,31625,90750,32375"
)
tg (CPTG
uid 805,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 806,0
va (VaSet
)
xt "86100,31500,89000,32500"
st "shifting"
ju 2
blo "89000,32300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "shifting"
t "std_logic"
prec "-- status:"
preAdd 0
posAdd 0
o 9
suid 10,0
i "'0'"
)
)
)
*60 (CptPort
uid 807,0
ps "OnEdgeStrategy"
shape (Triangle
uid 808,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "90000,30625,90750,31375"
)
tg (CPTG
uid 809,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 810,0
va (VaSet
)
xt "86800,30500,89000,31500"
st "ready"
ju 2
blo "89000,31300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ready"
t "std_logic"
preAdd 0
posAdd 0
o 10
suid 11,0
i "'0'"
)
)
)
*61 (CptPort
uid 811,0
ps "OnEdgeStrategy"
shape (Triangle
uid 812,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "90000,33625,90750,34375"
)
tg (CPTG
uid 813,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 814,0
va (VaSet
)
xt "84200,33500,89000,34500"
st "offset : (7:0)"
ju 2
blo "89000,34300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "offset"
t "std_logic_vector"
b "(7 DOWNTO 0)"
preAdd 0
posAdd 0
o 11
suid 12,0
i "(OTHERS => '0')"
)
)
)
*62 (CptPort
uid 815,0
ps "OnEdgeStrategy"
shape (Triangle
uid 816,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "90000,34625,90750,35375"
)
tg (CPTG
uid 817,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 818,0
va (VaSet
)
xt "83800,34500,89000,35500"
st "DCM_locked"
ju 2
blo "89000,35300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "DCM_locked"
t "std_logic"
preAdd 0
posAdd 0
o 12
suid 13,0
)
)
)
]
shape (Rectangle
uid 827,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "64000,30000,90000,45000"
)
oxt "50000,7000,63000,25000"
ttg (MlTextGroup
uid 828,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*63 (Text
uid 829,0
va (VaSet
font "Arial,8,1"
)
xt "65700,26000,71900,27000"
st "FACT_FAD_lib"
blo "65700,26800"
tm "BdLibraryNameMgr"
)
*64 (Text
uid 830,0
va (VaSet
font "Arial,8,1"
)
xt "65700,27000,71500,28000"
st "phase_shifter"
blo "65700,27800"
tm "CptNameMgr"
)
*65 (Text
uid 831,0
va (VaSet
font "Arial,8,1"
)
xt "65700,28000,67500,29000"
st "U_4"
blo "65700,28800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 832,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 833,0
text (MLText
uid 834,0
va (VaSet
font "Courier New,8,0"
)
xt "64000,29000,64000,29000"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 835,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "64250,43250,65750,44750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*66 (Net
uid 853,0
decl (Decl
n "ready"
t "std_logic"
preAdd 0
posAdd 0
o 12
suid 23,0
i "'0'"
)
declText (MLText
uid 854,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,12400,50500,13200"
st "ready           : std_logic                    := '0'
"
)
)
*67 (PortIoOut
uid 861,0
shape (CompositeShape
uid 862,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 863,0
sl 0
ro 270
xt "100500,30625,102000,31375"
)
(Line
uid 864,0
sl 0
ro 270
xt "100000,31000,100500,31000"
pts [
"100000,31000"
"100500,31000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 865,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 866,0
va (VaSet
font "arial,8,0"
)
xt "103000,30500,105200,31500"
st "ready"
blo "103000,31300"
tm "WireNameMgr"
)
)
)
*68 (Net
uid 867,0
decl (Decl
n "shifting"
t "std_logic"
prec "-- status:"
preAdd 0
posAdd 0
o 13
suid 24,0
i "'0'"
)
declText (MLText
uid 868,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,13200,50500,14800"
st "-- status:
shifting        : std_logic                    := '0'
"
)
)
*69 (PortIoOut
uid 875,0
shape (CompositeShape
uid 876,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 877,0
sl 0
ro 270
xt "100500,31625,102000,32375"
)
(Line
uid 878,0
sl 0
ro 270
xt "100000,32000,100500,32000"
pts [
"100000,32000"
"100500,32000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 879,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 880,0
va (VaSet
font "arial,8,0"
)
xt "103000,31500,105900,32500"
st "shifting"
blo "103000,32300"
tm "WireNameMgr"
)
)
)
*70 (Net
uid 881,0
decl (Decl
n "offset"
t "std_logic_vector"
b "(7 downto 0)"
preAdd 0
posAdd 0
o 11
suid 25,0
i "(OTHERS => '0')"
)
declText (MLText
uid 882,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,11600,56500,12400"
st "offset          : std_logic_vector(7 downto 0) := (OTHERS => '0')
"
)
)
*71 (PortIoOut
uid 889,0
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lineWidth 2
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xt "95976,52730,96976,52730"
)
oxt "6976,6730,7976,6730"
)
]
shape (Rectangle
uid 1150,0
va (VaSet
vasetType 1
transparent 1
fg "0,65535,0"
lineColor "65535,65535,65535"
lineWidth -1
)
xt "95000,52000,98000,54000"
fos 1
)
showPorts 0
oxt "6000,6000,9000,8000"
ttg (MlTextGroup
uid 1151,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*118 (Text
uid 1152,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "95350,53100,100150,54100"
st "moduleware"
blo "95350,53900"
)
*119 (Text
uid 1153,0
va (VaSet
font "arial,8,0"
)
xt "95350,54100,100050,55100"
st "assignment"
blo "95350,54900"
)
*120 (Text
uid 1154,0
va (VaSet
font "arial,8,0"
)
xt "95350,55100,97150,56100"
st "U_8"
blo "95350,55900"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1155,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1156,0
text (MLText
uid 1157,0
va (VaSet
font "arial,8,0"
)
xt "90000,32400,90000,32400"
)
header ""
)
elements [
]
)
sed 1
awe 1
portVis (PortSigDisplay
disp 1
sN 0
sTC 0
selT 0
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
visOptions (mwParamsVisibilityOptions
)
)
*121 (MWC
uid 1186,0
optionalChildren [
*122 (CptPort
uid 1195,0
optionalChildren [
*123 (Line
uid 1200,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "95000,57000,95000,57000"
pts [
"95000,57000"
"95000,57000"
]
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 1196,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "94250,56625,95000,57375"
)
tg (CPTG
uid 1197,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1198,0
sl 0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "217200,355000,218000,356000"
st "s"
blo "217200,355800"
)
s (Text
uid 1199,0
sl 0
va (VaSet
font "arial,8,0"
)
xt "217200,356000,217200,356000"
blo "217200,356000"
)
)
thePort (LogicalPort
decl (Decl
n "s"
t "std_logic"
o 15
)
)
)
*124 (CptPort
uid 1201,0
optionalChildren [
*125 (Line
uid 1206,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "98000,57000,98000,57000"
pts [
"98000,57000"
"98000,57000"
]
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 1202,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "98000,56625,98750,57375"
)
tg (CPTG
uid 1203,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1204,0
sl 0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "221000,356000,221600,357000"
st "t"
ju 2
blo "221600,356800"
)
s (Text
uid 1205,0
sl 0
va (VaSet
font "arial,8,0"
)
xt "221600,357000,221600,357000"
ju 2
blo "221600,357000"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "t"
t "std_logic"
o 21
)
)
)
*126 (CommentGraphic
uid 1207,0
shape (PolyLine2D
pts [
"95000,57000"
"96000,56000"
]
uid 1208,0
layer 8
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
lineColor "26368,26368,26368"
lineWidth 2
)
xt "95000,56000,96000,57000"
)
oxt "6000,6000,7000,7000"
)
*127 (CommentGraphic
uid 1209,0
shape (PolyLine2D
pts [
"95000,57000"
"96000,58000"
]
uid 1210,0
layer 8
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
lineColor "26368,26368,26368"
lineWidth 2
)
xt "95000,57000,96000,58000"
)
oxt "6000,7000,7000,8000"
)
*128 (CommentGraphic
uid 1211,0
shape (PolyLine2D
pts [
"95988,57329"
"96988,57329"
]
uid 1212,0
layer 8
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
lineColor "26368,26368,26368"
lineWidth 2
)
xt "95988,57329,96988,57329"
)
oxt "6988,7329,7988,7329"
)
*129 (CommentGraphic
uid 1213,0
shape (PolyLine2D
pts [
"97000,57000"
"98000,57000"
]
uid 1214,0
layer 0
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
)
xt "97000,57000,98000,57000"
)
oxt "8000,7000,9000,7000"
)
*130 (CommentGraphic
uid 1215,0
shape (PolyLine2D
pts [
"95976,56730"
"96976,56730"
]
uid 1216,0
layer 8
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
lineColor "26368,26368,26368"
lineWidth 2
)
xt "95976,56730,96976,56730"
)
oxt "6976,6730,7976,6730"
)
]
shape (Rectangle
uid 1187,0
va (VaSet
vasetType 1
transparent 1
fg "0,65535,0"
lineColor "65535,65535,65535"
lineWidth -1
)
xt "95000,56000,98000,58000"
fos 1
)
showPorts 0
oxt "6000,6000,9000,8000"
ttg (MlTextGroup
uid 1188,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*131 (Text
uid 1189,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "95350,57100,100150,58100"
st "moduleware"
blo "95350,57900"
)
*132 (Text
uid 1190,0
va (VaSet
font "arial,8,0"
)
xt "95350,58100,100050,59100"
st "assignment"
blo "95350,58900"
)
*133 (Text
uid 1191,0
va (VaSet
font "arial,8,0"
)
xt "95350,59100,97150,60100"
st "U_9"
blo "95350,59900"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1192,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1193,0
text (MLText
uid 1194,0
va (VaSet
font "arial,8,0"
)
xt "90000,36400,90000,36400"
)
header ""
)
elements [
]
)
sed 1
awe 1
portVis (PortSigDisplay
disp 1
sN 0
sTC 0
selT 0
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
visOptions (mwParamsVisibilityOptions
)
)
*134 (PortIoOut
uid 1248,0
shape (CompositeShape
uid 1249,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 1250,0
sl 0
ro 270
xt "68500,21625,70000,22375"
)
(Line
uid 1251,0
sl 0
ro 270
xt "68000,22000,68500,22000"
pts [
"68000,22000"
"68500,22000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 1252,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1253,0
va (VaSet
font "arial,8,0"
)
xt "71000,21500,75500,22500"
st "CLK_25_PS"
blo "71000,22300"
tm "WireNameMgr"
)
)
)
*135 (Net
uid 1260,0
decl (Decl
n "CLK_25_PS"
t "std_logic"
o 22
suid 34,0
)
declText (MLText
uid 1261,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,6000,37000,6800"
st "CLK_25_PS       : std_logic
"
)
)
*136 (PortIoIn
uid 1266,0
shape (CompositeShape
uid 1267,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 1268,0
sl 0
ro 270
xt "37000,63625,38500,64375"
)
(Line
uid 1269,0
sl 0
ro 270
xt "38500,64000,39000,64000"
pts [
"38500,64000"
"39000,64000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 1270,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1271,0
va (VaSet
font "arial,8,0"
)
xt "33000,63500,36000,64500"
st "do_shift"
ju 2
blo "36000,64300"
tm "WireNameMgr"
)
)
)
*137 (Net
uid 1278,0
decl (Decl
n "do_shift"
t "std_logic"
o 23
suid 35,0
)
declText (MLText
uid 1279,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,4400,37000,5200"
st "do_shift        : std_logic
"
)
)
*138 (PortIoIn
uid 1280,0
shape (CompositeShape
uid 1281,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 1282,0
sl 0
ro 270
xt "37000,65625,38500,66375"
)
(Line
uid 1283,0
sl 0
ro 270
xt "38500,66000,39000,66000"
pts [
"38500,66000"
"39000,66000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 1284,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1285,0
va (VaSet
font "arial,8,0"
)
xt "32700,65500,36000,66500"
st "direction"
ju 2
blo "36000,66300"
tm "WireNameMgr"
)
)
)
*139 (Net
uid 1292,0
decl (Decl
n "direction"
t "std_logic"
o 24
suid 36,0
)
declText (MLText
uid 1293,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,3600,37000,4400"
st "direction       : std_logic
"
)
)
*140 (Net
uid 1491,0
decl (Decl
n "RST_IN"
t "std_logic"
o 22
suid 37,0
)
declText (MLText
uid 1492,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,2800,37000,3600"
st "RST_IN          : std_logic
"
)
)
*141 (PortIoIn
uid 1499,0
shape (CompositeShape
uid 1500,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 1501,0
sl 0
ro 270
xt "32000,37625,33500,38375"
)
(Line
uid 1502,0
sl 0
ro 270
xt "33500,38000,34000,38000"
pts [
"33500,38000"
"34000,38000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 1503,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1504,0
va (VaSet
font "arial,8,0"
)
xt "27800,37500,31000,38500"
st "RST_IN"
ju 2
blo "31000,38300"
tm "WireNameMgr"
)
)
)
*142 (Wire
uid 163,0
shape (OrthoPolyLine
uid 164,0
va (VaSet
vasetType 3
)
xt "10000,14000,16250,14000"
pts [
"10000,14000"
"16250,14000"
]
)
start &12
end &25
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 167,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 168,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "11000,13000,12900,14000"
st "CLK"
blo "11000,13800"
tm "WireNameMgr"
)
)
on &17
)
*143 (Wire
uid 191,0
shape (OrthoPolyLine
uid 192,0
va (VaSet
vasetType 3
)
xt "32750,16000,39000,16000"
pts [
"32750,16000"
"39000,16000"
]
)
start &28
end &13
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 195,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 196,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "34000,15000,37100,16000"
st "CLK_50"
blo "34000,15800"
tm "WireNameMgr"
)
)
on &15
)
*144 (Wire
uid 209,0
optionalChildren [
*145 (BdJunction
uid 233,0
ps "OnConnectorStrategy"
shape (Circle
uid 234,0
va (VaSet
vasetType 1
)
xt "35600,13600,36400,14400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 210,0
va (VaSet
vasetType 3
)
xt "32750,14000,39000,14000"
pts [
"32750,14000"
"39000,14000"
]
)
start &26
end &14
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 213,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 214,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "34000,13000,37100,14000"
st "CLK_25"
blo "34000,13800"
tm "WireNameMgr"
)
)
on &16
)
*146 (Wire
uid 229,0
shape (OrthoPolyLine
uid 230,0
va (VaSet
vasetType 3
)
xt "16000,14000,36000,26000"
pts [
"36000,14000"
"36000,23000"
"16000,23000"
"16000,26000"
"20250,26000"
]
)
start &145
end &19
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 231,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 232,0
va (VaSet
font "arial,8,0"
)
xt "17000,25000,20100,26000"
st "CLK_25"
blo "17000,25800"
tm "WireNameMgr"
)
)
on &16
)
*147 (Wire
uid 526,0
optionalChildren [
*148 (BdJunction
uid 1462,0
ps "OnConnectorStrategy"
shape (Circle
uid 1463,0
va (VaSet
vasetType 1
)
xt "35600,30600,36400,31400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 527,0
va (VaSet
vasetType 3
)
xt "32750,28000,39250,34000"
pts [
"32750,28000"
"36000,28000"
"36000,34000"
"39250,34000"
]
)
start &20
end &33
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 528,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 529,0
va (VaSet
font "arial,8,0"
)
xt "34750,33000,39150,34000"
st "CLK0_OUT"
blo "34750,33800"
tm "WireNameMgr"
)
)
on &44
)
*149 (Wire
uid 532,0
optionalChildren [
*150 (BdJunction
uid 1073,0
ps "OnConnectorStrategy"
shape (Circle
uid 1074,0
va (VaSet
vasetType 1
)
xt "92600,39600,93400,40400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 533,0
va (VaSet
vasetType 3
)
xt "29000,35000,93000,48000"
pts [
"90750,40000"
"93000,40000"
"93000,48000"
"29000,48000"
"29000,35000"
"39250,35000"
]
)
start &52
end &34
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 536,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 537,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "92750,39000,96850,40000"
st "PSCLK_IN"
blo "92750,39800"
tm "WireNameMgr"
)
)
on &45
)
*151 (Wire
uid 546,0
shape (OrthoPolyLine
uid 547,0
va (VaSet
vasetType 3
)
xt "30000,36000,92000,47000"
pts [
"90750,41000"
"92000,41000"
"92000,47000"
"30000,47000"
"30000,36000"
"39250,36000"
]
)
start &53
end &35
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 550,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 551,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "92750,40000,96450,41000"
st "PSEN_IN"
blo "92750,40800"
tm "WireNameMgr"
)
)
on &46
)
*152 (Wire
uid 588,0
optionalChildren [
*153 (BdJunction
uid 1184,0
ps "OnConnectorStrategy"
shape (Circle
uid 1185,0
va (VaSet
vasetType 1
)
xt "57600,35600,58400,36400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 589,0
va (VaSet
vasetType 3
)
xt "55750,36000,63250,36000"
pts [
"55750,36000"
"63250,36000"
]
)
start &39
end &55
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 592,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 593,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "57750,35000,63950,36000"
st "PSDONE_OUT"
blo "57750,35800"
tm "WireNameMgr"
)
)
on &48
)
*154 (Wire
uid 602,0
optionalChildren [
*155 (BdJunction
uid 1221,0
ps "OnConnectorStrategy"
shape (Circle
uid 1222,0
va (VaSet
vasetType 1
)
xt "56600,34600,57400,35400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 603,0
va (VaSet
vasetType 3
)
xt "55750,35000,63250,35000"
pts [
"55750,35000"
"63250,35000"
]
)
start &38
end &56
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 606,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 607,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "57750,34000,63850,35000"
st "LOCKED_OUT"
blo "57750,34800"
tm "WireNameMgr"
)
)
on &49
)
*156 (Wire
uid 841,0
optionalChildren [
*157 (BdJunction
uid 1147,0
ps "OnConnectorStrategy"
shape (Circle
uid 1148,0
va (VaSet
vasetType 1
)
xt "90350,45600,91150,46400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 842,0
va (VaSet
vasetType 3
)
xt "31000,37000,90750,46000"
pts [
"90750,42000"
"90750,46000"
"31000,46000"
"31000,37000"
"39250,37000"
]
)
start &54
end &36
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 843,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 844,0
ro 270
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "53000,41900,54000,48000"
st "PSINCDEC_IN"
blo "53800,48000"
tm "WireNameMgr"
)
)
on &47
)
*158 (Wire
uid 855,0
shape (OrthoPolyLine
uid 856,0
va (VaSet
vasetType 3
)
xt "90750,31000,100000,31000"
pts [
"90750,31000"
"100000,31000"
]
)
start &60
end &67
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 859,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 860,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "92000,30000,94200,31000"
st "ready"
blo "92000,30800"
tm "WireNameMgr"
)
)
on &66
)
*159 (Wire
uid 869,0
shape (OrthoPolyLine
uid 870,0
va (VaSet
vasetType 3
)
xt "90750,32000,100000,32000"
pts [
"90750,32000"
"100000,32000"
]
)
start &59
end &69
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 873,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 874,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "92000,31000,94900,32000"
st "shifting"
blo "92000,31800"
tm "WireNameMgr"
)
)
on &68
)
*160 (Wire
uid 883,0
shape (OrthoPolyLine
uid 884,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "90750,34000,100000,34000"
pts [
"90750,34000"
"100000,34000"
]
)
start &61
end &71
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 887,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 888,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "92000,33000,94200,34000"
st "offset"
blo "92000,33800"
tm "WireNameMgr"
)
)
on &70
)
*161 (Wire
uid 897,0
shape (OrthoPolyLine
uid 898,0
va (VaSet
vasetType 3
)
xt "90750,35000,100000,35000"
pts [
"90750,35000"
"100000,35000"
]
)
start &62
end &73
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 901,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 902,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "92000,34000,97200,35000"
st "DCM_locked"
blo "92000,34800"
tm "WireNameMgr"
)
)
on &72
)
*162 (Wire
uid 974,0
shape (OrthoPolyLine
uid 975,0
va (VaSet
vasetType 3
)
xt "98000,40000,110000,40000"
pts [
"98000,40000"
"110000,40000"
]
)
start &85
end &74
ss 0
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 978,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 979,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "100000,39000,105000,40000"
st "PSCLK_OUT"
blo "100000,39800"
tm "WireNameMgr"
)
)
on &75
)
*163 (Wire
uid 1002,0
shape (OrthoPolyLine
uid 1003,0
va (VaSet
vasetType 3
)
xt "98000,49000,110000,49000"
pts [
"98000,49000"
"110000,49000"
]
)
start &98
end &76
ss 0
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 1006,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1007,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "100000,48000,107000,49000"
st "PSINCDEC_OUT"
blo "100000,48800"
tm "WireNameMgr"
)
)
on &77
)
*164 (Wire
uid 1016,0
shape (OrthoPolyLine
uid 1017,0
va (VaSet
vasetType 3
)
xt "98000,53000,110000,53000"
pts [
"98000,53000"
"110000,53000"
]
)
start &111
end &78
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 1020,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1021,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "100000,52000,107800,53000"
st "PSDONE_extraOUT"
blo "100000,52800"
tm "WireNameMgr"
)
)
on &79
)
*165 (Wire
uid 1030,0
shape (OrthoPolyLine
uid 1031,0
va (VaSet
vasetType 3
)
xt "98000,57000,110000,57000"
pts [
"98000,57000"
"110000,57000"
]
)
start &124
end &80
ss 0
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 1034,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1035,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "100000,56000,107700,57000"
st "LOCKED_extraOUT"
blo "100000,56800"
tm "WireNameMgr"
)
)
on &81
)
*166 (Wire
uid 1069,0
shape (OrthoPolyLine
uid 1070,0
va (VaSet
vasetType 3
)
xt "93000,40000,95000,40000"
pts [
"93000,40000"
"95000,40000"
]
)
start &150
end &83
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1071,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1072,0
va (VaSet
font "arial,8,0"
)
xt "90000,39000,94100,40000"
st "PSCLK_IN"
blo "90000,39800"
tm "WireNameMgr"
)
)
on &45
)
*167 (Wire
uid 1143,0
shape (OrthoPolyLine
uid 1144,0
va (VaSet
vasetType 3
)
xt "90750,46000,95000,49000"
pts [
"90750,46000"
"91000,46000"
"91000,49000"
"95000,49000"
]
)
start &157
end &96
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1145,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1146,0
va (VaSet
font "arial,8,0"
)
xt "88000,48000,94100,49000"
st "PSINCDEC_IN"
blo "88000,48800"
tm "WireNameMgr"
)
)
on &47
)
*168 (Wire
uid 1180,0
shape (OrthoPolyLine
uid 1181,0
va (VaSet
vasetType 3
)
xt "58000,36000,95000,53000"
pts [
"58000,36000"
"58000,53000"
"95000,53000"
]
)
start &153
end &109
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1182,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1183,0
va (VaSet
font "arial,8,0"
)
xt "88000,52000,94200,53000"
st "PSDONE_OUT"
blo "88000,52800"
tm "WireNameMgr"
)
)
on &48
)
*169 (Wire
uid 1217,0
shape (OrthoPolyLine
uid 1218,0
va (VaSet
vasetType 3
)
xt "57000,35000,95000,57000"
pts [
"57000,35000"
"57000,57000"
"95000,57000"
]
)
start &155
end &122
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1219,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1220,0
va (VaSet
font "arial,8,0"
)
xt "88000,56000,94100,57000"
st "LOCKED_OUT"
blo "88000,56800"
tm "WireNameMgr"
)
)
on &49
)
*170 (Wire
uid 1254,0
shape (OrthoPolyLine
uid 1255,0
va (VaSet
vasetType 3
)
xt "55750,22000,68000,34000"
pts [
"55750,34000"
"57000,34000"
"57000,22000"
"68000,22000"
]
)
start &37
end &134
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1258,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1259,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "57750,33000,62250,34000"
st "CLK_25_PS"
blo "57750,33800"
tm "WireNameMgr"
)
)
on &135
)
*171 (Wire
uid 1272,0
shape (OrthoPolyLine
uid 1273,0
va (VaSet
vasetType 3
)
xt "39000,41000,63250,64000"
pts [
"39000,64000"
"49000,64000"
"49000,41000"
"63250,41000"
]
)
start &136
end &57
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1276,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1277,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "41000,63000,44000,64000"
st "do_shift"
blo "41000,63800"
tm "WireNameMgr"
)
)
on &137
)
*172 (Wire
uid 1286,0
shape (OrthoPolyLine
uid 1287,0
va (VaSet
vasetType 3
)
xt "39000,42000,63250,66000"
pts [
"39000,66000"
"50000,66000"
"50000,42000"
"63250,42000"
]
)
start &138
end &58
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1290,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1291,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "41000,65000,44300,66000"
st "direction"
blo "41000,65800"
tm "WireNameMgr"
)
)
on &139
)
*173 (Wire
uid 1458,0
shape (OrthoPolyLine
uid 1459,0
va (VaSet
vasetType 3
)
xt "36000,31000,63250,31000"
pts [
"36000,31000"
"63250,31000"
]
)
start &148
end &51
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1460,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1461,0
va (VaSet
font "arial,8,0"
)
xt "58250,30000,62650,31000"
st "CLK0_OUT"
blo "58250,30800"
tm "WireNameMgr"
)
)
on &44
)
*174 (Wire
uid 1493,0
shape (OrthoPolyLine
uid 1494,0
va (VaSet
vasetType 3
)
xt "34000,38000,39250,38000"
pts [
"34000,38000"
"39250,38000"
]
)
start &141
end &40
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1497,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1498,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "35000,37000,38200,38000"
st "RST_IN"
blo "35000,37800"
tm "WireNameMgr"
)
)
on &140
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 1
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *175 (PackageList
uid 41,0
stg "VerticalLayoutStrategy"
textVec [
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uid 42,0
va (VaSet
font "arial,8,1"
)
xt "0,0,5400,1000"
st "Package List"
blo "0,800"
)
*177 (MLText
uid 43,0
va (VaSet
font "arial,8,0"
)
xt "0,1000,12300,7000"
st "LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.numeric_std.all;
LIBRARY UNISIM;
--USE UNISIM.Vcomponents.all;"
tm "PackageList"
)
]
)
compDirBlock (MlTextGroup
uid 44,0
stg "VerticalLayoutStrategy"
textVec [
*178 (Text
uid 45,0
va (VaSet
isHidden 1
font "arial,8,1"
)
xt "20000,0,28100,1000"
st "Compiler Directives"
blo "20000,800"
)
*179 (Text
uid 46,0
va (VaSet
isHidden 1
font "arial,8,1"
)
xt "20000,1000,29600,2000"
st "Pre-module directives:"
blo "20000,1800"
)
*180 (MLText
uid 47,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "20000,2000,27500,4000"
st "`resetall
`timescale 1ns/10ps"
tm "BdCompilerDirectivesTextMgr"
)
*181 (Text
uid 48,0
va (VaSet
isHidden 1
font "arial,8,1"
)
xt "20000,4000,30100,5000"
st "Post-module directives:"
blo "20000,4800"
)
*182 (MLText
uid 49,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "20000,0,20000,0"
tm "BdCompilerDirectivesTextMgr"
)
*183 (Text
uid 50,0
va (VaSet
isHidden 1
font "arial,8,1"
)
xt "20000,5000,29900,6000"
st "End-module directives:"
blo "20000,5800"
)
*184 (MLText
uid 51,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "20000,6000,20000,6000"
tm "BdCompilerDirectivesTextMgr"
)
]
associable 1
)
windowSize "0,0,1281,1024"
viewArea "51518,24931,132154,91431"
cachedDiagramExtent "0,0,221600,357000"
pageSetupInfo (PageSetupInfo
ptrCmd ""
toPrinter 1
exportedDirectories [
"$HDS_PROJECT_DIR/HTMLExport"
]
exportStdIncludeRefs 1
exportStdPackageRefs 1
)
hasePageBreakOrigin 1
pageBreakOrigin "0,0"
lastUid 1552,0
defaultCommentText (CommentText
shape (Rectangle
layer 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
lineColor "0,0,32768"
)
xt "0,0,15000,5000"
)
text (MLText
va (VaSet
fg "0,0,32768"
font "arial,8,0"
)
xt "200,200,2000,1200"
st "
Text
"
tm "CommentText"
wrapOption 3
visibleHeight 4600
visibleWidth 14600
)
)
defaultPanel (Panel
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "32768,0,0"
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (Text
va (VaSet
font "arial,8,1"
)
xt "1000,1000,3800,2000"
st "Panel0"
blo "1000,1800"
tm "PanelText"
)
)
)
defaultBlk (Blk
shape (Rectangle
va (VaSet
vasetType 1
fg "39936,56832,65280"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
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va (VaSet
font "arial,8,1"
)
xt "2200,3500,5800,4500"
st "<library>"
blo "2200,4300"
tm "BdLibraryNameMgr"
)
*186 (Text
va (VaSet
font "arial,8,1"
)
xt "2200,4500,5600,5500"
st "<block>"
blo "2200,5300"
tm "BlkNameMgr"
)
*187 (Text
va (VaSet
font "arial,8,1"
)
xt "2200,5500,4000,6500"
st "U_0"
blo "2200,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "2200,13500,2200,13500"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
)
defaultMWComponent (MWC
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
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*188 (Text
va (VaSet
font "arial,8,1"
)
xt "550,3500,3450,4500"
st "Library"
blo "550,4300"
)
*189 (Text
va (VaSet
font "arial,8,1"
)
xt "550,4500,7450,5500"
st "MWComponent"
blo "550,5300"
)
*190 (Text
va (VaSet
font "arial,8,1"
)
xt "550,5500,2350,6500"
st "U_0"
blo "550,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-6450,1500,-6450,1500"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
visOptions (mwParamsVisibilityOptions
)
)
defaultSaComponent (SaComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*191 (Text
va (VaSet
font "arial,8,1"
)
xt "900,3500,3800,4500"
st "Library"
blo "900,4300"
tm "BdLibraryNameMgr"
)
*192 (Text
va (VaSet
font "arial,8,1"
)
xt "900,4500,7100,5500"
st "SaComponent"
blo "900,5300"
tm "CptNameMgr"
)
*193 (Text
va (VaSet
font "arial,8,1"
)
xt "900,5500,2700,6500"
st "U_0"
blo "900,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-6100,1500,-6100,1500"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
defaultVhdlComponent (VhdlComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
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va (VaSet
font "arial,8,1"
)
xt "500,3500,3400,4500"
st "Library"
blo "500,4300"
)
*195 (Text
va (VaSet
font "arial,8,1"
)
xt "500,4500,7500,5500"
st "VhdlComponent"
blo "500,5300"
)
*196 (Text
va (VaSet
font "arial,8,1"
)
xt "500,5500,2300,6500"
st "U_0"
blo "500,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-6500,1500,-6500,1500"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
)
entityPath ""
archName ""
archPath ""
)
defaultVerilogComponent (VerilogComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-450,0,8450,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
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va (VaSet
font "arial,8,1"
)
xt "50,3500,2950,4500"
st "Library"
blo "50,4300"
)
*198 (Text
va (VaSet
font "arial,8,1"
)
xt "50,4500,7950,5500"
st "VerilogComponent"
blo "50,5300"
)
*199 (Text
va (VaSet
font "arial,8,1"
)
xt "50,5500,1850,6500"
st "U_0"
blo "50,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-6950,1500,-6950,1500"
)
header ""
)
elements [
]
)
entityPath ""
)
defaultHdlText (HdlText
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,37120"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
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va (VaSet
font "arial,8,1"
)
xt "3150,4000,4850,5000"
st "eb1"
blo "3150,4800"
tm "HdlTextNameMgr"
)
*201 (Text
va (VaSet
font "arial,8,1"
)
xt "3150,5000,3950,6000"
st "1"
blo "3150,5800"
tm "HdlTextNumberMgr"
)
]
)
viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
)
defaultEmbeddedText (EmbeddedText
commentText (CommentText
ps "CenterOffsetStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,18000,5000"
)
text (MLText
va (VaSet
font "arial,8,0"
)
xt "200,200,2000,1200"
st "
Text
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 4600
visibleWidth 17600
)
)
)
defaultGlobalConnector (GlobalConnector
shape (Circle
va (VaSet
vasetType 1
fg "65535,65535,0"
)
xt "-1000,-1000,1000,1000"
radius 1000
)
name (Text
va (VaSet
font "arial,8,1"
)
xt "-500,-500,500,500"
st "G"
blo "-500,300"
)
)
defaultRipper (Ripper
ps "OnConnectorStrategy"
shape (Line2D
pts [
"0,0"
"1000,1000"
]
va (VaSet
vasetType 1
)
xt "0,0,1000,1000"
)
)
defaultBdJunction (BdJunction
ps "OnConnectorStrategy"
shape (Circle
va (VaSet
vasetType 1
)
xt "-400,-400,400,400"
radius 400
)
)
defaultPortIoIn (PortIoIn
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "-2000,-375,-500,375"
)
(Line
sl 0
ro 270
xt "-500,0,0,0"
pts [
"-500,0"
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]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
font "arial,8,0"
)
xt "-1375,-1000,-1375,-1000"
ju 2
blo "-1375,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoOut (PortIoOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "500,-375,2000,375"
)
(Line
sl 0
ro 270
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
font "arial,8,0"
)
xt "625,-1000,625,-1000"
blo "625,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoInOut (PortIoInOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
font "arial,8,0"
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultPortIoBuffer (PortIoBuffer
shape (CompositeShape
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
font "arial,8,0"
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultSignal (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
font "arial,8,0"
)
xt "0,0,1900,1000"
st "sig0"
blo "0,800"
tm "WireNameMgr"
)
)
)
defaultBus (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineWidth 2
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
font "arial,8,0"
)
xt "0,0,2400,1000"
st "dbus0"
blo "0,800"
tm "WireNameMgr"
)
)
)
defaultBundle (Bundle
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineColor "32768,0,0"
lineWidth 2
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
textGroup (BiTextGroup
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
first (Text
va (VaSet
font "arial,8,0"
)
xt "0,0,3000,1000"
st "bundle0"
blo "0,800"
tm "BundleNameMgr"
)
second (MLText
va (VaSet
font "arial,8,0"
)
xt "0,1000,1000,2000"
st "()"
tm "BundleContentsMgr"
)
)
bundleNet &0
)
defaultPortMapFrame (PortMapFrame
ps "PortMapFrameStrategy"
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,10000,12000"
)
portMapText (BiTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
first (MLText
va (VaSet
font "arial,8,0"
)
)
second (MLText
va (VaSet
font "arial,8,0"
)
tm "PortMapTextMgr"
)
)
)
defaultGenFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "26368,26368,26368"
lineStyle 2
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
font "arial,8,0"
)
xt "0,-1100,12600,-100"
st "g0: FOR i IN 0 TO n GENERATE"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1250,1450"
)
num (Text
va (VaSet
font "arial,8,0"
)
xt "250,250,1050,1250"
st "1"
blo "250,1050"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*202 (Text
va (VaSet
font "arial,8,1"
)
xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*203 (MLText
va (VaSet
font "arial,8,0"
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
)
]
)
)
defaultBlockFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "26368,26368,26368"
lineStyle 1
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
font "arial,8,0"
)
xt "0,-1100,7400,-100"
st "b0: BLOCK (guard)"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1250,1450"
)
num (Text
va (VaSet
font "arial,8,0"
)
xt "250,250,1050,1250"
st "1"
blo "250,1050"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*204 (Text
va (VaSet
font "arial,8,1"
)
xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*205 (MLText
va (VaSet
font "arial,8,0"
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
)
]
)
style 3
)
defaultSaCptPort (CptPort
ps "OnEdgeStrategy"
shape (Triangle
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
font "arial,8,0"
)
xt "0,750,1800,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultSaCptPortBuffer (CptPort
ps "OnEdgeStrategy"
shape (Diamond
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
font "arial,8,0"
)
xt "0,750,1800,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
m 3
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultDeclText (MLText
va (VaSet
font "Courier New,8,0"
)
)
archDeclarativeBlock (BdArchDeclBlock
uid 1,0
stg "BdArchDeclBlockLS"
declLabel (Text
uid 2,0
va (VaSet
font "arial,8,1"
)
xt "20000,0,25400,1000"
st "Declarations"
blo "20000,800"
)
portLabel (Text
uid 3,0
va (VaSet
font "arial,8,1"
)
xt "20000,1000,22700,2000"
st "Ports:"
blo "20000,1800"
)
preUserLabel (Text
uid 4,0
va (VaSet
isHidden 1
font "arial,8,1"
)
xt "20000,0,23800,1000"
st "Pre User:"
blo "20000,800"
)
preUserText (MLText
uid 5,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "20000,0,20000,0"
tm "BdDeclarativeTextMgr"
)
diagSignalLabel (Text
uid 6,0
va (VaSet
font "arial,8,1"
)
xt "20000,14800,27100,15800"
st "Diagram Signals:"
blo "20000,15600"
)
postUserLabel (Text
uid 7,0
va (VaSet
isHidden 1
font "arial,8,1"
)
xt "20000,0,24700,1000"
st "Post User:"
blo "20000,800"
)
postUserText (MLText
uid 8,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "20000,0,20000,0"
tm "BdDeclarativeTextMgr"
)
)
commonDM (CommonDM
ldm (LogicalDM
suid 37,0
usingSuid 1
emptyRow *206 (LEmptyRow
)
uid 54,0
optionalChildren [
*207 (RefLabelRowHdr
)
*208 (TitleRowHdr
)
*209 (FilterRowHdr
)
*210 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*211 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*212 (GroupColHdr
tm "GroupColHdrMgr"
)
*213 (NameColHdr
tm "BlockDiagramNameColHdrMgr"
)
*214 (ModeColHdr
tm "BlockDiagramModeColHdrMgr"
)
*215 (TypeColHdr
tm "BlockDiagramTypeColHdrMgr"
)
*216 (BoundsColHdr
tm "BlockDiagramBoundsColHdrMgr"
)
*217 (InitColHdr
tm "BlockDiagramInitColHdrMgr"
)
*218 (EolColHdr
tm "BlockDiagramEolColHdrMgr"
)
*219 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "CLK_50"
t "std_logic"
o 3
suid 9,0
)
)
uid 237,0
)
*220 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "CLK_25"
t "std_logic"
o 2
suid 10,0
)
)
uid 239,0
)
*221 (LeafLogPort
port (LogicalPort
decl (Decl
n "CLK"
t "std_logic"
o 1
suid 13,0
)
)
uid 295,0
)
*222 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "CLK0_OUT"
t "std_logic"
o 14
suid 14,0
)
)
uid 614,0
)
*223 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "PSCLK_IN"
t "std_logic"
o 16
suid 15,0
)
)
uid 616,0
)
*224 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "PSEN_IN"
t "std_logic"
o 18
suid 16,0
)
)
uid 618,0
)
*225 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "PSINCDEC_IN"
t "std_logic"
o 19
suid 17,0
)
)
uid 620,0
)
*226 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "PSDONE_OUT"
t "std_logic"
o 17
suid 19,0
)
)
uid 624,0
)
*227 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "LOCKED_OUT"
t "std_logic"
o 15
suid 20,0
)
)
uid 626,0
)
*228 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "ready"
t "std_logic"
preAdd 0
posAdd 0
o 12
suid 23,0
i "'0'"
)
)
uid 923,0
)
*229 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "shifting"
t "std_logic"
prec "-- status:"
preAdd 0
posAdd 0
o 13
suid 24,0
i "'0'"
)
)
uid 925,0
)
*230 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "offset"
t "std_logic_vector"
b "(7 downto 0)"
preAdd 0
posAdd 0
o 11
suid 25,0
i "(OTHERS => '0')"
)
)
uid 927,0
)
*231 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "DCM_locked"
t "std_logic"
preAdd 0
posAdd 0
o 4
suid 26,0
)
)
uid 929,0
)
*232 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "PSCLK_OUT"
t "std_logic"
o 17
suid 28,0
)
)
uid 956,0
scheme 0
)
*233 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "PSINCDEC_OUT"
t "std_logic"
o 19
suid 30,0
)
)
uid 960,0
scheme 0
)
*234 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "PSDONE_extraOUT"
t "std_logic"
o 20
suid 31,0
)
)
uid 962,0
scheme 0
)
*235 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "LOCKED_extraOUT"
t "std_logic"
o 21
suid 32,0
)
)
uid 964,0
scheme 0
)
*236 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "CLK_25_PS"
t "std_logic"
o 22
suid 34,0
)
)
uid 1246,0
scheme 0
)
*237 (LeafLogPort
port (LogicalPort
decl (Decl
n "do_shift"
t "std_logic"
o 23
suid 35,0
)
)
uid 1262,0
scheme 0
)
*238 (LeafLogPort
port (LogicalPort
decl (Decl
n "direction"
t "std_logic"
o 24
suid 36,0
)
)
uid 1264,0
scheme 0
)
*239 (LeafLogPort
port (LogicalPort
decl (Decl
n "RST_IN"
t "std_logic"
o 22
suid 37,0
)
)
uid 1505,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 67,0
optionalChildren [
*240 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *241 (MRCItem
litem &206
pos 21
dimension 20
)
uid 69,0
optionalChildren [
*242 (MRCItem
litem &207
pos 0
dimension 20
uid 70,0
)
*243 (MRCItem
litem &208
pos 1
dimension 23
uid 71,0
)
*244 (MRCItem
litem &209
pos 2
hidden 1
dimension 20
uid 72,0
)
*245 (MRCItem
litem &219
pos 0
dimension 20
uid 238,0
)
*246 (MRCItem
litem &220
pos 1
dimension 20
uid 240,0
)
*247 (MRCItem
litem &221
pos 2
dimension 20
uid 296,0
)
*248 (MRCItem
litem &222
pos 8
dimension 20
uid 615,0
)
*249 (MRCItem
litem &223
pos 3
dimension 20
uid 617,0
)
*250 (MRCItem
litem &224
pos 4
dimension 20
uid 619,0
)
*251 (MRCItem
litem &225
pos 5
dimension 20
uid 621,0
)
*252 (MRCItem
litem &226
pos 6
dimension 20
uid 625,0
)
*253 (MRCItem
litem &227
pos 7
dimension 20
uid 627,0
)
*254 (MRCItem
litem &228
pos 9
dimension 20
uid 924,0
)
*255 (MRCItem
litem &229
pos 10
dimension 20
uid 926,0
)
*256 (MRCItem
litem &230
pos 11
dimension 20
uid 928,0
)
*257 (MRCItem
litem &231
pos 12
dimension 20
uid 930,0
)
*258 (MRCItem
litem &232
pos 13
dimension 20
uid 957,0
)
*259 (MRCItem
litem &233
pos 14
dimension 20
uid 961,0
)
*260 (MRCItem
litem &234
pos 15
dimension 20
uid 963,0
)
*261 (MRCItem
litem &235
pos 16
dimension 20
uid 965,0
)
*262 (MRCItem
litem &236
pos 17
dimension 20
uid 1247,0
)
*263 (MRCItem
litem &237
pos 18
dimension 20
uid 1263,0
)
*264 (MRCItem
litem &238
pos 19
dimension 20
uid 1265,0
)
*265 (MRCItem
litem &239
pos 20
dimension 20
uid 1506,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 73,0
optionalChildren [
*266 (MRCItem
litem &210
pos 0
dimension 20
uid 74,0
)
*267 (MRCItem
litem &212
pos 1
dimension 50
uid 75,0
)
*268 (MRCItem
litem &213
pos 2
dimension 100
uid 76,0
)
*269 (MRCItem
litem &214
pos 3
dimension 50
uid 77,0
)
*270 (MRCItem
litem &215
pos 4
dimension 100
uid 78,0
)
*271 (MRCItem
litem &216
pos 5
dimension 100
uid 79,0
)
*272 (MRCItem
litem &217
pos 6
dimension 50
uid 80,0
)
*273 (MRCItem
litem &218
pos 7
dimension 80
uid 81,0
)
]
)
fixedCol 4
fixedRow 2
name "Ports"
uid 68,0
vaOverrides [
]
)
]
)
uid 53,0
)
genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *274 (LEmptyRow
)
uid 83,0
optionalChildren [
*275 (RefLabelRowHdr
)
*276 (TitleRowHdr
)
*277 (FilterRowHdr
)
*278 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*279 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*280 (GroupColHdr
tm "GroupColHdrMgr"
)
*281 (NameColHdr
tm "GenericNameColHdrMgr"
)
*282 (TypeColHdr
tm "GenericTypeColHdrMgr"
)
*283 (InitColHdr
tm "GenericValueColHdrMgr"
)
*284 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
)
*285 (EolColHdr
tm "GenericEolColHdrMgr"
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 95,0
optionalChildren [
*286 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *287 (MRCItem
litem &274
pos 0
dimension 20
)
uid 97,0
optionalChildren [
*288 (MRCItem
litem &275
pos 0
dimension 20
uid 98,0
)
*289 (MRCItem
litem &276
pos 1
dimension 23
uid 99,0
)
*290 (MRCItem
litem &277
pos 2
hidden 1
dimension 20
uid 100,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 101,0
optionalChildren [
*291 (MRCItem
litem &278
pos 0
dimension 20
uid 102,0
)
*292 (MRCItem
litem &280
pos 1
dimension 50
uid 103,0
)
*293 (MRCItem
litem &281
pos 2
dimension 100
uid 104,0
)
*294 (MRCItem
litem &282
pos 3
dimension 100
uid 105,0
)
*295 (MRCItem
litem &283
pos 4
dimension 50
uid 106,0
)
*296 (MRCItem
litem &284
pos 5
dimension 50
uid 107,0
)
*297 (MRCItem
litem &285
pos 6
dimension 80
uid 108,0
)
]
)
fixedCol 3
fixedRow 2
name "Ports"
uid 96,0
vaOverrides [
]
)
]
)
uid 82,0
type 1
)
activeModelName "BlockDiag"
)