source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/data_generator/symbol.sb@ 10121

DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
dmPackageRefs [
(DmPackageRef
library "IEEE"
unitName "STD_LOGIC_1164"
itemName "ALL"
)
(DmPackageRef
library "IEEE"
unitName "STD_LOGIC_ARITH"
itemName "ALL"
)
(DmPackageRef
library "IEEE"
unitName "STD_LOGIC_UNSIGNED"
itemName "ALL"
)
(DmPackageRef
library "fact_fad_lib"
unitName "fad_definitions"
)
]
libraryRefs [
"IEEE"
"fact_fad_lib"
]
)
version "24.1"
appVersion "2009.1 (Build 12)"
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commonDM (CommonDM
ldm (LogicalDM
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suid 63,0
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uid 136,0
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tm "RowExpandColHdrMgr"
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tm "NameColHdrMgr"
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*10 (TypeColHdr
tm "TypeColHdrMgr"
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*11 (BoundsColHdr
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*12 (InitColHdr
tm "InitColHdrMgr"
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*13 (EolColHdr
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n "clk"
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posAdd 0
o 1
suid 1,0
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*15 (LogPort
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posAdd 0
o 2
suid 2,0
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uid 111,0
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*16 (LogPort
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uid 113,0
)
*17 (LogPort
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i "\"0\""
)
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)
uid 127,0
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*21 (LogPort
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posAdd 0
o 27
suid 11,0
)
)
uid 129,0
)
*22 (LogPort
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b "(1 downto 0)"
o 25
suid 12,0
)
)
uid 290,0
)
*23 (LogPort
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o 6
suid 16,0
)
)
uid 421,0
)
*24 (LogPort
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decl (Decl
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o 7
suid 17,0
i "'0'"
)
)
uid 423,0
)
*25 (LogPort
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suid 18,0
)
)
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*26 (LogPort
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suid 19,0
)
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i "'1'"
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o 34
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i "(others => '0')"
)
)
uid 701,0
)
*30 (LogPort
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m 1
decl (Decl
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o 37
suid 26,0
i "'0'"
)
)
uid 703,0
)
*31 (LogPort
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o 38
suid 33,0
i "'0'"
)
)
uid 816,0
)
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suid 34,0
)
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)
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o 13
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)
)
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*36 (LogPort
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decl (Decl
n "config_start_cm"
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o 10
suid 40,0
i "'0'"
)
)
uid 970,0
)
*37 (LogPort
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suid 42,0
)
)
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*38 (LogPort
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*39 (LogPort
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)
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*40 (LogPort
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o 21
suid 45,0
)
)
uid 1097,0
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*41 (LogPort
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o 9
suid 46,0
i "'0'"
)
)
uid 1132,0
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o 11
suid 47,0
i "'0'"
)
)
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)
*43 (LogPort
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o 29
suid 48,0
i "'0'"
)
)
uid 1169,0
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*44 (LogPort
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decl (Decl
n "new_config"
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prec "--      s_trigger      : in std_logic;"
preAdd 0
o 28
suid 49,0
)
)
uid 1171,0
)
*45 (LogPort
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suid 50,0
)
)
uid 1211,0
)
*46 (LogPort
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suid 51,0
)
)
uid 1213,0
)
*47 (LogPort
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decl (Decl
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t "std_logic"
o 17
suid 52,0
)
)
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*48 (LogPort
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)
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i "'0'"
)
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)
)
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)
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decl (Decl
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suid 56,0
i "(others => '0')"
)
)
uid 1484,0
)
*52 (LogPort
port (LogicalPort
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decl (Decl
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o 39
suid 57,0
i "'0'"
)
)
uid 1486,0
)
*53 (LogPort
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o 40
suid 58,0
)
)
uid 1488,0
)
*54 (LogPort
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n "drs_srin_write_ready"
t "std_logic"
o 42
suid 59,0
)
)
uid 1490,0
)
*55 (LogPort
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decl (Decl
n "ram_write_ready_ack"
t "std_logic"
prec "-- --"
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posAdd 0
o 8
suid 60,0
)
)
uid 1492,0
)
*56 (LogPort
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m 1
decl (Decl
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o 45
suid 61,0
i "'0'"
)
)
uid 1524,0
)
*57 (LogPort
port (LogicalPort
m 1
decl (Decl
n "drs_readout_ready"
t "std_logic"
prec "-- --
--      drs_dwrite : out std_logic := '1';"
preAdd 0
posAdd 0
o 35
suid 62,0
i "'0'"
)
)
uid 1556,0
)
*58 (LogPort
port (LogicalPort
decl (Decl
n "drs_readout_ready_ack"
t "std_logic"
o 36
suid 63,0
)
)
uid 1588,0
)
]
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uid 157,0
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uid 160,0
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VExpander (VariableExpander
vvMap [
(vvPair
variable "HDLDir"
value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl"
)
(vvPair
variable "HDSDir"
value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator\\symbol.sb.info"
)
(vvPair
variable "SideDataUserDir"
value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator\\symbol.sb.user"
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(vvPair
variable "SourceDir"
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)
(vvPair
variable "appl"
value "HDL Designer"
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(vvPair
variable "arch_name"
value "symbol"
)
(vvPair
variable "config"
value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator"
)
(vvPair
variable "d_logical"
value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator"
)
(vvPair
variable "date"
value "14.01.2011"
)
(vvPair
variable "day"
value "Fr"
)
(vvPair
variable "day_long"
value "Freitag"
)
(vvPair
variable "dd"
value "14"
)
(vvPair
variable "entity_name"
value "data_generator"
)
(vvPair
variable "ext"
value "<TBD>"
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(vvPair
variable "f"
value "symbol.sb"
)
(vvPair
variable "f_logical"
value "symbol.sb"
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(vvPair
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value "symbol"
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(vvPair
variable "group"
value "UNKNOWN"
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(vvPair
variable "host"
value "IHP110"
)
(vvPair
variable "language"
value "VHDL"
)
(vvPair
variable "library"
value "FACT_FAD_lib"
)
(vvPair
variable "library_downstream_HdsLintPlugin"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/designcheck"
)
(vvPair
variable "library_downstream_ISEPARInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
)
(vvPair
variable "library_downstream_ImpactInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/work"
)
(vvPair
variable "library_downstream_PrecisionSynthesisDataPrep"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ps"
)
(vvPair
variable "library_downstream_XSTDataPrep"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
)
(vvPair
variable "mm"
value "01"
)
(vvPair
variable "module_name"
value "data_generator"
)
(vvPair
variable "month"
value "Jan"
)
(vvPair
variable "month_long"
value "Januar"
)
(vvPair
variable "p"
value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator\\symbol.sb"
)
(vvPair
variable "p_logical"
value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator\\symbol.sb"
)
(vvPair
variable "package_name"
value "<Undefined Variable>"
)
(vvPair
variable "project_name"
value "FACT_FAD"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "D:\\modeltech_6.5e\\win32"
)
(vvPair
variable "task_NC-SimPath"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
)
(vvPair
variable "task_QuestaSimPath"
value "<TBD>"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "this_ext"
value "sb"
)
(vvPair
variable "this_file"
value "symbol"
)
(vvPair
variable "this_file_logical"
value "symbol"
)
(vvPair
variable "time"
value "11:17:29"
)
(vvPair
variable "unit"
value "data_generator"
)
(vvPair
variable "user"
value "daqct3"
)
(vvPair
variable "version"
value "2009.1 (Build 12)"
)
(vvPair
variable "view"
value "symbol"
)
(vvPair
variable "year"
value "2011"
)
(vvPair
variable "yy"
value "11"
)
]
)
LanguageMgr "VhdlLangMgr"
uid 134,0
optionalChildren [
*143 (SymbolBody
uid 8,0
optionalChildren [
*144 (CptPort
uid 48,0
ps "OnEdgeStrategy"
shape (Triangle
uid 49,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,1625,37000,2375"
)
tg (CPTG
uid 50,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 51,0
va (VaSet
)
xt "38000,1500,39300,2500"
st "clk"
blo "38000,2300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 52,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,12000,44500,13600"
st "--      led            : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
clk                   : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "clk"
t "std_logic"
prec "--      led            : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');"
preAdd 0
posAdd 0
o 1
suid 1,0
)
)
)
*145 (CptPort
uid 53,0
ps "OnEdgeStrategy"
shape (Triangle
uid 54,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,3625,67750,4375"
)
tg (CPTG
uid 55,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 56,0
va (VaSet
)
xt "59800,3500,66000,4500"
st "data_out : (63:0)"
ju 2
blo "66000,4300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 57,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,13600,35500,14400"
st "data_out              : OUT    std_logic_vector (63 downto 0) ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "data_out"
t "std_logic_vector"
b "(63 downto 0)"
preAdd 0
posAdd 0
o 2
suid 2,0
)
)
)
*146 (CptPort
uid 58,0
ps "OnEdgeStrategy"
shape (Triangle
uid 59,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,2625,67750,3375"
)
tg (CPTG
uid 60,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 61,0
va (VaSet
)
xt "51900,2500,66000,3500"
st "addr_out : (RAM_ADDR_WIDTH-1:0)"
ju 2
blo "66000,3300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 62,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,14400,42500,15200"
st "addr_out              : OUT    std_logic_vector (RAM_ADDR_WIDTH-1 downto 0) ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "addr_out"
t "std_logic_vector"
b "(RAM_ADDR_WIDTH-1 downto 0)"
preAdd 0
posAdd 0
o 3
suid 3,0
)
)
)
*147 (CptPort
uid 73,0
ps "OnEdgeStrategy"
shape (Triangle
uid 74,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,1625,67750,2375"
)
tg (CPTG
uid 75,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 76,0
va (VaSet
)
xt "60200,1500,66000,2500"
st "write_ea : (0:0)"
ju 2
blo "66000,2300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 77,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,15200,38500,16000"
st "write_ea              : OUT    std_logic_vector (0 downto 0) := \"0\" ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "write_ea"
t "std_logic_vector"
b "(0 downto 0)"
preAdd 0
posAdd 0
o 4
suid 6,0
i "\"0\""
)
)
)
*148 (CptPort
uid 78,0
ps "OnEdgeStrategy"
shape (Triangle
uid 391,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,18625,67750,19375"
)
tg (CPTG
uid 80,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 81,0
va (VaSet
)
xt "49700,18500,66000,19500"
st "ram_start_addr : (RAM_ADDR_WIDTH-1:0)"
ju 2
blo "66000,19300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 82,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,16000,42500,16800"
st "ram_start_addr        : IN     std_logic_vector (RAM_ADDR_WIDTH-1 downto 0) ;
"
)
thePort (LogicalPort
decl (Decl
n "ram_start_addr"
t "std_logic_vector"
b "(RAM_ADDR_WIDTH-1 downto 0)"
preAdd 0
posAdd 0
o 5
suid 7,0
)
)
)
*149 (CptPort
uid 88,0
ps "OnEdgeStrategy"
shape (Triangle
uid 89,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,10625,37000,11375"
)
tg (CPTG
uid 90,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 91,0
va (VaSet
)
xt "38000,10500,43900,11500"
st "board_id : (3:0)"
blo "38000,11300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 92,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,34400,35000,35200"
st "board_id              : IN     std_logic_vector (3 downto 0) ;
"
)
thePort (LogicalPort
decl (Decl
n "board_id"
t "std_logic_vector"
b "(3 downto 0)"
preAdd 0
posAdd 0
o 24
suid 9,0
)
)
)
*150 (CptPort
uid 93,0
ps "OnEdgeStrategy"
shape (Triangle
uid 94,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,11625,37000,12375"
)
tg (CPTG
uid 95,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 96,0
va (VaSet
)
xt "38000,11500,44800,12500"
st "trigger_id : (47:0)"
blo "38000,12300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 97,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,36000,35500,36800"
st "trigger_id            : IN     std_logic_vector (47 downto 0) ;
"
)
thePort (LogicalPort
decl (Decl
n "trigger_id"
t "std_logic_vector"
b "(47 downto 0)"
preAdd 0
posAdd 0
o 26
suid 10,0
)
)
)
*151 (CptPort
uid 98,0
ps "OnEdgeStrategy"
shape (Triangle
uid 99,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,6625,37000,7375"
)
tg (CPTG
uid 100,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 101,0
va (VaSet
)
xt "38000,6500,40800,7500"
st "trigger"
blo "38000,7300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 102,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,36800,25500,37600"
st "trigger               : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "trigger"
t "std_logic"
preAdd 0
posAdd 0
o 27
suid 11,0
)
)
)
*152 (CommentText
uid 106,0
ps "EdgeToEdgeStrategy"
shape (Rectangle
uid 107,0
layer 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
lineColor "0,0,32768"
)
xt "37000,2000,52000,6400"
)
oxt "37000,2000,52000,6000"
text (MLText
uid 108,0
va (VaSet
fg "0,0,32768"
)
xt "37200,2200,51100,6200"
st "
-- -- Uncomment the following library declaration if instantiating
-- -- any Xilinx primitives in this code.
-- library UNISIM;
-- use UNISIM.VComponents.all;
"
tm "CommentText"
wrapOption 3
visibleHeight 4400
visibleWidth 15000
)
included 1
excludeCommentLeader 1
)
*153 (CptPort
uid 285,0
ps "OnEdgeStrategy"
shape (Triangle
uid 286,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,12625,37000,13375"
)
tg (CPTG
uid 287,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 288,0
va (VaSet
)
xt "38000,12500,43700,13500"
st "crate_id : (1:0)"
blo "38000,13300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 289,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,35200,35000,36000"
st "crate_id              : IN     std_logic_vector (1 downto 0) ;
"
)
thePort (LogicalPort
decl (Decl
n "crate_id"
t "std_logic_vector"
b "(1 downto 0)"
o 25
suid 12,0
)
)
)
*154 (CptPort
uid 402,0
ps "OnEdgeStrategy"
shape (Triangle
uid 403,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,14625,37000,15375"
)
tg (CPTG
uid 404,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 405,0
va (VaSet
)
xt "38000,14500,43300,15500"
st "ram_write_ea"
blo "38000,15300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 406,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,16800,25500,17600"
st "ram_write_ea          : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "ram_write_ea"
t "std_logic"
o 6
suid 16,0
)
)
)
*155 (CptPort
uid 407,0
ps "OnEdgeStrategy"
shape (Triangle
uid 408,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,20625,67750,21375"
)
tg (CPTG
uid 409,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 410,0
va (VaSet
)
xt "59700,20500,66000,21500"
st "ram_write_ready"
ju 2
blo "66000,21300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 411,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,17600,38500,18400"
st "ram_write_ready       : OUT    std_logic                     := '0' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "ram_write_ready"
t "std_logic"
posAdd 0
o 7
suid 17,0
i "'0'"
)
)
)
*156 (CptPort
uid 412,0
ps "OnEdgeStrategy"
shape (Triangle
uid 413,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,15625,37000,16375"
)
tg (CPTG
uid 414,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 415,0
va (VaSet
)
xt "38000,15500,41000,16500"
st "roi_max"
blo "38000,16300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 416,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,30400,27000,31200"
st "roi_max               : IN     roi_max_type  ;
"
)
thePort (LogicalPort
decl (Decl
n "roi_max"
t "roi_max_type"
o 19
suid 18,0
)
)
)
*157 (CptPort
uid 473,0
ps "OnEdgeStrategy"
shape (Triangle
uid 474,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,16625,37000,17375"
)
tg (CPTG
uid 475,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 476,0
va (VaSet
)
xt "38000,16500,41400,17500"
st "roi_array"
blo "38000,17300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 477,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,29600,28000,30400"
st "roi_array             : IN     roi_array_type  ;
"
)
thePort (LogicalPort
decl (Decl
n "roi_array"
t "roi_array_type"
o 18
suid 19,0
)
)
)
*158 (CptPort
uid 526,0
ps "OnEdgeStrategy"
shape (Triangle
uid 527,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,17625,37000,18375"
)
tg (CPTG
uid 528,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 529,0
va (VaSet
)
xt "38000,17500,47100,18500"
st "package_length : (15:0)"
blo "38000,18300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 530,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,33600,35500,34400"
st "package_length        : IN     std_logic_vector (15 downto 0) ;
"
)
thePort (LogicalPort
decl (Decl
n "package_length"
t "std_logic_vector"
b "(15 downto 0)"
o 23
suid 20,0
)
)
)
*159 (CptPort
uid 637,0
ps "OnEdgeStrategy"
shape (Triangle
uid 638,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,21625,67750,22375"
)
tg (CPTG
uid 639,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 640,0
va (VaSet
)
xt "62800,21500,66000,22500"
st "adc_oeb"
ju 2
blo "66000,22300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 641,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,40800,38500,41600"
st "adc_oeb               : OUT    std_logic                     := '1' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "adc_oeb"
t "std_logic"
o 31
suid 23,0
i "'1'"
)
)
)
*160 (CptPort
uid 676,0
ps "OnEdgeStrategy"
shape (Triangle
uid 677,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,22625,67750,23375"
)
tg (CPTG
uid 678,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 679,0
va (VaSet
)
xt "57500,22500,66000,23500"
st "drs_channel_id : (3:0)"
ju 2
blo "66000,23300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 680,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,43200,44500,44000"
st "drs_channel_id        : OUT    std_logic_vector (3 downto 0) := (others => '0') ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_channel_id"
t "std_logic_vector"
b "(3 downto 0)"
posAdd 0
o 34
suid 25,0
i "(others => '0')"
)
)
)
*161 (CptPort
uid 681,0
ps "OnEdgeStrategy"
shape (Triangle
uid 682,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,23625,67750,24375"
)
tg (CPTG
uid 683,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 684,0
va (VaSet
)
xt "61600,23500,66000,24500"
st "drs_clk_en"
ju 2
blo "66000,24300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 685,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,47200,38500,48800"
st "-- --
drs_clk_en            : OUT    std_logic                     := '0' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_clk_en"
t "std_logic"
prec "-- --"
preAdd 0
posAdd 0
o 37
suid 26,0
i "'0'"
)
)
)
*162 (CptPort
uid 801,0
ps "OnEdgeStrategy"
shape (Triangle
uid 802,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,24625,67750,25375"
)
tg (CPTG
uid 803,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 804,0
va (VaSet
)
xt "59800,24500,66000,25500"
st "drs_read_s_cell"
ju 2
blo "66000,25300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 805,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,48800,38500,50400"
st "-- --
drs_read_s_cell       : OUT    std_logic                     := '0' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_read_s_cell"
t "std_logic"
prec "-- --"
preAdd 0
o 38
suid 33,0
i "'0'"
)
)
)
*163 (CptPort
uid 806,0
ps "OnEdgeStrategy"
shape (Triangle
uid 807,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,20625,37000,21375"
)
tg (CPTG
uid 808,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 809,0
va (VaSet
)
xt "38000,20500,46800,21500"
st "drs_read_s_cell_ready"
blo "38000,21300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 810,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,53600,25500,54400"
st "drs_read_s_cell_ready : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "drs_read_s_cell_ready"
t "std_logic"
o 43
suid 34,0
)
)
)
*164 (CptPort
uid 811,0
ps "OnEdgeStrategy"
shape (Triangle
uid 812,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,21625,37000,22375"
)
tg (CPTG
uid 813,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 814,0
va (VaSet
)
xt "38000,21500,44400,22500"
st "drs_s_cell_array"
blo "38000,22300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 815,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,54400,31500,55200"
st "drs_s_cell_array      : IN     drs_s_cell_array_type  ;
"
)
thePort (LogicalPort
decl (Decl
n "drs_s_cell_array"
t "drs_s_cell_array_type"
o 44
suid 35,0
)
)
)
*165 (CptPort
uid 898,0
ps "OnEdgeStrategy"
shape (Triangle
uid 899,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,22625,37000,23375"
)
tg (CPTG
uid 900,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 901,0
va (VaSet
)
xt "38000,22500,43900,23500"
st "adc_data_array"
blo "38000,23300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 902,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,40000,30500,40800"
st "adc_data_array        : IN     adc_data_array_type  ;
"
)
thePort (LogicalPort
decl (Decl
n "adc_data_array"
t "adc_data_array_type"
o 30
suid 37,0
)
)
)
*166 (CptPort
uid 958,0
ps "OnEdgeStrategy"
shape (Triangle
uid 959,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,23625,37000,24375"
)
tg (CPTG
uid 960,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 961,0
va (VaSet
)
xt "38000,23500,44500,24500"
st "config_ready_cm"
blo "38000,24300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 962,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,25600,25500,26400"
st "config_ready_cm       : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "config_ready_cm"
t "std_logic"
o 13
suid 39,0
)
)
)
*167 (CptPort
uid 963,0
ps "OnEdgeStrategy"
shape (Triangle
uid 964,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,27625,67750,28375"
)
tg (CPTG
uid 965,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 966,0
va (VaSet
)
xt "59800,27500,66000,28500"
st "config_start_cm"
ju 2
blo "66000,28300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 967,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,21600,38500,23200"
st "-- --
config_start_cm       : OUT    std_logic                     := '0' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "config_start_cm"
t "std_logic"
prec "-- --"
preAdd 0
posAdd 0
o 10
suid 40,0
i "'0'"
)
)
)
*168 (CptPort
uid 1048,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1049,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,25625,37000,26375"
)
tg (CPTG
uid 1050,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1051,0
va (VaSet
)
xt "38000,25500,44700,26500"
st "config_ready_mm"
blo "38000,26300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1052,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,24800,25500,25600"
st "config_ready_mm       : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "config_ready_mm"
t "std_logic"
o 12
suid 42,0
)
)
)
*169 (CptPort
uid 1053,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1054,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,26625,37000,27375"
)
tg (CPTG
uid 1055,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1056,0
va (VaSet
)
xt "38000,26500,44500,27500"
st "config_ready_spi"
blo "38000,27300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1057,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,26400,25500,27200"
st "config_ready_spi      : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "config_ready_spi"
t "std_logic"
o 14
suid 43,0
)
)
)
*170 (CptPort
uid 1085,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1086,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,27625,37000,28375"
)
tg (CPTG
uid 1087,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1088,0
va (VaSet
)
xt "38000,27500,43200,28500"
st "sensor_array"
blo "38000,28300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1089,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,31200,29500,32000"
st "sensor_array          : IN     sensor_array_type  ;
"
)
thePort (LogicalPort
decl (Decl
n "sensor_array"
t "sensor_array_type"
o 20
suid 44,0
)
)
)
*171 (CptPort
uid 1090,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1091,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,28625,37000,29375"
)
tg (CPTG
uid 1092,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1093,0
va (VaSet
)
xt "38000,28500,43300,29500"
st "sensor_ready"
blo "38000,29300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1094,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,32000,25500,32800"
st "sensor_ready          : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "sensor_ready"
t "std_logic"
o 21
suid 45,0
)
)
)
*172 (CptPort
uid 1122,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1123,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,28625,67750,29375"
)
tg (CPTG
uid 1124,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1125,0
va (VaSet
)
xt "59600,28500,66000,29500"
st "config_start_mm"
ju 2
blo "66000,29300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1126,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,20000,38500,21600"
st "-- --
config_start_mm       : OUT    std_logic                     := '0' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "config_start_mm"
t "std_logic"
prec "-- --"
preAdd 0
posAdd 0
o 9
suid 46,0
i "'0'"
)
)
)
*173 (CptPort
uid 1127,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1128,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,29625,67750,30375"
)
tg (CPTG
uid 1129,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1130,0
va (VaSet
)
xt "59800,29500,66000,30500"
st "config_start_spi"
ju 2
blo "66000,30300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1131,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,23200,38500,24800"
st "-- --
config_start_spi      : OUT    std_logic                     := '0' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "config_start_spi"
t "std_logic"
prec "-- --"
preAdd 0
o 11
suid 47,0
i "'0'"
)
)
)
*174 (CptPort
uid 1159,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1160,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,30625,67750,31375"
)
tg (CPTG
uid 1161,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1162,0
va (VaSet
)
xt "60400,30500,66000,31500"
st "config_started"
ju 2
blo "66000,31300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1163,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,39200,38500,40000"
st "config_started        : OUT    std_logic                     := '0' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "config_started"
t "std_logic"
o 29
suid 48,0
i "'0'"
)
)
)
*175 (CptPort
uid 1164,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1165,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,29625,37000,30375"
)
tg (CPTG
uid 1166,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1167,0
va (VaSet
)
xt "38000,29500,42600,30500"
st "new_config"
blo "38000,30300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1168,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,37600,25500,39200"
st "--      s_trigger      : in std_logic;
new_config            : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "new_config"
t "std_logic"
prec "--      s_trigger      : in std_logic;"
preAdd 0
o 28
suid 49,0
)
)
)
*176 (CptPort
uid 1196,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1197,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,30625,37000,31375"
)
tg (CPTG
uid 1198,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1199,0
va (VaSet
)
xt "38000,30500,45000,31500"
st "config_started_cm"
blo "38000,31300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1200,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,28000,25500,28800"
st "config_started_cm     : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "config_started_cm"
t "std_logic"
o 16
suid 50,0
)
)
)
*177 (CptPort
uid 1201,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1202,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,31625,37000,32375"
)
tg (CPTG
uid 1203,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1204,0
va (VaSet
)
xt "38000,31500,45200,32500"
st "config_started_mm"
blo "38000,32300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1205,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,27200,25500,28000"
st "config_started_mm     : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "config_started_mm"
t "std_logic"
o 15
suid 51,0
)
)
)
*178 (CptPort
uid 1206,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1207,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,32625,37000,33375"
)
tg (CPTG
uid 1208,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1209,0
va (VaSet
)
xt "38000,32500,45000,33500"
st "config_started_spi"
blo "38000,33300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1210,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,28800,25500,29600"
st "config_started_spi    : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "config_started_spi"
t "std_logic"
o 17
suid 52,0
)
)
)
*179 (CptPort
uid 1240,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1241,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,33625,37000,34375"
)
tg (CPTG
uid 1242,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1243,0
va (VaSet
)
xt "38000,33500,41700,34500"
st "dac_array"
blo "38000,34300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1244,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,32800,28000,33600"
st "dac_array             : IN     dac_array_type  ;
"
)
thePort (LogicalPort
decl (Decl
n "dac_array"
t "dac_array_type"
o 22
suid 53,0
)
)
)
*180 (CptPort
uid 1395,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1396,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,31625,67750,32375"
)
tg (CPTG
uid 1397,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1398,0
va (VaSet
)
xt "61500,31500,66000,32500"
st "adc_clk_en"
ju 2
blo "66000,32300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1399,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,41600,38500,42400"
st "adc_clk_en            : OUT    std_logic                     := '0' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "adc_clk_en"
t "std_logic"
o 32
suid 54,0
i "'0'"
)
)
)
*181 (CptPort
uid 1427,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1428,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,34625,37000,35375"
)
tg (CPTG
uid 1429,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1430,0
va (VaSet
)
xt "38000,34500,43500,35500"
st "adc_otr : (3:0)"
blo "38000,35300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1431,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,42400,35000,43200"
st "adc_otr               : IN     std_logic_vector (3 downto 0) ;
"
)
thePort (LogicalPort
decl (Decl
n "adc_otr"
t "std_logic_vector"
b "(3 downto 0)"
o 33
suid 55,0
)
)
)
*182 (CptPort
uid 1459,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1460,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,32625,67750,33375"
)
tg (CPTG
uid 1461,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1462,0
va (VaSet
)
xt "58000,32500,66000,33500"
st "drs_srin_data : (7:0)"
ju 2
blo "66000,33300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1463,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,52000,44500,52800"
st "drs_srin_data         : OUT    std_logic_vector (7 downto 0) := (others => '0') ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_srin_data"
t "std_logic_vector"
b "(7 downto 0)"
o 41
suid 56,0
i "(others => '0')"
)
)
)
*183 (CptPort
uid 1464,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1465,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,33625,67750,34375"
)
tg (CPTG
uid 1466,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1467,0
va (VaSet
)
xt "59200,33500,66000,34500"
st "drs_srin_write_8b"
ju 2
blo "66000,34300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1468,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,50400,38500,51200"
st "drs_srin_write_8b     : OUT    std_logic                     := '0' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_srin_write_8b"
t "std_logic"
o 39
suid 57,0
i "'0'"
)
)
)
*184 (CptPort
uid 1469,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1470,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,35625,37000,36375"
)
tg (CPTG
uid 1471,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1472,0
va (VaSet
)
xt "38000,35500,45100,36500"
st "drs_srin_write_ack"
blo "38000,36300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1473,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,51200,25500,52000"
st "drs_srin_write_ack    : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "drs_srin_write_ack"
t "std_logic"
o 40
suid 58,0
)
)
)
*185 (CptPort
uid 1474,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1475,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,36625,37000,37375"
)
tg (CPTG
uid 1476,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1477,0
va (VaSet
)
xt "38000,36500,46200,37500"
st "drs_srin_write_ready"
blo "38000,37300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1478,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,52800,25500,53600"
st "drs_srin_write_ready  : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "drs_srin_write_ready"
t "std_logic"
o 42
suid 59,0
)
)
)
*186 (CptPort
uid 1479,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1480,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,37625,37000,38375"
)
tg (CPTG
uid 1481,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1482,0
va (VaSet
)
xt "38000,37500,45800,38500"
st "ram_write_ready_ack"
blo "38000,38300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1483,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,18400,25500,20000"
st "-- --
ram_write_ready_ack   : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "ram_write_ready_ack"
t "std_logic"
prec "-- --"
preAdd 0
posAdd 0
o 8
suid 60,0
)
)
)
*187 (CptPort
uid 1519,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1520,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,34625,67750,35375"
)
tg (CPTG
uid 1521,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1522,0
va (VaSet
)
xt "58500,34500,66000,35500"
st "drs_readout_started"
ju 2
blo "66000,35300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1523,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,55200,37500,56000"
st "drs_readout_started   : OUT    std_logic                     := '0'
"
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_readout_started"
t "std_logic"
o 45
suid 61,0
i "'0'"
)
)
)
*188 (CptPort
uid 1551,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1552,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,35625,67750,36375"
)
tg (CPTG
uid 1553,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1554,0
va (VaSet
)
xt "59000,35500,66000,36500"
st "drs_readout_ready"
ju 2
blo "66000,36300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1555,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,44000,38500,46400"
st "-- --
--      drs_dwrite : out std_logic := '1';
drs_readout_ready     : OUT    std_logic                     := '0' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_readout_ready"
t "std_logic"
prec "-- --
--      drs_dwrite : out std_logic := '1';"
preAdd 0
posAdd 0
o 35
suid 62,0
i "'0'"
)
)
)
*189 (CptPort
uid 1583,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1584,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,38625,37000,39375"
)
tg (CPTG
uid 1585,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1586,0
va (VaSet
)
xt "38000,38500,46900,39500"
st "drs_readout_ready_ack"
blo "38000,39300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1587,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,46400,25500,47200"
st "drs_readout_ready_ack : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "drs_readout_ready_ack"
t "std_logic"
o 36
suid 63,0
)
)
)
]
shape (Rectangle
uid 238,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "37000,1000,67000,40000"
)
oxt "37000,1000,51000,21000"
biTextGroup (BiTextGroup
uid 10,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
first (Text
uid 11,0
va (VaSet
font "Arial,8,1"
)
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