source: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/w5300_modul/symbol.sb @ 10138

Last change on this file since 10138 was 10138, checked in by neise, 9 years ago
File size: 60.3 KB
Line 
1DocumentHdrVersion "1.1"
2Header (DocumentHdr
3version 2
4dmPackageRefs [
5(DmPackageRef
6library "IEEE"
7unitName "STD_LOGIC_1164"
8itemName "ALL"
9)
10(DmPackageRef
11library "IEEE"
12unitName "STD_LOGIC_ARITH"
13itemName "ALL"
14)
15(DmPackageRef
16library "IEEE"
17unitName "STD_LOGIC_UNSIGNED"
18itemName "ALL"
19)
20(DmPackageRef
21library "FACT_FAD_lib"
22unitName "fad_definitions"
23itemName "ALL"
24)
25]
26libraryRefs [
27"IEEE"
28"FACT_FAD_lib"
29]
30)
31version "24.1"
32appVersion "2009.2 (Build 10)"
33model (Symbol
34commonDM (CommonDM
35ldm (LogicalDM
36ordering 1
37suid 50,0
38usingSuid 1
39emptyRow *1 (LEmptyRow
40)
41uid 175,0
42optionalChildren [
43*2 (RefLabelRowHdr
44)
45*3 (TitleRowHdr
46)
47*4 (FilterRowHdr
48)
49*5 (RefLabelColHdr
50tm "RefLabelColHdrMgr"
51)
52*6 (RowExpandColHdr
53tm "RowExpandColHdrMgr"
54)
55*7 (GroupColHdr
56tm "GroupColHdrMgr"
57)
58*8 (NameColHdr
59tm "NameColHdrMgr"
60)
61*9 (ModeColHdr
62tm "ModeColHdrMgr"
63)
64*10 (TypeColHdr
65tm "TypeColHdrMgr"
66)
67*11 (BoundsColHdr
68tm "BoundsColHdrMgr"
69)
70*12 (InitColHdr
71tm "InitColHdrMgr"
72)
73*13 (EolColHdr
74tm "EolColHdrMgr"
75)
76*14 (LogPort
77port (LogicalPort
78decl (Decl
79n "clk"
80t "std_logic"
81preAdd 0
82posAdd 0
83o 1
84suid 1,0
85)
86)
87uid 136,0
88)
89*15 (LogPort
90port (LogicalPort
91m 1
92decl (Decl
93n "wiz_reset"
94t "std_logic"
95preAdd 0
96posAdd 0
97o 2
98suid 2,0
99i "'1'"
100)
101)
102uid 138,0
103)
104*16 (LogPort
105port (LogicalPort
106m 1
107decl (Decl
108n "addr"
109t "std_logic_vector"
110b "(9 DOWNTO 0)"
111preAdd 0
112posAdd 0
113o 3
114suid 3,0
115)
116)
117uid 140,0
118)
119*17 (LogPort
120port (LogicalPort
121m 2
122decl (Decl
123n "data"
124t "std_logic_vector"
125b "(15 DOWNTO 0)"
126preAdd 0
127posAdd 0
128o 4
129suid 4,0
130)
131)
132uid 142,0
133)
134*18 (LogPort
135port (LogicalPort
136m 1
137decl (Decl
138n "cs"
139t "std_logic"
140preAdd 0
141posAdd 0
142o 5
143suid 5,0
144i "'1'"
145)
146)
147uid 144,0
148)
149*19 (LogPort
150port (LogicalPort
151m 1
152decl (Decl
153n "wr"
154t "std_logic"
155preAdd 0
156posAdd 0
157o 6
158suid 6,0
159i "'1'"
160)
161)
162uid 146,0
163)
164*20 (LogPort
165port (LogicalPort
166m 1
167decl (Decl
168n "rd"
169t "std_logic"
170preAdd 0
171posAdd 0
172o 8
173suid 8,0
174i "'1'"
175)
176)
177uid 150,0
178)
179*21 (LogPort
180port (LogicalPort
181decl (Decl
182n "int"
183t "std_logic"
184preAdd 0
185posAdd 0
186o 9
187suid 9,0
188)
189)
190uid 152,0
191)
192*22 (LogPort
193port (LogicalPort
194decl (Decl
195n "write_length"
196t "std_logic_vector"
197b "(16 DOWNTO 0)"
198preAdd 0
199posAdd 0
200o 10
201suid 10,0
202)
203)
204uid 154,0
205)
206*23 (LogPort
207port (LogicalPort
208decl (Decl
209n "ram_start_addr"
210t "std_logic_vector"
211b "(RAM_ADDR_WIDTH-1 DOWNTO 0)"
212preAdd 0
213posAdd 0
214o 11
215suid 11,0
216)
217)
218uid 156,0
219)
220*24 (LogPort
221port (LogicalPort
222decl (Decl
223n "ram_data"
224t "std_logic_vector"
225b "(15 DOWNTO 0)"
226preAdd 0
227posAdd 0
228o 12
229suid 12,0
230)
231)
232uid 158,0
233)
234*25 (LogPort
235port (LogicalPort
236m 1
237decl (Decl
238n "ram_addr"
239t "std_logic_vector"
240b "(RAM_ADDR_WIDTH-1 DOWNTO 0)"
241preAdd 0
242posAdd 0
243o 13
244suid 13,0
245)
246)
247uid 160,0
248)
249*26 (LogPort
250port (LogicalPort
251decl (Decl
252n "data_valid"
253t "std_logic"
254preAdd 0
255posAdd 0
256o 14
257suid 14,0
258)
259)
260uid 162,0
261)
262*27 (LogPort
263port (LogicalPort
264m 1
265decl (Decl
266n "busy"
267t "std_logic"
268preAdd 0
269posAdd 0
270o 16
271suid 15,0
272i "'1'"
273)
274)
275uid 164,0
276)
277*28 (LogPort
278port (LogicalPort
279decl (Decl
280n "write_end_flag"
281t "std_logic"
282o 18
283suid 18,0
284)
285)
286uid 358,0
287)
288*29 (LogPort
289port (LogicalPort
290decl (Decl
291n "write_header_flag"
292t "std_logic"
293o 17
294suid 19,0
295)
296)
297uid 360,0
298)
299*30 (LogPort
300port (LogicalPort
301decl (Decl
302n "fifo_channels"
303t "std_logic_vector"
304b "(3 downto 0)"
305posAdd 0
306o 19
307suid 20,0
308)
309)
310uid 390,0
311)
312*31 (LogPort
313port (LogicalPort
314m 1
315decl (Decl
316n "led"
317t "std_logic_vector"
318b "(7 DOWNTO 0)"
319posAdd 0
320o 7
321suid 22,0
322i "(OTHERS => '0')"
323)
324)
325uid 496,0
326)
327*32 (LogPort
328port (LogicalPort
329m 1
330decl (Decl
331n "s_trigger"
332t "std_logic"
333prec "-- softtrigger:"
334preAdd 0
335o 20
336suid 23,0
337i "'0'"
338)
339)
340uid 526,0
341)
342*33 (LogPort
343port (LogicalPort
344m 1
345decl (Decl
346n "config_addr"
347t "std_logic_vector"
348b "(7 downto 0)"
349prec "-- read/write configRAM"
350preAdd 0
351o 25
352suid 24,0
353)
354)
355uid 581,0
356)
357*34 (LogPort
358port (LogicalPort
359decl (Decl
360n "config_busy"
361t "std_logic"
362preAdd 0
363posAdd 0
364o 31
365suid 25,0
366)
367)
368uid 583,0
369)
370*35 (LogPort
371port (LogicalPort
372m 2
373decl (Decl
374n "config_data"
375t "std_logic_vector"
376b "(15 downto 0)"
377o 26
378suid 26,0
379i "(others => 'Z')"
380)
381)
382uid 585,0
383)
384*36 (LogPort
385port (LogicalPort
386decl (Decl
387n "config_started"
388t "std_logic"
389posAdd 0
390o 24
391suid 27,0
392)
393)
394uid 587,0
395)
396*37 (LogPort
397port (LogicalPort
398m 1
399decl (Decl
400n "config_wr_en"
401t "std_logic"
402o 27
403suid 28,0
404i "'0'"
405)
406)
407uid 589,0
408)
409*38 (LogPort
410port (LogicalPort
411m 1
412decl (Decl
413n "new_config"
414t "std_logic"
415prec "-- FAD configuration signals:
416------------------------------------------------------------------------------
417-- start entire configuration chain"
418preAdd 0
419o 23
420suid 29,0
421i "'0'"
422)
423)
424uid 591,0
425)
426*39 (LogPort
427port (LogicalPort
428m 1
429decl (Decl
430n "config_rd_en"
431t "std_logic"
432posAdd 0
433o 28
434suid 30,0
435i "'0'"
436)
437)
438uid 645,0
439)
440*40 (LogPort
441port (LogicalPort
442m 1
443decl (Decl
444n "denable"
445t "std_logic"
446eolc "-- default domino wave off"
447posAdd 0
448o 36
449suid 31,0
450i "'0'"
451)
452)
453uid 675,0
454)
455*41 (LogPort
456port (LogicalPort
457m 1
458decl (Decl
459n "dwrite_enable"
460t "std_logic"
461eolc "-- default DWRITE low."
462preAdd 0
463posAdd 0
464o 37
465suid 32,0
466i "'0'"
467)
468)
469uid 728,0
470)
471*42 (LogPort
472port (LogicalPort
473m 1
474decl (Decl
475n "data_valid_ack"
476t "std_logic"
477o 15
478suid 34,0
479i "'0'"
480)
481)
482uid 890,0
483)
484*43 (LogPort
485port (LogicalPort
486m 1
487decl (Decl
488n "sclk_enable"
489t "std_logic"
490eolc "-- default DWRITE HIGH."
491posAdd 0
492o 38
493suid 35,0
494i "'1'"
495)
496)
497uid 922,0
498)
499*44 (LogPort
500port (LogicalPort
501m 1
502decl (Decl
503n "ps_direction"
504t "std_logic"
505prec "------------------------------------------------------------------------------
506
507-- ADC CLK generator, is able to shift phase with respect to X_50M
508-- these signals control the behavior of the digital clock manager (DCM)
509------------------------------------------------------------------------------"
510eolc "-- default phase shift upwards"
511preAdd 0
512posAdd 0
513o 40
514suid 36,0
515i "'1'"
516)
517)
518uid 959,0
519)
520*45 (LogPort
521port (LogicalPort
522m 1
523decl (Decl
524n "ps_do_phase_shift"
525t "std_logic"
526eolc "--pulse this to phase shift once"
527preAdd 0
528posAdd 0
529o 41
530suid 37,0
531i "'0'"
532)
533)
534uid 961,0
535)
536*46 (LogPort
537port (LogicalPort
538m 1
539decl (Decl
540n "ps_reset"
541t "std_logic"
542eolc "-- pulse this to reset the variable phase shift"
543posAdd 0
544o 42
545suid 38,0
546i "'0'"
547)
548)
549uid 993,0
550)
551*47 (LogPort
552port (LogicalPort
553m 1
554decl (Decl
555n "srclk_enable"
556t "std_logic"
557eolc "-- default SRCLK on."
558posAdd 0
559o 39
560suid 39,0
561i "'1'"
562)
563)
564uid 1025,0
565)
566*48 (LogPort
567port (LogicalPort
568decl (Decl
569n "config_rw_ack"
570t "std_logic"
571preAdd 0
572posAdd 0
573o 29
574suid 40,0
575)
576)
577uid 1062,0
578)
579*49 (LogPort
580port (LogicalPort
581decl (Decl
582n "config_rw_ready"
583t "std_logic"
584preAdd 0
585posAdd 0
586o 30
587suid 41,0
588)
589)
590uid 1064,0
591)
592*50 (LogPort
593port (LogicalPort
594m 1
595decl (Decl
596n "socks_connected"
597t "std_logic"
598posc "------------------------------------------------------------------------------"
599posAdd 0
600o 44
601suid 42,0
602)
603)
604uid 1101,0
605)
606*51 (LogPort
607port (LogicalPort
608m 1
609decl (Decl
610n "socks_waiting"
611t "std_logic"
612prec "------------------------------------------------------------------------------
613
614-- signals used to control FAD LED bahavior:
615-- one of the three LEDs is used for com-status info
616------------------------------------------------------------------------------"
617preAdd 0
618o 43
619suid 43,0
620)
621)
622uid 1103,0
623)
624*52 (LogPort
625port (LogicalPort
626m 1
627decl (Decl
628n "trigger_enable"
629t "std_logic"
630prec "------------------------------------------------------------------------------
631
632-- user controllable enable signals
633------------------------------------------------------------------------------"
634eolc "-- default triggers are NOT accepted"
635preAdd 0
636posAdd 0
637o 35
638suid 44,0
639i "'0'"
640)
641)
642uid 1135,0
643)
644*53 (LogPort
645port (LogicalPort
646m 1
647decl (Decl
648n "c_trigger_enable"
649t "std_logic"
650o 21
651suid 45,0
652i "'0'"
653)
654)
655uid 1197,0
656)
657*54 (LogPort
658port (LogicalPort
659m 1
660decl (Decl
661n "c_trigger_mult"
662t "std_logic_vector"
663b "(7 DOWNTO 0)"
664eolc "--subject to changes"
665posAdd 0
666o 22
667suid 46,0
668i "(OTHERS => '1')"
669)
670)
671uid 1199,0
672)
673*55 (LogPort
674port (LogicalPort
675decl (Decl
676n "MAC_jumper"
677t "std_logic_vector"
678b "(1 downto 0)"
679prec "------------------------------------------------------------------------------
680
681-- MAC/IP calculation signals:
682------------------------------------------------------------------------------"
683preAdd 0
684o 32
685suid 48,0
686)
687)
688uid 1288,0
689)
690*56 (LogPort
691port (LogicalPort
692decl (Decl
693n "BoardID"
694t "std_logic_vector"
695b "(3 downto 0)"
696o 33
697suid 49,0
698)
699)
700uid 1325,0
701)
702*57 (LogPort
703port (LogicalPort
704decl (Decl
705n "CrateID"
706t "std_logic_vector"
707b "(1 downto 0)"
708posAdd 0
709o 34
710suid 50,0
711)
712)
713uid 1327,0
714)
715]
716)
717pdm (PhysicalDM
718displayShortBounds 1
719editShortBounds 1
720uid 188,0
721optionalChildren [
722*58 (Sheet
723sheetRow (SheetRow
724headerVa (MVa
725cellColor "49152,49152,49152"
726fontColor "0,0,0"
727font "Tahoma,10,0"
728)
729cellVa (MVa
730cellColor "65535,65535,65535"
731fontColor "0,0,0"
732font "Tahoma,10,0"
733)
734groupVa (MVa
735cellColor "39936,56832,65280"
736fontColor "0,0,0"
737font "Tahoma,10,0"
738)
739emptyMRCItem *59 (MRCItem
740litem &1
741pos 3
742dimension 20
743)
744uid 190,0
745optionalChildren [
746*60 (MRCItem
747litem &2
748pos 0
749dimension 20
750uid 191,0
751)
752*61 (MRCItem
753litem &3
754pos 1
755dimension 23
756uid 192,0
757)
758*62 (MRCItem
759litem &4
760pos 2
761hidden 1
762dimension 20
763uid 193,0
764)
765*63 (MRCItem
766litem &14
767pos 0
768dimension 20
769uid 137,0
770)
771*64 (MRCItem
772litem &15
773pos 1
774dimension 20
775uid 139,0
776)
777*65 (MRCItem
778litem &16
779pos 2
780dimension 20
781uid 141,0
782)
783*66 (MRCItem
784litem &17
785pos 3
786dimension 20
787uid 143,0
788)
789*67 (MRCItem
790litem &18
791pos 4
792dimension 20
793uid 145,0
794)
795*68 (MRCItem
796litem &19
797pos 5
798dimension 20
799uid 147,0
800)
801*69 (MRCItem
802litem &20
803pos 6
804dimension 20
805uid 151,0
806)
807*70 (MRCItem
808litem &21
809pos 7
810dimension 20
811uid 153,0
812)
813*71 (MRCItem
814litem &22
815pos 8
816dimension 20
817uid 155,0
818)
819*72 (MRCItem
820litem &23
821pos 9
822dimension 20
823uid 157,0
824)
825*73 (MRCItem
826litem &24
827pos 10
828dimension 20
829uid 159,0
830)
831*74 (MRCItem
832litem &25
833pos 11
834dimension 20
835uid 161,0
836)
837*75 (MRCItem
838litem &26
839pos 12
840dimension 20
841uid 163,0
842)
843*76 (MRCItem
844litem &27
845pos 13
846dimension 20
847uid 165,0
848)
849*77 (MRCItem
850litem &28
851pos 14
852dimension 20
853uid 359,0
854)
855*78 (MRCItem
856litem &29
857pos 15
858dimension 20
859uid 361,0
860)
861*79 (MRCItem
862litem &30
863pos 16
864dimension 20
865uid 391,0
866)
867*80 (MRCItem
868litem &31
869pos 17
870dimension 20
871uid 497,0
872)
873*81 (MRCItem
874litem &32
875pos 18
876dimension 20
877uid 527,0
878)
879*82 (MRCItem
880litem &33
881pos 19
882dimension 20
883uid 582,0
884)
885*83 (MRCItem
886litem &34
887pos 20
888dimension 20
889uid 584,0
890)
891*84 (MRCItem
892litem &35
893pos 21
894dimension 20
895uid 586,0
896)
897*85 (MRCItem
898litem &36
899pos 22
900dimension 20
901uid 588,0
902)
903*86 (MRCItem
904litem &37
905pos 23
906dimension 20
907uid 590,0
908)
909*87 (MRCItem
910litem &38
911pos 24
912dimension 20
913uid 592,0
914)
915*88 (MRCItem
916litem &39
917pos 25
918dimension 20
919uid 646,0
920)
921*89 (MRCItem
922litem &40
923pos 26
924dimension 20
925uid 676,0
926)
927*90 (MRCItem
928litem &41
929pos 27
930dimension 20
931uid 729,0
932)
933*91 (MRCItem
934litem &42
935pos 28
936dimension 20
937uid 891,0
938)
939*92 (MRCItem
940litem &43
941pos 29
942dimension 20
943uid 923,0
944)
945*93 (MRCItem
946litem &44
947pos 30
948dimension 20
949uid 960,0
950)
951*94 (MRCItem
952litem &45
953pos 31
954dimension 20
955uid 962,0
956)
957*95 (MRCItem
958litem &46
959pos 32
960dimension 20
961uid 994,0
962)
963*96 (MRCItem
964litem &47
965pos 33
966dimension 20
967uid 1026,0
968)
969*97 (MRCItem
970litem &48
971pos 34
972dimension 20
973uid 1063,0
974)
975*98 (MRCItem
976litem &49
977pos 35
978dimension 20
979uid 1065,0
980)
981*99 (MRCItem
982litem &50
983pos 36
984dimension 20
985uid 1102,0
986)
987*100 (MRCItem
988litem &51
989pos 37
990dimension 20
991uid 1104,0
992)
993*101 (MRCItem
994litem &52
995pos 38
996dimension 20
997uid 1136,0
998)
999*102 (MRCItem
1000litem &53
1001pos 39
1002dimension 20
1003uid 1198,0
1004)
1005*103 (MRCItem
1006litem &54
1007pos 40
1008dimension 20
1009uid 1200,0
1010)
1011*104 (MRCItem
1012litem &55
1013pos 41
1014dimension 20
1015uid 1289,0
1016)
1017*105 (MRCItem
1018litem &56
1019pos 42
1020dimension 20
1021uid 1326,0
1022)
1023*106 (MRCItem
1024litem &57
1025pos 43
1026dimension 20
1027uid 1328,0
1028)
1029]
1030)
1031sheetCol (SheetCol
1032propVa (MVa
1033cellColor "0,49152,49152"
1034fontColor "0,0,0"
1035font "Tahoma,10,0"
1036textAngle 90
1037)
1038uid 194,0
1039optionalChildren [
1040*107 (MRCItem
1041litem &5
1042pos 0
1043dimension 20
1044uid 195,0
1045)
1046*108 (MRCItem
1047litem &7
1048pos 1
1049dimension 50
1050uid 196,0
1051)
1052*109 (MRCItem
1053litem &8
1054pos 2
1055dimension 100
1056uid 197,0
1057)
1058*110 (MRCItem
1059litem &9
1060pos 3
1061dimension 50
1062uid 198,0
1063)
1064*111 (MRCItem
1065litem &10
1066pos 4
1067dimension 100
1068uid 199,0
1069)
1070*112 (MRCItem
1071litem &11
1072pos 5
1073dimension 100
1074uid 200,0
1075)
1076*113 (MRCItem
1077litem &12
1078pos 6
1079dimension 50
1080uid 201,0
1081)
1082*114 (MRCItem
1083litem &13
1084pos 7
1085dimension 80
1086uid 202,0
1087)
1088]
1089)
1090fixedCol 4
1091fixedRow 2
1092name "Ports"
1093uid 189,0
1094vaOverrides [
1095]
1096)
1097]
1098)
1099uid 174,0
1100)
1101genericsCommonDM (CommonDM
1102ldm (LogicalDM
1103emptyRow *115 (LEmptyRow
1104)
1105uid 204,0
1106optionalChildren [
1107*116 (RefLabelRowHdr
1108)
1109*117 (TitleRowHdr
1110)
1111*118 (FilterRowHdr
1112)
1113*119 (RefLabelColHdr
1114tm "RefLabelColHdrMgr"
1115)
1116*120 (RowExpandColHdr
1117tm "RowExpandColHdrMgr"
1118)
1119*121 (GroupColHdr
1120tm "GroupColHdrMgr"
1121)
1122*122 (NameColHdr
1123tm "GenericNameColHdrMgr"
1124)
1125*123 (TypeColHdr
1126tm "GenericTypeColHdrMgr"
1127)
1128*124 (InitColHdr
1129tm "GenericValueColHdrMgr"
1130)
1131*125 (PragmaColHdr
1132tm "GenericPragmaColHdrMgr"
1133)
1134*126 (EolColHdr
1135tm "GenericEolColHdrMgr"
1136)
1137*127 (LogGeneric
1138generic (GiElement
1139name "RAM_ADDR_WIDTH"
1140type "integer"
1141value "14"
1142)
1143uid 1354,0
1144)
1145]
1146)
1147pdm (PhysicalDM
1148displayShortBounds 1
1149editShortBounds 1
1150uid 216,0
1151optionalChildren [
1152*128 (Sheet
1153sheetRow (SheetRow
1154headerVa (MVa
1155cellColor "49152,49152,49152"
1156fontColor "0,0,0"
1157font "Tahoma,10,0"
1158)
1159cellVa (MVa
1160cellColor "65535,65535,65535"
1161fontColor "0,0,0"
1162font "Tahoma,10,0"
1163)
1164groupVa (MVa
1165cellColor "39936,56832,65280"
1166fontColor "0,0,0"
1167font "Tahoma,10,0"
1168)
1169emptyMRCItem *129 (MRCItem
1170litem &115
1171pos 3
1172dimension 20
1173)
1174uid 218,0
1175optionalChildren [
1176*130 (MRCItem
1177litem &116
1178pos 0
1179dimension 20
1180uid 219,0
1181)
1182*131 (MRCItem
1183litem &117
1184pos 1
1185dimension 23
1186uid 220,0
1187)
1188*132 (MRCItem
1189litem &118
1190pos 2
1191hidden 1
1192dimension 20
1193uid 221,0
1194)
1195*133 (MRCItem
1196litem &127
1197pos 0
1198dimension 20
1199uid 1355,0
1200)
1201]
1202)
1203sheetCol (SheetCol
1204propVa (MVa
1205cellColor "0,49152,49152"
1206fontColor "0,0,0"
1207font "Tahoma,10,0"
1208textAngle 90
1209)
1210uid 222,0
1211optionalChildren [
1212*134 (MRCItem
1213litem &119
1214pos 0
1215dimension 20
1216uid 223,0
1217)
1218*135 (MRCItem
1219litem &121
1220pos 1
1221dimension 50
1222uid 224,0
1223)
1224*136 (MRCItem
1225litem &122
1226pos 2
1227dimension 100
1228uid 225,0
1229)
1230*137 (MRCItem
1231litem &123
1232pos 3
1233dimension 100
1234uid 226,0
1235)
1236*138 (MRCItem
1237litem &124
1238pos 4
1239dimension 50
1240uid 227,0
1241)
1242*139 (MRCItem
1243litem &125
1244pos 5
1245dimension 50
1246uid 228,0
1247)
1248*140 (MRCItem
1249litem &126
1250pos 6
1251dimension 80
1252uid 229,0
1253)
1254]
1255)
1256fixedCol 3
1257fixedRow 2
1258name "Ports"
1259uid 217,0
1260vaOverrides [
1261]
1262)
1263]
1264)
1265uid 203,0
1266type 1
1267)
1268VExpander (VariableExpander
1269vvMap [
1270(vvPair
1271variable "HDLDir"
1272value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl"
1273)
1274(vvPair
1275variable "HDSDir"
1276value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
1277)
1278(vvPair
1279variable "SideDataDesignDir"
1280value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\w5300_modul\\symbol.sb.info"
1281)
1282(vvPair
1283variable "SideDataUserDir"
1284value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\w5300_modul\\symbol.sb.user"
1285)
1286(vvPair
1287variable "SourceDir"
1288value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
1289)
1290(vvPair
1291variable "appl"
1292value "HDL Designer"
1293)
1294(vvPair
1295variable "arch_name"
1296value "symbol"
1297)
1298(vvPair
1299variable "config"
1300value "%(unit)_%(view)_config"
1301)
1302(vvPair
1303variable "d"
1304value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\w5300_modul"
1305)
1306(vvPair
1307variable "d_logical"
1308value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\w5300_modul"
1309)
1310(vvPair
1311variable "date"
1312value "08.02.2011"
1313)
1314(vvPair
1315variable "day"
1316value "Di"
1317)
1318(vvPair
1319variable "day_long"
1320value "Dienstag"
1321)
1322(vvPair
1323variable "dd"
1324value "08"
1325)
1326(vvPair
1327variable "entity_name"
1328value "w5300_modul"
1329)
1330(vvPair
1331variable "ext"
1332value "<TBD>"
1333)
1334(vvPair
1335variable "f"
1336value "symbol.sb"
1337)
1338(vvPair
1339variable "f_logical"
1340value "symbol.sb"
1341)
1342(vvPair
1343variable "f_noext"
1344value "symbol"
1345)
1346(vvPair
1347variable "group"
1348value "UNKNOWN"
1349)
1350(vvPair
1351variable "host"
1352value "E5B-LABOR6"
1353)
1354(vvPair
1355variable "language"
1356value "VHDL"
1357)
1358(vvPair
1359variable "library"
1360value "FACT_FAD_lib"
1361)
1362(vvPair
1363variable "library_downstream_HdsLintPlugin"
1364value "$HDS_PROJECT_DIR/FACT_FAD_lib/designcheck"
1365)
1366(vvPair
1367variable "library_downstream_ISEPARInvoke"
1368value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
1369)
1370(vvPair
1371variable "library_downstream_ImpactInvoke"
1372value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
1373)
1374(vvPair
1375variable "library_downstream_ModelSimCompiler"
1376value "$HDS_PROJECT_DIR/FACT_FAD_lib/work"
1377)
1378(vvPair
1379variable "library_downstream_PrecisionSynthesisDataPrep"
1380value "$HDS_PROJECT_DIR/FACT_FAD_lib/ps"
1381)
1382(vvPair
1383variable "library_downstream_XSTDataPrep"
1384value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
1385)
1386(vvPair
1387variable "mm"
1388value "02"
1389)
1390(vvPair
1391variable "module_name"
1392value "w5300_modul"
1393)
1394(vvPair
1395variable "month"
1396value "Feb"
1397)
1398(vvPair
1399variable "month_long"
1400value "Februar"
1401)
1402(vvPair
1403variable "p"
1404value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\w5300_modul\\symbol.sb"
1405)
1406(vvPair
1407variable "p_logical"
1408value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\w5300_modul\\symbol.sb"
1409)
1410(vvPair
1411variable "package_name"
1412value "<Undefined Variable>"
1413)
1414(vvPair
1415variable "project_name"
1416value "FACT_FAD"
1417)
1418(vvPair
1419variable "series"
1420value "HDL Designer Series"
1421)
1422(vvPair
1423variable "task_DesignCompilerPath"
1424value "<TBD>"
1425)
1426(vvPair
1427variable "task_LeonardoPath"
1428value "<TBD>"
1429)
1430(vvPair
1431variable "task_ModelSimPath"
1432value "C:\\modeltech_6.6a\\win32"
1433)
1434(vvPair
1435variable "task_NC-SimPath"
1436value "<TBD>"
1437)
1438(vvPair
1439variable "task_PrecisionRTLPath"
1440value "<TBD>"
1441)
1442(vvPair
1443variable "task_QuestaSimPath"
1444value "<TBD>"
1445)
1446(vvPair
1447variable "task_VCSPath"
1448value "<TBD>"
1449)
1450(vvPair
1451variable "this_ext"
1452value "sb"
1453)
1454(vvPair
1455variable "this_file"
1456value "symbol"
1457)
1458(vvPair
1459variable "this_file_logical"
1460value "symbol"
1461)
1462(vvPair
1463variable "time"
1464value "10:18:42"
1465)
1466(vvPair
1467variable "unit"
1468value "w5300_modul"
1469)
1470(vvPair
1471variable "user"
1472value "dneise"
1473)
1474(vvPair
1475variable "version"
1476value "2009.2 (Build 10)"
1477)
1478(vvPair
1479variable "view"
1480value "symbol"
1481)
1482(vvPair
1483variable "year"
1484value "2011"
1485)
1486(vvPair
1487variable "yy"
1488value "11"
1489)
1490]
1491)
1492LanguageMgr "VhdlLangMgr"
1493uid 173,0
1494optionalChildren [
1495*141 (SymbolBody
1496uid 8,0
1497optionalChildren [
1498*142 (CptPort
1499uid 48,0
1500ps "OnEdgeStrategy"
1501shape (Triangle
1502uid 49,0
1503ro 90
1504va (VaSet
1505vasetType 1
1506fg "0,65535,0"
1507)
1508xt "42250,3625,43000,4375"
1509)
1510tg (CPTG
1511uid 50,0
1512ps "CptPortTextPlaceStrategy"
1513stg "VerticalLayoutStrategy"
1514f (Text
1515uid 51,0
1516va (VaSet
1517)
1518xt "44000,3500,45300,4500"
1519st "clk"
1520blo "44000,4300"
1521tm "CptPortNameMgr"
1522)
1523)
1524dt (MLText
1525uid 52,0
1526va (VaSet
1527font "Courier New,8,0"
1528)
1529xt "2000,16000,23000,16800"
1530st "clk               : IN     std_logic  ;
1531"
1532)
1533thePort (LogicalPort
1534decl (Decl
1535n "clk"
1536t "std_logic"
1537preAdd 0
1538posAdd 0
1539o 1
1540suid 1,0
1541)
1542)
1543)
1544*143 (CptPort
1545uid 53,0
1546ps "OnEdgeStrategy"
1547shape (Triangle
1548uid 54,0
1549ro 90
1550va (VaSet
1551vasetType 1
1552fg "0,65535,0"
1553)
1554xt "77000,3625,77750,4375"
1555)
1556tg (CPTG
1557uid 55,0
1558ps "CptPortTextPlaceStrategy"
1559stg "RightVerticalLayoutStrategy"
1560f (Text
1561uid 56,0
1562va (VaSet
1563)
1564xt "72400,3500,76000,4500"
1565st "wiz_reset"
1566ju 2
1567blo "76000,4300"
1568tm "CptPortNameMgr"
1569)
1570)
1571dt (MLText
1572uid 57,0
1573va (VaSet
1574font "Courier New,8,0"
1575)
1576xt "2000,16800,37000,17600"
1577st "wiz_reset         : OUT    std_logic                      := '1' ;
1578"
1579)
1580thePort (LogicalPort
1581m 1
1582decl (Decl
1583n "wiz_reset"
1584t "std_logic"
1585preAdd 0
1586posAdd 0
1587o 2
1588suid 2,0
1589i "'1'"
1590)
1591)
1592)
1593*144 (CptPort
1594uid 58,0
1595ps "OnEdgeStrategy"
1596shape (Triangle
1597uid 59,0
1598ro 90
1599va (VaSet
1600vasetType 1
1601fg "0,65535,0"
1602)
1603xt "77000,5625,77750,6375"
1604)
1605tg (CPTG
1606uid 60,0
1607ps "CptPortTextPlaceStrategy"
1608stg "RightVerticalLayoutStrategy"
1609f (Text
1610uid 61,0
1611va (VaSet
1612)
1613xt "74100,5500,76000,6500"
1614st "addr"
1615ju 2
1616blo "76000,6300"
1617tm "CptPortNameMgr"
1618)
1619)
1620dt (MLText
1621uid 62,0
1622va (VaSet
1623font "Courier New,8,0"
1624)
1625xt "2000,17600,33000,18400"
1626st "addr              : OUT    std_logic_vector (9 DOWNTO 0) ;
1627"
1628)
1629thePort (LogicalPort
1630m 1
1631decl (Decl
1632n "addr"
1633t "std_logic_vector"
1634b "(9 DOWNTO 0)"
1635preAdd 0
1636posAdd 0
1637o 3
1638suid 3,0
1639)
1640)
1641)
1642*145 (CptPort
1643uid 63,0
1644ps "OnEdgeStrategy"
1645shape (Diamond
1646uid 64,0
1647ro 90
1648va (VaSet
1649vasetType 1
1650fg "0,65535,0"
1651)
1652xt "77000,7625,77750,8375"
1653)
1654tg (CPTG
1655uid 65,0
1656ps "CptPortTextPlaceStrategy"
1657stg "RightVerticalLayoutStrategy"
1658f (Text
1659uid 66,0
1660va (VaSet
1661)
1662xt "74200,7500,76000,8500"
1663st "data"
1664ju 2
1665blo "76000,8300"
1666tm "CptPortNameMgr"
1667)
1668)
1669dt (MLText
1670uid 67,0
1671va (VaSet
1672font "Courier New,8,0"
1673)
1674xt "2000,18400,33500,19200"
1675st "data              : INOUT  std_logic_vector (15 DOWNTO 0) ;
1676"
1677)
1678thePort (LogicalPort
1679m 2
1680decl (Decl
1681n "data"
1682t "std_logic_vector"
1683b "(15 DOWNTO 0)"
1684preAdd 0
1685posAdd 0
1686o 4
1687suid 4,0
1688)
1689)
1690)
1691*146 (CptPort
1692uid 68,0
1693ps "OnEdgeStrategy"
1694shape (Triangle
1695uid 69,0
1696ro 90
1697va (VaSet
1698vasetType 1
1699fg "0,65535,0"
1700)
1701xt "77000,9625,77750,10375"
1702)
1703tg (CPTG
1704uid 70,0
1705ps "CptPortTextPlaceStrategy"
1706stg "RightVerticalLayoutStrategy"
1707f (Text
1708uid 71,0
1709va (VaSet
1710)
1711xt "74800,9500,76000,10500"
1712st "cs"
1713ju 2
1714blo "76000,10300"
1715tm "CptPortNameMgr"
1716)
1717)
1718dt (MLText
1719uid 72,0
1720va (VaSet
1721font "Courier New,8,0"
1722)
1723xt "2000,19200,37000,20000"
1724st "cs                : OUT    std_logic                      := '1' ;
1725"
1726)
1727thePort (LogicalPort
1728m 1
1729decl (Decl
1730n "cs"
1731t "std_logic"
1732preAdd 0
1733posAdd 0
1734o 5
1735suid 5,0
1736i "'1'"
1737)
1738)
1739)
1740*147 (CptPort
1741uid 73,0
1742ps "OnEdgeStrategy"
1743shape (Triangle
1744uid 74,0
1745ro 90
1746va (VaSet
1747vasetType 1
1748fg "0,65535,0"
1749)
1750xt "77000,11625,77750,12375"
1751)
1752tg (CPTG
1753uid 75,0
1754ps "CptPortTextPlaceStrategy"
1755stg "RightVerticalLayoutStrategy"
1756f (Text
1757uid 76,0
1758va (VaSet
1759)
1760xt "74800,11500,76000,12500"
1761st "wr"
1762ju 2
1763blo "76000,12300"
1764tm "CptPortNameMgr"
1765)
1766)
1767dt (MLText
1768uid 77,0
1769va (VaSet
1770font "Courier New,8,0"
1771)
1772xt "2000,20000,37000,20800"
1773st "wr                : OUT    std_logic                      := '1' ;
1774"
1775)
1776thePort (LogicalPort
1777m 1
1778decl (Decl
1779n "wr"
1780t "std_logic"
1781preAdd 0
1782posAdd 0
1783o 6
1784suid 6,0
1785i "'1'"
1786)
1787)
1788)
1789*148 (CptPort
1790uid 83,0
1791ps "OnEdgeStrategy"
1792shape (Triangle
1793uid 84,0
1794ro 90
1795va (VaSet
1796vasetType 1
1797fg "0,65535,0"
1798)
1799xt "77000,15625,77750,16375"
1800)
1801tg (CPTG
1802uid 85,0
1803ps "CptPortTextPlaceStrategy"
1804stg "RightVerticalLayoutStrategy"
1805f (Text
1806uid 86,0
1807va (VaSet
1808)
1809xt "74900,15500,76000,16500"
1810st "rd"
1811ju 2
1812blo "76000,16300"
1813tm "CptPortNameMgr"
1814)
1815)
1816dt (MLText
1817uid 87,0
1818va (VaSet
1819font "Courier New,8,0"
1820)
1821xt "2000,21600,37000,22400"
1822st "rd                : OUT    std_logic                      := '1' ;
1823"
1824)
1825thePort (LogicalPort
1826m 1
1827decl (Decl
1828n "rd"
1829t "std_logic"
1830preAdd 0
1831posAdd 0
1832o 8
1833suid 8,0
1834i "'1'"
1835)
1836)
1837)
1838*149 (CptPort
1839uid 88,0
1840ps "OnEdgeStrategy"
1841shape (Triangle
1842uid 89,0
1843ro 90
1844va (VaSet
1845vasetType 1
1846fg "0,65535,0"
1847)
1848xt "42250,5625,43000,6375"
1849)
1850tg (CPTG
1851uid 90,0
1852ps "CptPortTextPlaceStrategy"
1853stg "VerticalLayoutStrategy"
1854f (Text
1855uid 91,0
1856va (VaSet
1857)
1858xt "44000,5500,45200,6500"
1859st "int"
1860blo "44000,6300"
1861tm "CptPortNameMgr"
1862)
1863)
1864dt (MLText
1865uid 92,0
1866va (VaSet
1867font "Courier New,8,0"
1868)
1869xt "2000,22400,23000,23200"
1870st "int               : IN     std_logic  ;
1871"
1872)
1873thePort (LogicalPort
1874decl (Decl
1875n "int"
1876t "std_logic"
1877preAdd 0
1878posAdd 0
1879o 9
1880suid 9,0
1881)
1882)
1883)
1884*150 (CptPort
1885uid 93,0
1886ps "OnEdgeStrategy"
1887shape (Triangle
1888uid 94,0
1889ro 90
1890va (VaSet
1891vasetType 1
1892fg "0,65535,0"
1893)
1894xt "42250,7625,43000,8375"
1895)
1896tg (CPTG
1897uid 95,0
1898ps "CptPortTextPlaceStrategy"
1899stg "VerticalLayoutStrategy"
1900f (Text
1901uid 96,0
1902va (VaSet
1903)
1904xt "44000,7500,48900,8500"
1905st "write_length"
1906blo "44000,8300"
1907tm "CptPortNameMgr"
1908)
1909)
1910dt (MLText
1911uid 97,0
1912va (VaSet
1913font "Courier New,8,0"
1914)
1915xt "2000,23200,33500,24000"
1916st "write_length      : IN     std_logic_vector (16 DOWNTO 0) ;
1917"
1918)
1919thePort (LogicalPort
1920decl (Decl
1921n "write_length"
1922t "std_logic_vector"
1923b "(16 DOWNTO 0)"
1924preAdd 0
1925posAdd 0
1926o 10
1927suid 10,0
1928)
1929)
1930)
1931*151 (CptPort
1932uid 98,0
1933ps "OnEdgeStrategy"
1934shape (Triangle
1935uid 99,0
1936ro 90
1937va (VaSet
1938vasetType 1
1939fg "0,65535,0"
1940)
1941xt "42250,9625,43000,10375"
1942)
1943tg (CPTG
1944uid 100,0
1945ps "CptPortTextPlaceStrategy"
1946stg "VerticalLayoutStrategy"
1947f (Text
1948uid 101,0
1949va (VaSet
1950)
1951xt "44000,9500,49900,10500"
1952st "ram_start_addr"
1953blo "44000,10300"
1954tm "CptPortNameMgr"
1955)
1956)
1957dt (MLText
1958uid 102,0
1959va (VaSet
1960font "Courier New,8,0"
1961)
1962xt "2000,24000,40500,24800"
1963st "ram_start_addr    : IN     std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0) ;
1964"
1965)
1966thePort (LogicalPort
1967decl (Decl
1968n "ram_start_addr"
1969t "std_logic_vector"
1970b "(RAM_ADDR_WIDTH-1 DOWNTO 0)"
1971preAdd 0
1972posAdd 0
1973o 11
1974suid 11,0
1975)
1976)
1977)
1978*152 (CptPort
1979uid 103,0
1980ps "OnEdgeStrategy"
1981shape (Triangle
1982uid 104,0
1983ro 90
1984va (VaSet
1985vasetType 1
1986fg "0,65535,0"
1987)
1988xt "42250,11625,43000,12375"
1989)
1990tg (CPTG
1991uid 105,0
1992ps "CptPortTextPlaceStrategy"
1993stg "VerticalLayoutStrategy"
1994f (Text
1995uid 106,0
1996va (VaSet
1997)
1998xt "44000,11500,47500,12500"
1999st "ram_data"
2000blo "44000,12300"
2001tm "CptPortNameMgr"
2002)
2003)
2004dt (MLText
2005uid 107,0
2006va (VaSet
2007font "Courier New,8,0"
2008)
2009xt "2000,24800,33500,25600"
2010st "ram_data          : IN     std_logic_vector (15 DOWNTO 0) ;
2011"
2012)
2013thePort (LogicalPort
2014decl (Decl
2015n "ram_data"
2016t "std_logic_vector"
2017b "(15 DOWNTO 0)"
2018preAdd 0
2019posAdd 0
2020o 12
2021suid 12,0
2022)
2023)
2024)
2025*153 (CptPort
2026uid 108,0
2027ps "OnEdgeStrategy"
2028shape (Triangle
2029uid 109,0
2030ro 90
2031va (VaSet
2032vasetType 1
2033fg "0,65535,0"
2034)
2035xt "77000,17625,77750,18375"
2036)
2037tg (CPTG
2038uid 110,0
2039ps "CptPortTextPlaceStrategy"
2040stg "RightVerticalLayoutStrategy"
2041f (Text
2042uid 111,0
2043va (VaSet
2044)
2045xt "72400,17500,76000,18500"
2046st "ram_addr"
2047ju 2
2048blo "76000,18300"
2049tm "CptPortNameMgr"
2050)
2051)
2052dt (MLText
2053uid 112,0
2054va (VaSet
2055font "Courier New,8,0"
2056)
2057xt "2000,25600,40500,26400"
2058st "ram_addr          : OUT    std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0) ;
2059"
2060)
2061thePort (LogicalPort
2062m 1
2063decl (Decl
2064n "ram_addr"
2065t "std_logic_vector"
2066b "(RAM_ADDR_WIDTH-1 DOWNTO 0)"
2067preAdd 0
2068posAdd 0
2069o 13
2070suid 13,0
2071)
2072)
2073)
2074*154 (CptPort
2075uid 113,0
2076ps "OnEdgeStrategy"
2077shape (Triangle
2078uid 114,0
2079ro 90
2080va (VaSet
2081vasetType 1
2082fg "0,65535,0"
2083)
2084xt "42250,13625,43000,14375"
2085)
2086tg (CPTG
2087uid 115,0
2088ps "CptPortTextPlaceStrategy"
2089stg "VerticalLayoutStrategy"
2090f (Text
2091uid 116,0
2092va (VaSet
2093)
2094xt "44000,13500,48100,14500"
2095st "data_valid"
2096blo "44000,14300"
2097tm "CptPortNameMgr"
2098)
2099)
2100dt (MLText
2101uid 117,0
2102va (VaSet
2103font "Courier New,8,0"
2104)
2105xt "2000,26400,23000,27200"
2106st "data_valid        : IN     std_logic  ;
2107"
2108)
2109thePort (LogicalPort
2110decl (Decl
2111n "data_valid"
2112t "std_logic"
2113preAdd 0
2114posAdd 0
2115o 14
2116suid 14,0
2117)
2118)
2119)
2120*155 (CptPort
2121uid 118,0
2122ps "OnEdgeStrategy"
2123shape (Triangle
2124uid 119,0
2125ro 90
2126va (VaSet
2127vasetType 1
2128fg "0,65535,0"
2129)
2130xt "77000,19625,77750,20375"
2131)
2132tg (CPTG
2133uid 120,0
2134ps "CptPortTextPlaceStrategy"
2135stg "RightVerticalLayoutStrategy"
2136f (Text
2137uid 121,0
2138va (VaSet
2139)
2140xt "74100,19500,76000,20500"
2141st "busy"
2142ju 2
2143blo "76000,20300"
2144tm "CptPortNameMgr"
2145)
2146)
2147dt (MLText
2148uid 122,0
2149va (VaSet
2150font "Courier New,8,0"
2151)
2152xt "2000,28000,37000,28800"
2153st "busy              : OUT    std_logic                      := '1' ;
2154"
2155)
2156thePort (LogicalPort
2157m 1
2158decl (Decl
2159n "busy"
2160t "std_logic"
2161preAdd 0
2162posAdd 0
2163o 16
2164suid 15,0
2165i "'1'"
2166)
2167)
2168)
2169*156 (CommentText
2170uid 299,0
2171ps "EdgeToEdgeStrategy"
2172shape (Rectangle
2173uid 300,0
2174layer 0
2175va (VaSet
2176vasetType 1
2177fg "65280,65280,46080"
2178lineColor "0,0,32768"
2179)
2180xt "0,30800,15000,35800"
2181)
2182oxt "0,0,15000,5000"
2183text (MLText
2184uid 301,0
2185va (VaSet
2186fg "0,0,32768"
2187)
2188xt "200,31000,13900,35000"
2189st "
2190
2191"
2192tm "CommentText"
2193wrapOption 3
2194visibleHeight 4600
2195visibleWidth 14600
2196)
2197included 1
2198excludeCommentLeader 1
2199)
2200*157 (CptPort
2201uid 348,0
2202ps "OnEdgeStrategy"
2203shape (Triangle
2204uid 349,0
2205ro 90
2206va (VaSet
2207vasetType 1
2208fg "0,65535,0"
2209)
2210xt "42250,14625,43000,15375"
2211)
2212tg (CPTG
2213uid 350,0
2214ps "CptPortTextPlaceStrategy"
2215stg "VerticalLayoutStrategy"
2216f (Text
2217uid 351,0
2218va (VaSet
2219)
2220xt "44000,14500,49700,15500"
2221st "write_end_flag"
2222blo "44000,15300"
2223tm "CptPortNameMgr"
2224)
2225)
2226dt (MLText
2227uid 352,0
2228va (VaSet
2229font "Courier New,8,0"
2230)
2231xt "2000,29600,23000,30400"
2232st "write_end_flag    : IN     std_logic  ;
2233"
2234)
2235thePort (LogicalPort
2236decl (Decl
2237n "write_end_flag"
2238t "std_logic"
2239o 18
2240suid 18,0
2241)
2242)
2243)
2244*158 (CptPort
2245uid 353,0
2246ps "OnEdgeStrategy"
2247shape (Triangle
2248uid 354,0
2249ro 90
2250va (VaSet
2251vasetType 1
2252fg "0,65535,0"
2253)
2254xt "42250,15625,43000,16375"
2255)
2256tg (CPTG
2257uid 355,0
2258ps "CptPortTextPlaceStrategy"
2259stg "VerticalLayoutStrategy"
2260f (Text
2261uid 356,0
2262va (VaSet
2263)
2264xt "44000,15500,50800,16500"
2265st "write_header_flag"
2266blo "44000,16300"
2267tm "CptPortNameMgr"
2268)
2269)
2270dt (MLText
2271uid 357,0
2272va (VaSet
2273font "Courier New,8,0"
2274)
2275xt "2000,28800,23000,29600"
2276st "write_header_flag : IN     std_logic  ;
2277"
2278)
2279thePort (LogicalPort
2280decl (Decl
2281n "write_header_flag"
2282t "std_logic"
2283o 17
2284suid 19,0
2285)
2286)
2287)
2288*159 (CptPort
2289uid 385,0
2290ps "OnEdgeStrategy"
2291shape (Triangle
2292uid 386,0
2293ro 90
2294va (VaSet
2295vasetType 1
2296fg "0,65535,0"
2297)
2298xt "42250,16625,43000,17375"
2299)
2300tg (CPTG
2301uid 387,0
2302ps "CptPortTextPlaceStrategy"
2303stg "VerticalLayoutStrategy"
2304f (Text
2305uid 388,0
2306va (VaSet
2307)
2308xt "44000,16500,49200,17500"
2309st "fifo_channels"
2310blo "44000,17300"
2311tm "CptPortNameMgr"
2312)
2313)
2314dt (MLText
2315uid 389,0
2316va (VaSet
2317font "Courier New,8,0"
2318)
2319xt "2000,30400,33000,31200"
2320st "fifo_channels     : IN     std_logic_vector (3 downto 0) ;
2321"
2322)
2323thePort (LogicalPort
2324decl (Decl
2325n "fifo_channels"
2326t "std_logic_vector"
2327b "(3 downto 0)"
2328posAdd 0
2329o 19
2330suid 20,0
2331)
2332)
2333)
2334*160 (CptPort
2335uid 491,0
2336ps "OnEdgeStrategy"
2337shape (Triangle
2338uid 492,0
2339ro 90
2340va (VaSet
2341vasetType 1
2342fg "0,65535,0"
2343)
2344xt "77000,20625,77750,21375"
2345)
2346tg (CPTG
2347uid 493,0
2348ps "CptPortTextPlaceStrategy"
2349stg "RightVerticalLayoutStrategy"
2350f (Text
2351uid 494,0
2352va (VaSet
2353)
2354xt "74600,20500,76000,21500"
2355st "led"
2356ju 2
2357blo "76000,21300"
2358tm "CptPortNameMgr"
2359)
2360)
2361dt (MLText
2362uid 495,0
2363va (VaSet
2364font "Courier New,8,0"
2365)
2366xt "2000,20800,43000,21600"
2367st "led               : OUT    std_logic_vector (7 DOWNTO 0)  := (OTHERS => '0') ;
2368"
2369)
2370thePort (LogicalPort
2371m 1
2372decl (Decl
2373n "led"
2374t "std_logic_vector"
2375b "(7 DOWNTO 0)"
2376posAdd 0
2377o 7
2378suid 22,0
2379i "(OTHERS => '0')"
2380)
2381)
2382)
2383*161 (CptPort
2384uid 521,0
2385ps "OnEdgeStrategy"
2386shape (Triangle
2387uid 522,0
2388ro 90
2389va (VaSet
2390vasetType 1
2391fg "0,65535,0"
2392)
2393xt "77000,21625,77750,22375"
2394)
2395tg (CPTG
2396uid 523,0
2397ps "CptPortTextPlaceStrategy"
2398stg "RightVerticalLayoutStrategy"
2399f (Text
2400uid 524,0
2401va (VaSet
2402)
2403xt "72400,21500,76000,22500"
2404st "s_trigger"
2405ju 2
2406blo "76000,22300"
2407tm "CptPortNameMgr"
2408)
2409)
2410dt (MLText
2411uid 525,0
2412va (VaSet
2413font "Courier New,8,0"
2414)
2415xt "2000,31200,37000,32800"
2416st "-- softtrigger:
2417s_trigger         : OUT    std_logic                      := '0' ;
2418"
2419)
2420thePort (LogicalPort
2421m 1
2422decl (Decl
2423n "s_trigger"
2424t "std_logic"
2425prec "-- softtrigger:"
2426preAdd 0
2427o 20
2428suid 23,0
2429i "'0'"
2430)
2431)
2432)
2433*162 (CptPort
2434uid 551,0
2435ps "OnEdgeStrategy"
2436shape (Triangle
2437uid 552,0
2438ro 90
2439va (VaSet
2440vasetType 1
2441fg "0,65535,0"
2442)
2443xt "77000,22625,77750,23375"
2444)
2445tg (CPTG
2446uid 553,0
2447ps "CptPortTextPlaceStrategy"
2448stg "RightVerticalLayoutStrategy"
2449f (Text
2450uid 554,0
2451va (VaSet
2452)
2453xt "71200,22500,76000,23500"
2454st "config_addr"
2455ju 2
2456blo "76000,23300"
2457tm "CptPortNameMgr"
2458)
2459)
2460dt (MLText
2461uid 555,0
2462va (VaSet
2463font "Courier New,8,0"
2464)
2465xt "2000,38400,33000,40000"
2466st "-- read/write configRAM
2467config_addr       : OUT    std_logic_vector (7 downto 0) ;
2468"
2469)
2470thePort (LogicalPort
2471m 1
2472decl (Decl
2473n "config_addr"
2474t "std_logic_vector"
2475b "(7 downto 0)"
2476prec "-- read/write configRAM"
2477preAdd 0
2478o 25
2479suid 24,0
2480)
2481)
2482)
2483*163 (CptPort
2484uid 556,0
2485ps "OnEdgeStrategy"
2486shape (Triangle
2487uid 557,0
2488ro 90
2489va (VaSet
2490vasetType 1
2491fg "0,65535,0"
2492)
2493xt "42250,17625,43000,18375"
2494)
2495tg (CPTG
2496uid 558,0
2497ps "CptPortTextPlaceStrategy"
2498stg "VerticalLayoutStrategy"
2499f (Text
2500uid 559,0
2501va (VaSet
2502)
2503xt "44000,17500,48800,18500"
2504st "config_busy"
2505blo "44000,18300"
2506tm "CptPortNameMgr"
2507)
2508)
2509dt (MLText
2510uid 560,0
2511va (VaSet
2512font "Courier New,8,0"
2513)
2514xt "2000,44000,23000,44800"
2515st "config_busy       : IN     std_logic  ;
2516"
2517)
2518thePort (LogicalPort
2519decl (Decl
2520n "config_busy"
2521t "std_logic"
2522preAdd 0
2523posAdd 0
2524o 31
2525suid 25,0
2526)
2527)
2528)
2529*164 (CptPort
2530uid 561,0
2531ps "OnEdgeStrategy"
2532shape (Diamond
2533uid 639,0
2534ro 90
2535va (VaSet
2536vasetType 1
2537fg "0,65535,0"
2538)
2539xt "77000,23625,77750,24375"
2540)
2541tg (CPTG
2542uid 563,0
2543ps "CptPortTextPlaceStrategy"
2544stg "RightVerticalLayoutStrategy"
2545f (Text
2546uid 564,0
2547va (VaSet
2548)
2549xt "71300,23500,76000,24500"
2550st "config_data"
2551ju 2
2552blo "76000,24300"
2553tm "CptPortNameMgr"
2554)
2555)
2556dt (MLText
2557uid 565,0
2558va (VaSet
2559font "Courier New,8,0"
2560)
2561xt "2000,40000,43000,40800"
2562st "config_data       : INOUT  std_logic_vector (15 downto 0) := (others => 'Z') ;
2563"
2564)
2565thePort (LogicalPort
2566m 2
2567decl (Decl
2568n "config_data"
2569t "std_logic_vector"
2570b "(15 downto 0)"
2571o 26
2572suid 26,0
2573i "(others => 'Z')"
2574)
2575)
2576)
2577*165 (CptPort
2578uid 566,0
2579ps "OnEdgeStrategy"
2580shape (Triangle
2581uid 567,0
2582ro 90
2583va (VaSet
2584vasetType 1
2585fg "0,65535,0"
2586)
2587xt "42250,18625,43000,19375"
2588)
2589tg (CPTG
2590uid 568,0
2591ps "CptPortTextPlaceStrategy"
2592stg "VerticalLayoutStrategy"
2593f (Text
2594uid 569,0
2595va (VaSet
2596)
2597xt "44000,18500,49600,19500"
2598st "config_started"
2599blo "44000,19300"
2600tm "CptPortNameMgr"
2601)
2602)
2603dt (MLText
2604uid 570,0
2605va (VaSet
2606font "Courier New,8,0"
2607)
2608xt "2000,37600,23000,38400"
2609st "config_started    : IN     std_logic  ;
2610"
2611)
2612thePort (LogicalPort
2613decl (Decl
2614n "config_started"
2615t "std_logic"
2616posAdd 0
2617o 24
2618suid 27,0
2619)
2620)
2621)
2622*166 (CptPort
2623uid 571,0
2624ps "OnEdgeStrategy"
2625shape (Triangle
2626uid 572,0
2627ro 90
2628va (VaSet
2629vasetType 1
2630fg "0,65535,0"
2631)
2632xt "77000,24625,77750,25375"
2633)
2634tg (CPTG
2635uid 573,0
2636ps "CptPortTextPlaceStrategy"
2637stg "RightVerticalLayoutStrategy"
2638f (Text
2639uid 574,0
2640va (VaSet
2641)
2642xt "70700,24500,76000,25500"
2643st "config_wr_en"
2644ju 2
2645blo "76000,25300"
2646tm "CptPortNameMgr"
2647)
2648)
2649dt (MLText
2650uid 575,0
2651va (VaSet
2652font "Courier New,8,0"
2653)
2654xt "2000,40800,37000,41600"
2655st "config_wr_en      : OUT    std_logic                      := '0' ;
2656"
2657)
2658thePort (LogicalPort
2659m 1
2660decl (Decl
2661n "config_wr_en"
2662t "std_logic"
2663o 27
2664suid 28,0
2665i "'0'"
2666)
2667)
2668)
2669*167 (CptPort
2670uid 576,0
2671ps "OnEdgeStrategy"
2672shape (Triangle
2673uid 577,0
2674ro 90
2675va (VaSet
2676vasetType 1
2677fg "0,65535,0"
2678)
2679xt "77000,25625,77750,26375"
2680)
2681tg (CPTG
2682uid 578,0
2683ps "CptPortTextPlaceStrategy"
2684stg "RightVerticalLayoutStrategy"
2685f (Text
2686uid 579,0
2687va (VaSet
2688)
2689xt "71400,25500,76000,26500"
2690st "new_config"
2691ju 2
2692blo "76000,26300"
2693tm "CptPortNameMgr"
2694)
2695)
2696dt (MLText
2697uid 580,0
2698va (VaSet
2699font "Courier New,8,0"
2700)
2701xt "2000,34400,43000,37600"
2702st "-- FAD configuration signals:
2703------------------------------------------------------------------------------
2704-- start entire configuration chain
2705new_config        : OUT    std_logic                      := '0' ;
2706"
2707)
2708thePort (LogicalPort
2709m 1
2710decl (Decl
2711n "new_config"
2712t "std_logic"
2713prec "-- FAD configuration signals:
2714------------------------------------------------------------------------------
2715-- start entire configuration chain"
2716preAdd 0
2717o 23
2718suid 29,0
2719i "'0'"
2720)
2721)
2722)
2723*168 (CptPort
2724uid 640,0
2725ps "OnEdgeStrategy"
2726shape (Triangle
2727uid 641,0
2728ro 90
2729va (VaSet
2730vasetType 1
2731fg "0,65535,0"
2732)
2733xt "77000,26625,77750,27375"
2734)
2735tg (CPTG
2736uid 642,0
2737ps "CptPortTextPlaceStrategy"
2738stg "RightVerticalLayoutStrategy"
2739f (Text
2740uid 643,0
2741va (VaSet
2742)
2743xt "70800,26500,76000,27500"
2744st "config_rd_en"
2745ju 2
2746blo "76000,27300"
2747tm "CptPortNameMgr"
2748)
2749)
2750dt (MLText
2751uid 644,0
2752va (VaSet
2753font "Courier New,8,0"
2754)
2755xt "2000,41600,37000,42400"
2756st "config_rd_en      : OUT    std_logic                      := '0' ;
2757"
2758)
2759thePort (LogicalPort
2760m 1
2761decl (Decl
2762n "config_rd_en"
2763t "std_logic"
2764posAdd 0
2765o 28
2766suid 30,0
2767i "'0'"
2768)
2769)
2770)
2771*169 (CptPort
2772uid 670,0
2773ps "OnEdgeStrategy"
2774shape (Triangle
2775uid 671,0
2776ro 90
2777va (VaSet
2778vasetType 1
2779fg "0,65535,0"
2780)
2781xt "77000,27625,77750,28375"
2782)
2783tg (CPTG
2784uid 672,0
2785ps "CptPortTextPlaceStrategy"
2786stg "RightVerticalLayoutStrategy"
2787f (Text
2788uid 673,0
2789va (VaSet
2790)
2791xt "73000,27500,76000,28500"
2792st "denable"
2793ju 2
2794blo "76000,28300"
2795tm "CptPortNameMgr"
2796)
2797)
2798dt (MLText
2799uid 674,0
2800va (VaSet
2801font "Courier New,8,0"
2802)
2803xt "2000,54400,50500,55200"
2804st "denable           : OUT    std_logic                      := '0' ; -- default domino wave off
2805"
2806)
2807thePort (LogicalPort
2808m 1
2809decl (Decl
2810n "denable"
2811t "std_logic"
2812eolc "-- default domino wave off"
2813posAdd 0
2814o 36
2815suid 31,0
2816i "'0'"
2817)
2818)
2819)
2820*170 (CptPort
2821uid 723,0
2822ps "OnEdgeStrategy"
2823shape (Triangle
2824uid 724,0
2825ro 90
2826va (VaSet
2827vasetType 1
2828fg "0,65535,0"
2829)
2830xt "77000,28625,77750,29375"
2831)
2832tg (CPTG
2833uid 725,0
2834ps "CptPortTextPlaceStrategy"
2835stg "RightVerticalLayoutStrategy"
2836f (Text
2837uid 726,0
2838va (VaSet
2839)
2840xt "70600,28500,76000,29500"
2841st "dwrite_enable"
2842ju 2
2843blo "76000,29300"
2844tm "CptPortNameMgr"
2845)
2846)
2847dt (MLText
2848uid 727,0
2849va (VaSet
2850font "Courier New,8,0"
2851)
2852xt "2000,55200,48500,56000"
2853st "dwrite_enable     : OUT    std_logic                      := '0' ; -- default DWRITE low.
2854"
2855)
2856thePort (LogicalPort
2857m 1
2858decl (Decl
2859n "dwrite_enable"
2860t "std_logic"
2861eolc "-- default DWRITE low."
2862preAdd 0
2863posAdd 0
2864o 37
2865suid 32,0
2866i "'0'"
2867)
2868)
2869)
2870*171 (CptPort
2871uid 885,0
2872ps "OnEdgeStrategy"
2873shape (Triangle
2874uid 886,0
2875ro 90
2876va (VaSet
2877vasetType 1
2878fg "0,65535,0"
2879)
2880xt "77000,29625,77750,30375"
2881)
2882tg (CPTG
2883uid 887,0
2884ps "CptPortTextPlaceStrategy"
2885stg "RightVerticalLayoutStrategy"
2886f (Text
2887uid 888,0
2888va (VaSet
2889)
2890xt "70400,29500,76000,30500"
2891st "data_valid_ack"
2892ju 2
2893blo "76000,30300"
2894tm "CptPortNameMgr"
2895)
2896)
2897dt (MLText
2898uid 889,0
2899va (VaSet
2900font "Courier New,8,0"
2901)
2902xt "2000,27200,37000,28000"
2903st "data_valid_ack    : OUT    std_logic                      := '0' ;
2904"
2905)
2906thePort (LogicalPort
2907m 1
2908decl (Decl
2909n "data_valid_ack"
2910t "std_logic"
2911o 15
2912suid 34,0
2913i "'0'"
2914)
2915)
2916)
2917*172 (CptPort
2918uid 917,0
2919ps "OnEdgeStrategy"
2920shape (Triangle
2921uid 918,0
2922ro 90
2923va (VaSet
2924vasetType 1
2925fg "0,65535,0"
2926)
2927xt "77000,30625,77750,31375"
2928)
2929tg (CPTG
2930uid 919,0
2931ps "CptPortTextPlaceStrategy"
2932stg "RightVerticalLayoutStrategy"
2933f (Text
2934uid 920,0
2935va (VaSet
2936)
2937xt "71300,30500,76000,31500"
2938st "sclk_enable"
2939ju 2
2940blo "76000,31300"
2941tm "CptPortNameMgr"
2942)
2943)
2944dt (MLText
2945uid 921,0
2946va (VaSet
2947font "Courier New,8,0"
2948)
2949xt "2000,56000,49000,56800"
2950st "sclk_enable       : OUT    std_logic                      := '1' ; -- default DWRITE HIGH.
2951"
2952)
2953thePort (LogicalPort
2954m 1
2955decl (Decl
2956n "sclk_enable"
2957t "std_logic"
2958eolc "-- default DWRITE HIGH."
2959posAdd 0
2960o 38
2961suid 35,0
2962i "'1'"
2963)
2964)
2965)
2966*173 (CptPort
2967uid 949,0
2968ps "OnEdgeStrategy"
2969shape (Triangle
2970uid 950,0
2971ro 90
2972va (VaSet
2973vasetType 1
2974fg "0,65535,0"
2975)
2976xt "77000,31625,77750,32375"
2977)
2978tg (CPTG
2979uid 951,0
2980ps "CptPortTextPlaceStrategy"
2981stg "RightVerticalLayoutStrategy"
2982f (Text
2983uid 952,0
2984va (VaSet
2985)
2986xt "71100,31500,76000,32500"
2987st "ps_direction"
2988ju 2
2989blo "76000,32300"
2990tm "CptPortNameMgr"
2991)
2992)
2993dt (MLText
2994uid 953,0
2995va (VaSet
2996font "Courier New,8,0"
2997)
2998xt "2000,57600,52500,62400"
2999st "------------------------------------------------------------------------------
3000
3001-- ADC CLK generator, is able to shift phase with respect to X_50M
3002-- these signals control the behavior of the digital clock manager (DCM)
3003------------------------------------------------------------------------------
3004ps_direction      : OUT    std_logic                      := '1' ; -- default phase shift upwards
3005"
3006)
3007thePort (LogicalPort
3008m 1
3009decl (Decl
3010n "ps_direction"
3011t "std_logic"
3012prec "------------------------------------------------------------------------------
3013
3014-- ADC CLK generator, is able to shift phase with respect to X_50M
3015-- these signals control the behavior of the digital clock manager (DCM)
3016------------------------------------------------------------------------------"
3017eolc "-- default phase shift upwards"
3018preAdd 0
3019posAdd 0
3020o 40
3021suid 36,0
3022i "'1'"
3023)
3024)
3025)
3026*174 (CptPort
3027uid 954,0
3028ps "OnEdgeStrategy"
3029shape (Triangle
3030uid 955,0
3031ro 90
3032va (VaSet
3033vasetType 1
3034fg "0,65535,0"
3035)
3036xt "77000,32625,77750,33375"
3037)
3038tg (CPTG
3039uid 956,0
3040ps "CptPortTextPlaceStrategy"
3041stg "RightVerticalLayoutStrategy"
3042f (Text
3043uid 957,0
3044va (VaSet
3045)
3046xt "69000,32500,76000,33500"
3047st "ps_do_phase_shift"
3048ju 2
3049blo "76000,33300"
3050tm "CptPortNameMgr"
3051)
3052)
3053dt (MLText
3054uid 958,0
3055va (VaSet
3056font "Courier New,8,0"
3057)
3058xt "2000,62400,53500,63200"
3059st "ps_do_phase_shift : OUT    std_logic                      := '0' ; --pulse this to phase shift once
3060"
3061)
3062thePort (LogicalPort
3063m 1
3064decl (Decl
3065n "ps_do_phase_shift"
3066t "std_logic"
3067eolc "--pulse this to phase shift once"
3068preAdd 0
3069posAdd 0
3070o 41
3071suid 37,0
3072i "'0'"
3073)
3074)
3075)
3076*175 (CptPort
3077uid 988,0
3078ps "OnEdgeStrategy"
3079shape (Triangle
3080uid 989,0
3081ro 90
3082va (VaSet
3083vasetType 1
3084fg "0,65535,0"
3085)
3086xt "77000,33625,77750,34375"
3087)
3088tg (CPTG
3089uid 990,0
3090ps "CptPortTextPlaceStrategy"
3091stg "RightVerticalLayoutStrategy"
3092f (Text
3093uid 991,0
3094va (VaSet
3095)
3096xt "72700,33500,76000,34500"
3097st "ps_reset"
3098ju 2
3099blo "76000,34300"
3100tm "CptPortNameMgr"
3101)
3102)
3103dt (MLText
3104uid 992,0
3105va (VaSet
3106font "Courier New,8,0"
3107)
3108xt "2000,63200,61000,64000"
3109st "ps_reset          : OUT    std_logic                      := '0' ; -- pulse this to reset the variable phase shift
3110"
3111)
3112thePort (LogicalPort
3113m 1
3114decl (Decl
3115n "ps_reset"
3116t "std_logic"
3117eolc "-- pulse this to reset the variable phase shift"
3118posAdd 0
3119o 42
3120suid 38,0
3121i "'0'"
3122)
3123)
3124)
3125*176 (CptPort
3126uid 1020,0
3127ps "OnEdgeStrategy"
3128shape (Triangle
3129uid 1021,0
3130ro 90
3131va (VaSet
3132vasetType 1
3133fg "0,65535,0"
3134)
3135xt "77000,34625,77750,35375"
3136)
3137tg (CPTG
3138uid 1022,0
3139ps "CptPortTextPlaceStrategy"
3140stg "RightVerticalLayoutStrategy"
3141f (Text
3142uid 1023,0
3143va (VaSet
3144)
3145xt "71000,34500,76000,35500"
3146st "srclk_enable"
3147ju 2
3148blo "76000,35300"
3149tm "CptPortNameMgr"
3150)
3151)
3152dt (MLText
3153uid 1024,0
3154va (VaSet
3155font "Courier New,8,0"
3156)
3157xt "2000,56800,47500,57600"
3158st "srclk_enable      : OUT    std_logic                      := '1' ; -- default SRCLK on.
3159"
3160)
3161thePort (LogicalPort
3162m 1
3163decl (Decl
3164n "srclk_enable"
3165t "std_logic"
3166eolc "-- default SRCLK on."
3167posAdd 0
3168o 39
3169suid 39,0
3170i "'1'"
3171)
3172)
3173)
3174*177 (CptPort
3175uid 1052,0
3176ps "OnEdgeStrategy"
3177shape (Triangle
3178uid 1053,0
3179ro 90
3180va (VaSet
3181vasetType 1
3182fg "0,65535,0"
3183)
3184xt "42250,19625,43000,20375"
3185)
3186tg (CPTG
3187uid 1054,0
3188ps "CptPortTextPlaceStrategy"
3189stg "VerticalLayoutStrategy"
3190f (Text
3191uid 1055,0
3192va (VaSet
3193)
3194xt "44000,19500,49600,20500"
3195st "config_rw_ack"
3196blo "44000,20300"
3197tm "CptPortNameMgr"
3198)
3199)
3200dt (MLText
3201uid 1056,0
3202va (VaSet
3203font "Courier New,8,0"
3204)
3205xt "2000,42400,23000,43200"
3206st "config_rw_ack     : IN     std_logic  ;
3207"
3208)
3209thePort (LogicalPort
3210decl (Decl
3211n "config_rw_ack"
3212t "std_logic"
3213preAdd 0
3214posAdd 0
3215o 29
3216suid 40,0
3217)
3218)
3219)
3220*178 (CptPort
3221uid 1057,0
3222ps "OnEdgeStrategy"
3223shape (Triangle
3224uid 1058,0
3225ro 90
3226va (VaSet
3227vasetType 1
3228fg "0,65535,0"
3229)
3230xt "42250,20625,43000,21375"
3231)
3232tg (CPTG
3233uid 1059,0
3234ps "CptPortTextPlaceStrategy"
3235stg "VerticalLayoutStrategy"
3236f (Text
3237uid 1060,0
3238va (VaSet
3239)
3240xt "44000,20500,50300,21500"
3241st "config_rw_ready"
3242blo "44000,21300"
3243tm "CptPortNameMgr"
3244)
3245)
3246dt (MLText
3247uid 1061,0
3248va (VaSet
3249font "Courier New,8,0"
3250)
3251xt "2000,43200,23000,44000"
3252st "config_rw_ready   : IN     std_logic  ;
3253"
3254)
3255thePort (LogicalPort
3256decl (Decl
3257n "config_rw_ready"
3258t "std_logic"
3259preAdd 0
3260posAdd 0
3261o 30
3262suid 41,0
3263)
3264)
3265)
3266*179 (CptPort
3267uid 1091,0
3268ps "OnEdgeStrategy"
3269shape (Triangle
3270uid 1092,0
3271ro 90
3272va (VaSet
3273vasetType 1
3274fg "0,65535,0"
3275)
3276xt "77000,35625,77750,36375"
3277)
3278tg (CPTG
3279uid 1093,0
3280ps "CptPortTextPlaceStrategy"
3281stg "RightVerticalLayoutStrategy"
3282f (Text
3283uid 1094,0
3284va (VaSet
3285)
3286xt "69500,35500,76000,36500"
3287st "socks_connected"
3288ju 2
3289blo "76000,36300"
3290tm "CptPortNameMgr"
3291)
3292)
3293dt (MLText
3294uid 1095,0
3295va (VaSet
3296font "Courier New,8,0"
3297)
3298xt "2000,68800,43000,70400"
3299st "socks_connected   : OUT    std_logic
3300------------------------------------------------------------------------------
3301"
3302)
3303thePort (LogicalPort
3304m 1
3305decl (Decl
3306n "socks_connected"
3307t "std_logic"
3308posc "------------------------------------------------------------------------------"
3309posAdd 0
3310o 44
3311suid 42,0
3312)
3313)
3314)
3315*180 (CptPort
3316uid 1096,0
3317ps "OnEdgeStrategy"
3318shape (Triangle
3319uid 1097,0
3320ro 90
3321va (VaSet
3322vasetType 1
3323fg "0,65535,0"
3324)
3325xt "77000,36625,77750,37375"
3326)
3327tg (CPTG
3328uid 1098,0
3329ps "CptPortTextPlaceStrategy"
3330stg "RightVerticalLayoutStrategy"
3331f (Text
3332uid 1099,0
3333va (VaSet
3334)
3335xt "70500,36500,76000,37500"
3336st "socks_waiting"
3337ju 2
3338blo "76000,37300"
3339tm "CptPortNameMgr"
3340)
3341)
3342dt (MLText
3343uid 1100,0
3344va (VaSet
3345font "Courier New,8,0"
3346)
3347xt "2000,64000,43000,68800"
3348st "------------------------------------------------------------------------------
3349
3350-- signals used to control FAD LED bahavior:
3351-- one of the three LEDs is used for com-status info
3352------------------------------------------------------------------------------
3353socks_waiting     : OUT    std_logic  ;
3354"
3355)
3356thePort (LogicalPort
3357m 1
3358decl (Decl
3359n "socks_waiting"
3360t "std_logic"
3361prec "------------------------------------------------------------------------------
3362
3363-- signals used to control FAD LED bahavior:
3364-- one of the three LEDs is used for com-status info
3365------------------------------------------------------------------------------"
3366preAdd 0
3367o 43
3368suid 43,0
3369)
3370)
3371)
3372*181 (CptPort
3373uid 1130,0
3374ps "OnEdgeStrategy"
3375shape (Triangle
3376uid 1131,0
3377ro 90
3378va (VaSet
3379vasetType 1
3380fg "0,65535,0"
3381)
3382xt "77000,37625,77750,38375"
3383)
3384tg (CPTG
3385uid 1132,0
3386ps "CptPortTextPlaceStrategy"
3387stg "RightVerticalLayoutStrategy"
3388f (Text
3389uid 1133,0
3390va (VaSet
3391)
3392xt "70200,37500,76000,38500"
3393st "trigger_enable"
3394ju 2
3395blo "76000,38300"
3396tm "CptPortNameMgr"
3397)
3398)
3399dt (MLText
3400uid 1134,0
3401va (VaSet
3402font "Courier New,8,0"
3403)
3404xt "2000,50400,55500,54400"
3405st "------------------------------------------------------------------------------
3406
3407-- user controllable enable signals
3408------------------------------------------------------------------------------
3409trigger_enable    : OUT    std_logic                      := '0' ; -- default triggers are NOT accepted
3410"
3411)
3412thePort (LogicalPort
3413m 1
3414decl (Decl
3415n "trigger_enable"
3416t "std_logic"
3417prec "------------------------------------------------------------------------------
3418
3419-- user controllable enable signals
3420------------------------------------------------------------------------------"
3421eolc "-- default triggers are NOT accepted"
3422preAdd 0
3423posAdd 0
3424o 35
3425suid 44,0
3426i "'0'"
3427)
3428)
3429)
3430*182 (CptPort
3431uid 1187,0
3432ps "OnEdgeStrategy"
3433shape (Triangle
3434uid 1188,0
3435ro 90
3436va (VaSet
3437vasetType 1
3438fg "0,65535,0"
3439)
3440xt "77000,38625,77750,39375"
3441)
3442tg (CPTG
3443uid 1189,0
3444ps "CptPortTextPlaceStrategy"
3445stg "RightVerticalLayoutStrategy"
3446f (Text
3447uid 1190,0
3448va (VaSet
3449)
3450xt "69400,38500,76000,39500"
3451st "c_trigger_enable"
3452ju 2
3453blo "76000,39300"
3454tm "CptPortNameMgr"
3455)
3456)
3457dt (MLText
3458uid 1191,0
3459va (VaSet
3460font "Courier New,8,0"
3461)
3462xt "2000,32800,37000,33600"
3463st "c_trigger_enable  : OUT    std_logic                      := '0' ;
3464"
3465)
3466thePort (LogicalPort
3467m 1
3468decl (Decl
3469n "c_trigger_enable"
3470t "std_logic"
3471o 21
3472suid 45,0
3473i "'0'"
3474)
3475)
3476)
3477*183 (CptPort
3478uid 1192,0
3479ps "OnEdgeStrategy"
3480shape (Triangle
3481uid 1193,0
3482ro 90
3483va (VaSet
3484vasetType 1
3485fg "0,65535,0"
3486)
3487xt "77000,39625,77750,40375"
3488)
3489tg (CPTG
3490uid 1194,0
3491ps "CptPortTextPlaceStrategy"
3492stg "RightVerticalLayoutStrategy"
3493f (Text
3494uid 1195,0
3495va (VaSet
3496)
3497xt "70200,39500,76000,40500"
3498st "c_trigger_mult"
3499ju 2
3500blo "76000,40300"
3501tm "CptPortNameMgr"
3502)
3503)
3504dt (MLText
3505uid 1196,0
3506va (VaSet
3507font "Courier New,8,0"
3508)
3509xt "2000,33600,53500,34400"
3510st "c_trigger_mult    : OUT    std_logic_vector (7 DOWNTO 0)  := (OTHERS => '1') ; --subject to changes
3511"
3512)
3513thePort (LogicalPort
3514m 1
3515decl (Decl
3516n "c_trigger_mult"
3517t "std_logic_vector"
3518b "(7 DOWNTO 0)"
3519eolc "--subject to changes"
3520posAdd 0
3521o 22
3522suid 46,0
3523i "(OTHERS => '1')"
3524)
3525)
3526)
3527*184 (CptPort
3528uid 1283,0
3529ps "OnEdgeStrategy"
3530shape (Triangle
3531uid 1284,0
3532ro 90
3533va (VaSet
3534vasetType 1
3535fg "0,65535,0"
3536)
3537xt "42250,21625,43000,22375"
3538)
3539tg (CPTG
3540uid 1285,0
3541ps "CptPortTextPlaceStrategy"
3542stg "VerticalLayoutStrategy"
3543f (Text
3544uid 1286,0
3545va (VaSet
3546)
3547xt "44000,21500,49300,22500"
3548st "MAC_jumper"
3549blo "44000,22300"
3550tm "CptPortNameMgr"
3551)
3552)
3553dt (MLText
3554uid 1287,0
3555va (VaSet
3556font "Courier New,8,0"
3557)
3558xt "2000,44800,43000,48800"
3559st "------------------------------------------------------------------------------
3560
3561-- MAC/IP calculation signals:
3562------------------------------------------------------------------------------
3563MAC_jumper        : IN     std_logic_vector (1 downto 0) ;
3564"
3565)
3566thePort (LogicalPort
3567decl (Decl
3568n "MAC_jumper"
3569t "std_logic_vector"
3570b "(1 downto 0)"
3571prec "------------------------------------------------------------------------------
3572
3573-- MAC/IP calculation signals:
3574------------------------------------------------------------------------------"
3575preAdd 0
3576o 32
3577suid 48,0
3578)
3579)
3580)
3581*185 (CptPort
3582uid 1315,0
3583ps "OnEdgeStrategy"
3584shape (Triangle
3585uid 1316,0
3586ro 90
3587va (VaSet
3588vasetType 1
3589fg "0,65535,0"
3590)
3591xt "42250,22625,43000,23375"
3592)
3593tg (CPTG
3594uid 1317,0
3595ps "CptPortTextPlaceStrategy"
3596stg "VerticalLayoutStrategy"
3597f (Text
3598uid 1318,0
3599va (VaSet
3600)
3601xt "44000,22500,47200,23500"
3602st "BoardID"
3603blo "44000,23300"
3604tm "CptPortNameMgr"
3605)
3606)
3607dt (MLText
3608uid 1319,0
3609va (VaSet
3610font "Courier New,8,0"
3611)
3612xt "2000,48800,33000,49600"
3613st "BoardID           : IN     std_logic_vector (3 downto 0) ;
3614"
3615)
3616thePort (LogicalPort
3617decl (Decl
3618n "BoardID"
3619t "std_logic_vector"
3620b "(3 downto 0)"
3621o 33
3622suid 49,0
3623)
3624)
3625)
3626*186 (CptPort
3627uid 1320,0
3628ps "OnEdgeStrategy"
3629shape (Triangle
3630uid 1321,0
3631ro 90
3632va (VaSet
3633vasetType 1
3634fg "0,65535,0"
3635)
3636xt "42250,23625,43000,24375"
3637)
3638tg (CPTG
3639uid 1322,0
3640ps "CptPortTextPlaceStrategy"
3641stg "VerticalLayoutStrategy"
3642f (Text
3643uid 1323,0
3644va (VaSet
3645)
3646xt "44000,23500,47100,24500"
3647st "CrateID"
3648blo "44000,24300"
3649tm "CptPortNameMgr"
3650)
3651)
3652dt (MLText
3653uid 1324,0
3654va (VaSet
3655font "Courier New,8,0"
3656)
3657xt "2000,49600,33000,50400"
3658st "CrateID           : IN     std_logic_vector (1 downto 0) ;
3659"
3660)
3661thePort (LogicalPort
3662decl (Decl
3663n "CrateID"
3664t "std_logic_vector"
3665b "(1 downto 0)"
3666posAdd 0
3667o 34
3668suid 50,0
3669)
3670)
3671)
3672]
3673shape (Rectangle
3674uid 9,0
3675va (VaSet
3676vasetType 1
3677fg "0,65535,0"
3678lineColor "0,32896,0"
3679lineWidth 2
3680)
3681xt "43000,2000,77000,41000"
3682)
3683oxt "43000,2000,56000,22000"
3684biTextGroup (BiTextGroup
3685uid 10,0
3686ps "CenterOffsetStrategy"
3687stg "VerticalLayoutStrategy"
3688first (Text
3689uid 11,0
3690va (VaSet
3691font "Arial,8,1"
3692)
3693xt "47700,11000,53900,12000"
3694st "FACT_FAD_lib"
3695blo "47700,11800"
3696)
3697second (Text
3698uid 12,0
3699va (VaSet
3700font "Arial,8,1"
3701)
3702xt "47700,12000,53400,13000"
3703st "w5300_modul"
3704blo "47700,12800"
3705)
3706)
3707gi *187 (GenericInterface
3708uid 13,0
3709ps "CenterOffsetStrategy"
3710matrix (Matrix
3711uid 14,0
3712text (MLText
3713uid 15,0
3714va (VaSet
3715font "Courier New,8,0"
3716)
3717xt "43000,200,58000,2600"
3718st "Generic Declarations
3719
3720RAM_ADDR_WIDTH integer 14 
3721"
3722)
3723header "Generic Declarations"
3724showHdrWhenContentsEmpty 1
3725)
3726elements [
3727(GiElement
3728name "RAM_ADDR_WIDTH"
3729type "integer"
3730value "14"
3731)
3732]
3733)
3734portInstanceVisAsIs 1
3735portInstanceVis (PortSigDisplay
3736sIVOD 1
3737)
3738portVis (PortSigDisplay
3739sTC 0
3740sF 0
3741)
3742)
3743*188 (Grouping
3744uid 16,0
3745optionalChildren [
3746*189 (CommentText
3747uid 18,0
3748shape (Rectangle
3749uid 19,0
3750sl 0
3751va (VaSet
3752vasetType 1
3753fg "65280,65280,46080"
3754)
3755xt "47000,30000,64000,31000"
3756)
3757oxt "18000,70000,35000,71000"
3758text (MLText
3759uid 20,0
3760va (VaSet
3761fg "0,0,32768"
3762bg "0,0,32768"
3763)
3764xt "47200,30000,56700,31000"
3765st "
3766by %user on %dd %month %year
3767"
3768tm "CommentText"
3769wrapOption 3
3770visibleHeight 1000
3771visibleWidth 17000
3772)
3773position 1
3774ignorePrefs 1
3775titleBlock 1
3776)
3777*190 (CommentText
3778uid 21,0
3779shape (Rectangle
3780uid 22,0
3781sl 0
3782va (VaSet
3783vasetType 1
3784fg "65280,65280,46080"
3785)
3786xt "64000,26000,68000,27000"
3787)
3788oxt "35000,66000,39000,67000"
3789text (MLText
3790uid 23,0
3791va (VaSet
3792fg "0,0,32768"
3793bg "0,0,32768"
3794)
3795xt "64200,26000,67200,27000"
3796st "
3797Project:
3798"
3799tm "CommentText"
3800wrapOption 3
3801visibleHeight 1000
3802visibleWidth 4000
3803)
3804position 1
3805ignorePrefs 1
3806titleBlock 1
3807)
3808*191 (CommentText
3809uid 24,0
3810shape (Rectangle
3811uid 25,0
3812sl 0
3813va (VaSet
3814vasetType 1
3815fg "65280,65280,46080"
3816)
3817xt "47000,28000,64000,29000"
3818)
3819oxt "18000,68000,35000,69000"
3820text (MLText
3821uid 26,0
3822va (VaSet
3823fg "0,0,32768"
3824bg "0,0,32768"
3825)
3826xt "47200,28000,57200,29000"
3827st "
3828<enter diagram title here>
3829"
3830tm "CommentText"
3831wrapOption 3
3832visibleHeight 1000
3833visibleWidth 17000
3834)
3835position 1
3836ignorePrefs 1
3837titleBlock 1
3838)
3839*192 (CommentText
3840uid 27,0
3841shape (Rectangle
3842uid 28,0
3843sl 0
3844va (VaSet
3845vasetType 1
3846fg "65280,65280,46080"
3847)
3848xt "43000,28000,47000,29000"
3849)
3850oxt "14000,68000,18000,69000"
3851text (MLText
3852uid 29,0
3853va (VaSet
3854fg "0,0,32768"
3855bg "0,0,32768"
3856)
3857xt "43200,28000,45300,29000"
3858st "
3859Title:
3860"
3861tm "CommentText"
3862wrapOption 3
3863visibleHeight 1000
3864visibleWidth 4000
3865)
3866position 1
3867ignorePrefs 1
3868titleBlock 1
3869)
3870*193 (CommentText
3871uid 30,0
3872shape (Rectangle
3873uid 31,0
3874sl 0
3875va (VaSet
3876vasetType 1
3877fg "65280,65280,46080"
3878)
3879xt "64000,27000,84000,31000"
3880)
3881oxt "35000,67000,55000,71000"
3882text (MLText
3883uid 32,0
3884va (VaSet
3885fg "0,0,32768"
3886bg "0,0,32768"
3887)
3888xt "64200,27200,73400,28200"
3889st "
3890<enter comments here>
3891"
3892tm "CommentText"
3893wrapOption 3
3894visibleHeight 4000
3895visibleWidth 20000
3896)
3897ignorePrefs 1
3898titleBlock 1
3899)
3900*194 (CommentText
3901uid 33,0
3902shape (Rectangle
3903uid 34,0
3904sl 0
3905va (VaSet
3906vasetType 1
3907fg "65280,65280,46080"
3908)
3909xt "68000,26000,84000,27000"
3910)
3911oxt "39000,66000,55000,67000"
3912text (MLText
3913uid 35,0
3914va (VaSet
3915fg "0,0,32768"
3916bg "0,0,32768"
3917)
3918xt "68200,26000,72700,27000"
3919st "
3920%project_name
3921"
3922tm "CommentText"
3923wrapOption 3
3924visibleHeight 1000
3925visibleWidth 16000
3926)
3927position 1
3928ignorePrefs 1
3929titleBlock 1
3930)
3931*195 (CommentText
3932uid 36,0
3933shape (Rectangle
3934uid 37,0
3935sl 0
3936va (VaSet
3937vasetType 1
3938fg "65280,65280,46080"
3939)
3940xt "43000,26000,64000,28000"
3941)
3942oxt "14000,66000,35000,68000"
3943text (MLText
3944uid 38,0
3945va (VaSet
3946fg "32768,0,0"
3947)
3948xt "50150,26500,56850,27500"
3949st "
3950<company name>
3951"
3952ju 0
3953tm "CommentText"
3954wrapOption 3
3955visibleHeight 2000
3956visibleWidth 21000
3957)
3958position 1
3959ignorePrefs 1
3960titleBlock 1
3961)
3962*196 (CommentText
3963uid 39,0
3964shape (Rectangle
3965uid 40,0
3966sl 0
3967va (VaSet
3968vasetType 1
3969fg "65280,65280,46080"
3970)
3971xt "43000,29000,47000,30000"
3972)
3973oxt "14000,69000,18000,70000"
3974text (MLText
3975uid 41,0
3976va (VaSet
3977fg "0,0,32768"
3978bg "0,0,32768"
3979)
3980xt "43200,29000,45300,30000"
3981st "
3982Path:
3983"
3984tm "CommentText"
3985wrapOption 3
3986visibleHeight 1000
3987visibleWidth 4000
3988)
3989position 1
3990ignorePrefs 1
3991titleBlock 1
3992)
3993*197 (CommentText
3994uid 42,0
3995shape (Rectangle
3996uid 43,0
3997sl 0
3998va (VaSet
3999vasetType 1
4000fg "65280,65280,46080"
4001)
4002xt "43000,30000,47000,31000"
4003)
4004oxt "14000,70000,18000,71000"
4005text (MLText
4006uid 44,0
4007va (VaSet
4008fg "0,0,32768"
4009bg "0,0,32768"
4010)
4011xt "43200,30000,45900,31000"
4012st "
4013Edited:
4014"
4015tm "CommentText"
4016wrapOption 3
4017visibleHeight 1000
4018visibleWidth 4000
4019)
4020position 1
4021ignorePrefs 1
4022titleBlock 1
4023)
4024*198 (CommentText
4025uid 45,0
4026shape (Rectangle
4027uid 46,0
4028sl 0
4029va (VaSet
4030vasetType 1
4031fg "65280,65280,46080"
4032)
4033xt "47000,29000,64000,30000"
4034)
4035oxt "18000,69000,35000,70000"
4036text (MLText
4037uid 47,0
4038va (VaSet
4039fg "0,0,32768"
4040bg "0,0,32768"
4041)
4042xt "47200,29000,60900,30000"
4043st "
4044%library/%unit/%view
4045"
4046tm "CommentText"
4047wrapOption 3
4048visibleHeight 1000
4049visibleWidth 17000
4050)
4051position 1
4052ignorePrefs 1
4053titleBlock 1
4054)
4055]
4056shape (GroupingShape
4057uid 17,0
4058va (VaSet
4059vasetType 1
4060fg "65535,65535,65535"
4061lineStyle 2
4062lineWidth 2
4063)
4064xt "43000,26000,84000,31000"
4065)
4066oxt "14000,66000,55000,71000"
4067)
4068*199 (CommentText
4069uid 133,0
4070shape (Rectangle
4071uid 134,0
4072layer 0
4073va (VaSet
4074vasetType 1
4075fg "65280,65280,46080"
4076lineColor "0,0,32768"
4077)
4078xt "0,-6000,33000,0"
4079)
4080text (MLText
4081uid 135,0
4082va (VaSet
4083fg "0,0,32768"
4084font "Arial,10,0"
4085)
4086xt "200,-5800,32200,-600"
4087st "
4088Created using Mentor Graphics HDL2Graphics(TM) Technology
4089on - 10:21:37 04.02.2010
4090from - D:\\E5b\\E5b_09_189\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hdl\\w5300_modul.vhd
4091
4092"
4093tm "CommentText"
4094wrapOption 3
4095visibleHeight 5600
4096visibleWidth 32600
4097)
4098)
4099]
4100bg "65535,65535,65535"
4101grid (Grid
4102origin "0,0"
4103isVisible 1
4104isActive 1
4105xSpacing 1000
4106xySpacing 1000
4107xShown 1
4108yShown 1
4109color "26368,26368,26368"
4110)
4111packageList *200 (PackageList
4112uid 170,0
4113stg "VerticalLayoutStrategy"
4114textVec [
4115*201 (Text
4116uid 171,0
4117va (VaSet
4118font "arial,8,1"
4119)
4120xt "0,1000,5400,2000"
4121st "Package List"
4122blo "0,1800"
4123)
4124*202 (MLText
4125uid 172,0
4126va (VaSet
4127)
4128xt "0,2000,15200,8000"
4129st "library IEEE;
4130use IEEE.STD_LOGIC_1164.ALL;
4131use IEEE.STD_LOGIC_ARITH.ALL;
4132use IEEE.STD_LOGIC_UNSIGNED.ALL;
4133library FACT_FAD_lib;
4134use FACT_FAD_lib.fad_definitions.ALL;"
4135tm "PackageList"
4136)
4137]
4138)
4139windowSize "0,0,1015,690"
4140viewArea "0,0,0,0"
4141cachedDiagramExtent "0,0,0,0"
4142pageBreakOrigin "0,0"
4143defaultCommentText (CommentText
4144shape (Rectangle
4145layer 0
4146va (VaSet
4147vasetType 1
4148fg "65280,65280,46080"
4149lineColor "0,0,32768"
4150)
4151xt "0,0,15000,5000"
4152)
4153text (MLText
4154va (VaSet
4155fg "0,0,32768"
4156)
4157xt "200,200,2000,1200"
4158st "
4159Text
4160"
4161tm "CommentText"
4162wrapOption 3
4163visibleHeight 4600
4164visibleWidth 14600
4165)
4166)
4167defaultPanel (Panel
4168shape (RectFrame
4169va (VaSet
4170vasetType 1
4171fg "65535,65535,65535"
4172lineColor "32768,0,0"
4173lineWidth 3
4174)
4175xt "0,0,20000,20000"
4176)
4177title (TextAssociate
4178ps "TopLeftStrategy"
4179text (Text
4180va (VaSet
4181font "Arial,8,1"
4182)
4183xt "1000,1000,3800,2000"
4184st "Panel0"
4185blo "1000,1800"
4186tm "PanelText"
4187)
4188)
4189)
4190parentGraphicsRef (HdmGraphicsRef
4191libraryName ""
4192entityName ""
4193viewName ""
4194)
4195defaultSymbolBody (SymbolBody
4196shape (Rectangle
4197va (VaSet
4198vasetType 1
4199fg "0,65535,0"
4200lineColor "0,32896,0"
4201lineWidth 2
4202)
4203xt "15000,6000,33000,26000"
4204)
4205biTextGroup (BiTextGroup
4206ps "CenterOffsetStrategy"
4207stg "VerticalLayoutStrategy"
4208first (Text
4209va (VaSet
4210font "Arial,8,1"
4211)
4212xt "22200,15000,25800,16000"
4213st "<library>"
4214blo "22200,15800"
4215)
4216second (Text
4217va (VaSet
4218font "Arial,8,1"
4219)
4220xt "22200,16000,24800,17000"
4221st "<cell>"
4222blo "22200,16800"
4223)
4224)
4225gi *203 (GenericInterface
4226ps "CenterOffsetStrategy"
4227matrix (Matrix
4228text (MLText
4229va (VaSet
4230font "Courier New,8,0"
4231)
4232xt "0,12000,11500,12800"
4233st "Generic Declarations"
4234)
4235header "Generic Declarations"
4236showHdrWhenContentsEmpty 1
4237)
4238elements [
4239]
4240)
4241portInstanceVisAsIs 1
4242portInstanceVis (PortSigDisplay
4243sIVOD 1
4244)
4245portVis (PortSigDisplay
4246sIVOD 1
4247)
4248)
4249defaultCptPort (CptPort
4250ps "OnEdgeStrategy"
4251shape (Triangle
4252ro 90
4253va (VaSet
4254vasetType 1
4255fg "0,65535,0"
4256)
4257xt "0,0,750,750"
4258)
4259tg (CPTG
4260ps "CptPortTextPlaceStrategy"
4261stg "VerticalLayoutStrategy"
4262f (Text
4263va (VaSet
4264)
4265xt "0,750,1400,1750"
4266st "In0"
4267blo "0,1550"
4268tm "CptPortNameMgr"
4269)
4270)
4271dt (MLText
4272va (VaSet
4273font "Courier New,8,0"
4274)
4275)
4276thePort (LogicalPort
4277decl (Decl
4278n "In0"
4279t "std_logic_vector"
4280b "(15 DOWNTO 0)"
4281o 0
4282)
4283)
4284)
4285defaultCptPortBuffer (CptPort
4286ps "OnEdgeStrategy"
4287shape (Diamond
4288va (VaSet
4289vasetType 1
4290fg "65535,65535,65535"
4291bg "0,0,0"
4292)
4293xt "0,0,750,750"
4294)
4295tg (CPTG
4296ps "CptPortTextPlaceStrategy"
4297stg "VerticalLayoutStrategy"
4298f (Text
4299va (VaSet
4300)
4301xt "0,750,2800,1750"
4302st "Buffer0"
4303blo "0,1550"
4304tm "CptPortNameMgr"
4305)
4306)
4307dt (MLText
4308va (VaSet
4309font "Courier New,8,0"
4310)
4311)
4312thePort (LogicalPort
4313m 3
4314decl (Decl
4315n "Buffer0"
4316t "std_logic_vector"
4317b "(15 DOWNTO 0)"
4318o 0
4319)
4320)
4321)
4322DeclarativeBlock *204 (SymDeclBlock
4323uid 1,0
4324stg "SymDeclLayoutStrategy"
4325declLabel (Text
4326uid 2,0
4327va (VaSet
4328font "Arial,8,1"
4329)
4330xt "0,14000,5400,15000"
4331st "Declarations"
4332blo "0,14800"
4333)
4334portLabel (Text
4335uid 3,0
4336va (VaSet
4337font "Arial,8,1"
4338)
4339xt "0,15000,2700,16000"
4340st "Ports:"
4341blo "0,15800"
4342)
4343externalLabel (Text
4344uid 4,0
4345va (VaSet
4346font "Arial,8,1"
4347)
4348xt "0,70400,2400,71400"
4349st "User:"
4350blo "0,71200"
4351)
4352internalLabel (Text
4353uid 6,0
4354va (VaSet
4355isHidden 1
4356font "Arial,8,1"
4357)
4358xt "0,14000,5800,15000"
4359st "Internal User:"
4360blo "0,14800"
4361)
4362externalText (MLText
4363uid 5,0
4364va (VaSet
4365font "Courier New,8,0"
4366)
4367xt "2000,71400,2000,71400"
4368tm "SyDeclarativeTextMgr"
4369)
4370internalText (MLText
4371uid 7,0
4372va (VaSet
4373isHidden 1
4374font "Courier New,8,0"
4375)
4376xt "0,14000,0,14000"
4377tm "SyDeclarativeTextMgr"
4378)
4379)
4380lastUid 1355,0
4381activeModelName "Symbol:CDM"
4382)
Note: See TracBrowser for help on using the repository browser.