source: firmware/FAD/FACT_FAD_TB_lib/hdl/dna_gen_tester_beha.vhd.bak@ 14207

--
-- VHDL Architecture FACT_FAD_TB_lib.dna_gen_tester.beha
--
-- Created:
--          by - daqct3.UNKNOWN (IHP110)
--          at - 09:57:18 03.03.2011
--
-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12)
--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;

ENTITY dna_gen_tester IS
   PORT( 
      dna   : IN     STD_LOGIC_VECTOR (63 DOWNTO 0);
      ready : IN     STD_LOGIC;
      clk   : OUT    STD_LOGIC
   );

-- Declarations

END dna_gen_tester ;

--
ARCHITECTURE beha OF dna_gen_tester IS
BEGIN
END ARCHITECTURE beha;