source: firmware/FAD/FACT_FAD_TB_lib/hdl/fad_main_tb_struct.vhd@ 18350

Last change on this file since 18350 was 11755, checked in by neise, 13 years ago
reinit of this svn repos .... it was all too messy deleted the old folders and restarted with FACT_FAD_lib only. (well and the testbenches)
File size: 14.6 KB
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1-- VHDL Entity FACT_FAD_TB_lib.fad_main_tb.symbol
2--
3-- Created:
4-- by - daqct3.UNKNOWN (IHP110)
5-- at - 16:23:49 09.06.2011
6--
7-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
8--
9LIBRARY ieee;
10USE ieee.std_logic_1164.all;
11USE ieee.std_logic_arith.all;
12
13ENTITY fad_main_tb IS
14-- Declarations
15
16END fad_main_tb ;
17
18--
19-- VHDL Architecture FACT_FAD_TB_lib.fad_main_tb.struct
20--
21-- Created:
22-- by - daqct3.UNKNOWN (IHP110)
23-- at - 16:23:49 09.06.2011
24--
25-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
26--
27LIBRARY ieee;
28USE ieee.std_logic_1164.all;
29USE ieee.std_logic_arith.all;
30USE ieee.std_logic_unsigned.all;
31
32LIBRARY FACT_FAD_lib;
33USE FACT_FAD_lib.fad_definitions.all;
34USE ieee.std_logic_textio.all;
35LIBRARY std;
36USE std.textio.all;
37
38LIBRARY FACT_FAD_lib;
39LIBRARY FACT_FAD_TB_lib;
40
41ARCHITECTURE struct OF fad_main_tb IS
42
43 -- Architecture declarations
44
45 -- Internal signal declarations
46 SIGNAL ADC_CLK : std_logic;
47 SIGNAL CLK_25_PS : std_logic;
48 SIGNAL CLK_50 : std_logic;
49 -- for debugging
50 SIGNAL DG_state : std_logic_vector(7 DOWNTO 0);
51 SIGNAL D_T_in : std_logic_vector(1 DOWNTO 0);
52 SIGNAL FTM_RS485_rx_d : std_logic;
53 SIGNAL FTM_RS485_rx_en : std_logic;
54 SIGNAL FTM_RS485_tx_d : std_logic;
55 SIGNAL FTM_RS485_tx_en : std_logic;
56 SIGNAL REF_CLK : STD_LOGIC := '0';
57 SIGNAL RSRLOAD : std_logic := '0';
58 SIGNAL SRCLK : std_logic := '0';
59 SIGNAL SRIN_out : std_logic := '0';
60 SIGNAL SROUT_in_0 : std_logic;
61 SIGNAL SROUT_in_1 : std_logic;
62 SIGNAL SROUT_in_2 : std_logic;
63 SIGNAL SROUT_in_3 : std_logic;
64 SIGNAL adc_data : std_logic_vector(11 DOWNTO 0);
65 SIGNAL adc_data_array : adc_data_array_type;
66 SIGNAL adc_oeb : std_logic;
67 SIGNAL adc_otr : STD_LOGIC;
68 SIGNAL adc_otr_array : std_logic_vector(3 DOWNTO 0);
69 SIGNAL alarm_refclk_too_high : std_logic;
70 SIGNAL alarm_refclk_too_low : std_logic;
71 SIGNAL amber : std_logic;
72 SIGNAL board_id : std_logic_vector(3 DOWNTO 0);
73 SIGNAL clk : STD_LOGIC;
74 SIGNAL counter_result : std_logic_vector(11 DOWNTO 0);
75 SIGNAL crate_id : std_logic_vector(1 DOWNTO 0);
76 SIGNAL dac_cs : std_logic;
77 SIGNAL debug_data_ram_empty : std_logic;
78 SIGNAL debug_data_valid : std_logic;
79 SIGNAL denable : std_logic := '0'; -- default domino wave off
80 SIGNAL drs_channel_id : std_logic_vector(3 DOWNTO 0) := (others => '0');
81 SIGNAL drs_dwrite : std_logic := '1';
82 SIGNAL green : std_logic;
83 SIGNAL led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
84 SIGNAL mem_manager_state : std_logic_vector(3 DOWNTO 0); -- state is encoded here ... useful for debugging.
85 SIGNAL mosi : std_logic := '0';
86 SIGNAL plllock_in : std_logic_vector(3 DOWNTO 0); -- high level, if dominowave is running and DRS PLL locked
87 SIGNAL red : std_logic;
88 SIGNAL sclk : std_logic;
89 SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0);
90 SIGNAL sio : std_logic;
91 SIGNAL socket_tx_free_out : std_logic_vector(16 DOWNTO 0); -- 17bit value .. that's true
92 SIGNAL trigger : std_logic;
93 SIGNAL trigger_veto : std_logic := '1';
94 SIGNAL w5300_state : std_logic_vector(7 DOWNTO 0); -- state is encoded here ... useful for debugging.
95 SIGNAL wiz_addr : std_logic_vector(9 DOWNTO 0);
96 SIGNAL wiz_cs : std_logic := '1';
97 SIGNAL wiz_data : std_logic_vector(15 DOWNTO 0);
98 SIGNAL wiz_int : std_logic;
99 SIGNAL wiz_rd : std_logic := '1';
100 SIGNAL wiz_reset : std_logic := '1';
101 SIGNAL wiz_wr : std_logic := '1';
102
103
104 -- Component Declarations
105 COMPONENT FAD_main
106 GENERIC (
107 RAMADDRWIDTH64b : integer := 12
108 );
109 PORT (
110 CLK : IN std_logic ;
111 D_T_in : IN std_logic_vector (1 DOWNTO 0);
112 FTM_RS485_rx_d : IN std_logic ;
113 SROUT_in_0 : IN std_logic ;
114 SROUT_in_1 : IN std_logic ;
115 SROUT_in_2 : IN std_logic ;
116 SROUT_in_3 : IN std_logic ;
117 adc_data_array : IN adc_data_array_type ;
118 adc_otr_array : IN std_logic_vector (3 DOWNTO 0);
119 board_id : IN std_logic_vector (3 DOWNTO 0);
120 crate_id : IN std_logic_vector (1 DOWNTO 0);
121 drs_refclk_in : IN std_logic ; -- used TO check if DRS REFCLK exsists, if not DENABLE inhibit
122 plllock_in : IN std_logic_vector (3 DOWNTO 0); -- high level, if dominowave is running and DRS PLL locked
123 trigger : IN std_logic ;
124 wiz_int : IN std_logic ;
125 ADC_CLK : OUT std_logic ;
126 CLK_25_PS : OUT std_logic ;
127 CLK_50 : OUT std_logic ;
128 -- for debugging
129 DG_state : OUT std_logic_vector (7 DOWNTO 0);
130 FTM_RS485_rx_en : OUT std_logic ;
131 FTM_RS485_tx_d : OUT std_logic ;
132 FTM_RS485_tx_en : OUT std_logic ;
133 RSRLOAD : OUT std_logic := '0';
134 SRCLK : OUT std_logic := '0';
135 SRIN_out : OUT std_logic := '0';
136 adc_oeb : OUT std_logic := '1';
137 alarm_refclk_too_high : OUT std_logic ;
138 alarm_refclk_too_low : OUT std_logic ;
139 amber : OUT std_logic ;
140 counter_result : OUT std_logic_vector (11 DOWNTO 0);
141 dac_cs : OUT std_logic ;
142 debug_data_ram_empty : OUT std_logic ;
143 debug_data_valid : OUT std_logic ;
144 denable : OUT std_logic := '0'; -- default domino wave off
145 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
146 drs_dwrite : OUT std_logic := '1';
147 green : OUT std_logic ;
148 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
149 mem_manager_state : OUT std_logic_vector (3 DOWNTO 0); -- state is encoded here ... useful for debugging.
150 mosi : OUT std_logic := '0';
151 red : OUT std_logic ;
152 sclk : OUT std_logic ;
153 sensor_cs : OUT std_logic_vector (3 DOWNTO 0);
154 socket_tx_free_out : OUT std_logic_vector (16 DOWNTO 0); -- 17bit value .. that's true
155 trigger_veto : OUT std_logic := '1';
156 w5300_state : OUT std_logic_vector (7 DOWNTO 0); -- state is encoded here ... useful for debugging.
157 wiz_addr : OUT std_logic_vector (9 DOWNTO 0);
158 wiz_cs : OUT std_logic := '1';
159 wiz_rd : OUT std_logic := '1';
160 wiz_reset : OUT std_logic := '1';
161 wiz_wr : OUT std_logic := '1';
162 sio : INOUT std_logic ;
163 wiz_data : INOUT std_logic_vector (15 DOWNTO 0)
164 );
165 END COMPONENT;
166 COMPONENT adc_emulator
167 GENERIC (
168 INPUT_FILE : string := "filename"
169 );
170 PORT (
171 clk : IN STD_LOGIC ;
172 data : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
173 otr : OUT STD_LOGIC ;
174 oeb : IN STD_LOGIC
175 );
176 END COMPONENT;
177 COMPONENT clock_generator
178 GENERIC (
179 clock_period : time := 50 ns;
180 reset_time : time := 50 ns
181 );
182 PORT (
183 clk : OUT std_logic := '0';
184 rst : OUT std_logic := '0'
185 );
186 END COMPONENT;
187 COMPONENT max6662_emulator
188 GENERIC (
189 DRS_TEMPERATURE : integer := 51
190 );
191 PORT (
192 sclk : IN std_logic ;
193 sio : INOUT std_logic ;
194 sensor_cs : IN std_logic_vector (3 DOWNTO 0)
195 );
196 END COMPONENT;
197 COMPONENT trigger_generator
198 GENERIC (
199 TRIGGER_RATE : time := 1 ms;
200 PULSE_WIDTH : time := 20 ns
201 );
202 PORT (
203 trigger : OUT std_logic
204 );
205 END COMPONENT;
206 COMPONENT w5300_emulator
207 PORT (
208 int : OUT std_logic := '1';
209 addr : IN std_logic_vector (9 DOWNTO 0);
210 data : INOUT std_logic_vector (15 DOWNTO 0);
211 rd : IN std_logic ;
212 cs : IN std_logic ;
213 wr : IN std_logic
214 );
215 END COMPONENT;
216
217 -- Optional embedded configurations
218 -- pragma synthesis_off
219 FOR ALL : FAD_main USE ENTITY FACT_FAD_lib.FAD_main;
220 FOR ALL : adc_emulator USE ENTITY FACT_FAD_TB_lib.adc_emulator;
221 FOR ALL : clock_generator USE ENTITY FACT_FAD_TB_lib.clock_generator;
222 FOR ALL : max6662_emulator USE ENTITY FACT_FAD_TB_lib.max6662_emulator;
223 FOR ALL : trigger_generator USE ENTITY FACT_FAD_TB_lib.trigger_generator;
224 FOR ALL : w5300_emulator USE ENTITY FACT_FAD_TB_lib.w5300_emulator;
225 -- pragma synthesis_on
226
227
228BEGIN
229 -- Architecture concurrent statements
230 -- HDL Embedded Text Block 1 eb_mainTB_ID
231 -- eb_ID 1: hard-wired IDs
232 board_id <= "0101";
233 crate_id <= "01";
234
235 -- HDL Embedded Text Block 2 eb_mainTB_adc
236 -- eb_adc 2: ADC routing
237 adc_data_array(0) <= adc_data;
238 adc_data_array(1) <= adc_data;
239 adc_data_array(2) <= adc_data;
240 adc_data_array(3) <= adc_data;
241 adc_otr_array(0) <= adc_otr;
242 adc_otr_array(1) <= adc_otr;
243 adc_otr_array(2) <= adc_otr;
244 adc_otr_array(3) <= adc_otr;
245
246 -- HDL Embedded Text Block 3 eb_mainTB_adc1
247
248 D_T_in(1 downto 0) <= "00";
249 plllock_in(3 downto 0) <= "1111";
250 SROUT_in_0 <= '1';
251 SROUT_in_1 <= '0';
252 SROUT_in_2 <= '1';
253 SROUT_in_3 <= '0';
254
255
256 -- Instance port mappings.
257 I_mainTB_FPGA : FAD_main
258 GENERIC MAP (
259 RAMADDRWIDTH64b => 15
260 )
261 PORT MAP (
262 CLK => clk,
263 D_T_in => D_T_in,
264 FTM_RS485_rx_d => FTM_RS485_rx_d,
265 SROUT_in_0 => SROUT_in_0,
266 SROUT_in_1 => SROUT_in_1,
267 SROUT_in_2 => SROUT_in_2,
268 SROUT_in_3 => SROUT_in_3,
269 adc_data_array => adc_data_array,
270 adc_otr_array => adc_otr_array,
271 board_id => board_id,
272 crate_id => crate_id,
273 drs_refclk_in => REF_CLK,
274 plllock_in => plllock_in,
275 trigger => trigger,
276 wiz_int => wiz_int,
277 ADC_CLK => ADC_CLK,
278 CLK_25_PS => CLK_25_PS,
279 CLK_50 => CLK_50,
280 DG_state => DG_state,
281 FTM_RS485_rx_en => FTM_RS485_rx_en,
282 FTM_RS485_tx_d => FTM_RS485_tx_d,
283 FTM_RS485_tx_en => FTM_RS485_tx_en,
284 RSRLOAD => RSRLOAD,
285 SRCLK => SRCLK,
286 SRIN_out => SRIN_out,
287 adc_oeb => adc_oeb,
288 alarm_refclk_too_high => alarm_refclk_too_high,
289 alarm_refclk_too_low => alarm_refclk_too_low,
290 amber => amber,
291 counter_result => counter_result,
292 dac_cs => dac_cs,
293 debug_data_ram_empty => debug_data_ram_empty,
294 debug_data_valid => debug_data_valid,
295 denable => denable,
296 drs_channel_id => drs_channel_id,
297 drs_dwrite => drs_dwrite,
298 green => green,
299 led => led,
300 mem_manager_state => mem_manager_state,
301 mosi => mosi,
302 red => red,
303 sclk => sclk,
304 sensor_cs => sensor_cs,
305 socket_tx_free_out => socket_tx_free_out,
306 trigger_veto => trigger_veto,
307 w5300_state => w5300_state,
308 wiz_addr => wiz_addr,
309 wiz_cs => wiz_cs,
310 wiz_rd => wiz_rd,
311 wiz_reset => wiz_reset,
312 wiz_wr => wiz_wr,
313 sio => sio,
314 wiz_data => wiz_data
315 );
316 I_mainTB_adc : adc_emulator
317 GENERIC MAP (
318 INPUT_FILE => "../memory_files/analog_input_ch0.txt"
319 )
320 PORT MAP (
321 clk => ADC_CLK,
322 data => adc_data,
323 otr => adc_otr,
324 oeb => adc_oeb
325 );
326 I_mainTB_clock : clock_generator
327 GENERIC MAP (
328 clock_period => 20 ns,
329 reset_time => 50 ns
330 )
331 PORT MAP (
332 clk => clk,
333 rst => OPEN
334 );
335 I_mainTB_clock1 : clock_generator
336 GENERIC MAP (
337 clock_period => 1 us,
338 reset_time => 1 us
339 )
340 PORT MAP (
341 clk => REF_CLK,
342 rst => OPEN
343 );
344 I_mainTB_max6662 : max6662_emulator
345 GENERIC MAP (
346 DRS_TEMPERATURE => 51
347 )
348 PORT MAP (
349 sclk => sclk,
350 sio => sio,
351 sensor_cs => sensor_cs
352 );
353 I_mainTB_trigger : trigger_generator
354 GENERIC MAP (
355 TRIGGER_RATE => 1 ms,
356 PULSE_WIDTH => 20 ns
357 )
358 PORT MAP (
359 trigger => trigger
360 );
361 I_mainTB_w5300 : w5300_emulator
362 PORT MAP (
363 int => wiz_int,
364 addr => wiz_addr,
365 data => wiz_data,
366 rd => wiz_rd,
367 cs => wiz_cs,
368 wr => wiz_wr
369 );
370
371END struct;
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