1 | -- VHDL Entity FACT_FAD_TB_lib.led_controller_tb.symbol
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2 | --
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3 | -- Created:
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4 | -- by - daqct3.UNKNOWN (IHP110)
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5 | -- at - 10:21:57 02.03.2011
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6 | --
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7 | -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
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8 | --
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9 |
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10 |
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11 | ENTITY led_controller_tb IS
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12 | GENERIC(
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13 | HEARTBEAT_PWM_DIVIDER : integer := 500;
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14 | WAITING_DIVIDER : integer := 500000000
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15 | );
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16 | -- Declarations
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17 |
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18 | END led_controller_tb ;
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19 |
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20 | --
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21 | -- VHDL Architecture FACT_FAD_TB_lib.led_controller_tb.struct
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22 | --
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23 | -- Created:
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24 | -- by - daqct3.UNKNOWN (IHP110)
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25 | -- at - 10:21:58 02.03.2011
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26 | --
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27 | -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
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28 | --
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29 | LIBRARY ieee;
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30 | USE ieee.std_logic_1164.ALL;
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31 | USE ieee.std_logic_arith.ALL;
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32 | USE ieee.STD_LOGIC_UNSIGNED.ALL;
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33 | LIBRARY FACT_FAD_lib;
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34 | USE FACT_FAD_lib.fad_definitions.ALL;
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35 |
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36 | LIBRARY FACT_FAD_lib;
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37 | LIBRARY FACT_FAD_TB_lib;
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38 |
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39 | ARCHITECTURE struct OF led_controller_tb IS
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40 |
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41 | -- Architecture declarations
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42 |
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43 | -- Internal signal declarations
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44 | SIGNAL CLK : std_logic;
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45 | SIGNAL additional_flasher_out : std_logic;
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46 | SIGNAL amber : std_logic;
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47 | SIGNAL green : std_logic;
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48 | SIGNAL red : std_logic;
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49 | SIGNAL refclk_too_high : std_logic;
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50 | SIGNAL refclk_too_low : std_logic;
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51 | SIGNAL socks_connected : std_logic;
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52 | SIGNAL socks_waiting : std_logic;
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53 | SIGNAL trigger : std_logic;
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54 |
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55 |
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56 | -- Component Declarations
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57 | COMPONENT led_controller
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58 | GENERIC (
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59 | HEARTBEAT_PWM_DIVIDER : integer := 500;
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60 | WAITING_DIVIDER : integer := 500000000
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61 | );
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62 | PORT (
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63 | CLK : IN std_logic;
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64 | refclk_too_high : IN std_logic;
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65 | refclk_too_low : IN std_logic;
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66 | socks_connected : IN std_logic;
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67 | socks_waiting : IN std_logic;
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68 | trigger : IN std_logic;
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69 | additional_flasher_out : OUT std_logic;
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70 | amber : OUT std_logic;
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71 | green : OUT std_logic;
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72 | red : OUT std_logic
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73 | );
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74 | END COMPONENT;
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75 | COMPONENT clock_generator
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76 | GENERIC (
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77 | clock_period : time := 20 ns;
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78 | reset_time : time := 50 ns
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79 | );
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80 | PORT (
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81 | clk : OUT std_logic := '0';
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82 | rst : OUT std_logic := '0'
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83 | );
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84 | END COMPONENT;
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85 | COMPONENT led_controller_tester
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86 | PORT (
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87 | additional_flasher_out : IN std_logic ;
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88 | amber : IN std_logic ;
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89 | green : IN std_logic ;
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90 | red : IN std_logic ;
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91 | refclk_too_high : OUT std_logic ;
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92 | refclk_too_low : OUT std_logic ;
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93 | socks_connected : OUT std_logic ;
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94 | socks_waiting : OUT std_logic ;
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95 | trigger : OUT std_logic
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96 | );
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97 | END COMPONENT;
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98 |
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99 | -- Optional embedded configurations
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100 | -- pragma synthesis_off
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101 | FOR ALL : clock_generator USE ENTITY FACT_FAD_TB_lib.clock_generator;
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102 | FOR ALL : led_controller USE ENTITY FACT_FAD_lib.led_controller;
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103 | FOR ALL : led_controller_tester USE ENTITY FACT_FAD_TB_lib.led_controller_tester;
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104 | -- pragma synthesis_on
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105 |
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106 |
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107 | BEGIN
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108 |
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109 | -- Instance port mappings.
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110 | led_controller_instance : led_controller
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111 | GENERIC MAP (
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112 | HEARTBEAT_PWM_DIVIDER => 500,
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113 | WAITING_DIVIDER => 500000000
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114 | )
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115 | PORT MAP (
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116 | CLK => CLK,
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117 | green => green,
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118 | amber => amber,
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119 | red => red,
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120 | additional_flasher_out => additional_flasher_out,
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121 | trigger => trigger,
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122 | refclk_too_high => refclk_too_high,
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123 | refclk_too_low => refclk_too_low,
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124 | socks_waiting => socks_waiting,
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125 | socks_connected => socks_connected
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126 | );
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127 | U_2 : clock_generator
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128 | GENERIC MAP (
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129 | clock_period => 20 ns,
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130 | reset_time => 50 ns
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131 | )
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132 | PORT MAP (
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133 | clk => CLK,
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134 | rst => OPEN
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135 | );
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136 | U_1 : led_controller_tester
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137 | PORT MAP (
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138 | additional_flasher_out => additional_flasher_out,
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139 | amber => amber,
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140 | green => green,
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141 | red => red,
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142 | refclk_too_high => refclk_too_high,
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143 | refclk_too_low => refclk_too_low,
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144 | socks_connected => socks_connected,
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145 | socks_waiting => socks_waiting,
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146 | trigger => trigger
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147 | );
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148 |
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149 | END struct;
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