source: firmware/FAD/FACT_FAD_TB_lib/hdl/phase_shifter_tester_beha.vhd@ 14207

Last change on this file since 14207 was 11755, checked in by neise, 13 years ago
reinit of this svn repos .... it was all too messy deleted the old folders and restarted with FACT_FAD_lib only. (well and the testbenches)
File size: 3.3 KB
Line 
1--
2-- VHDL Architecture FACT_FAD_TB_lib.phase_shifter_tester.beha
3--
4-- Created:
5-- by - dneise.UNKNOWN (E5B-LABOR6)
6-- at - 14:39:41 12.02.2011
7--
8-- using Mentor Graphics HDL Designer(TM) 2009.2 (Build 10)
9--
10LIBRARY ieee;
11USE ieee.std_logic_1164.ALL;
12USE IEEE.NUMERIC_STD.ALL;
13LIBRARY FACT_FAD_lib;
14USE FACT_FAD_lib.fad_definitions.ALL;
15
16ENTITY phase_shifter_tester IS
17 PORT(
18 -- interface to: clock_generator_variable_PS_struct.vhd
19
20 clk:in std_logic;
21
22
23 PSCLK : IN std_logic;
24 PSEN : IN std_logic;
25 PSINCDEC : IN std_logic; -- default is 'incrementing'
26 offset : IN std_logic_vector (7 DOWNTO 0);
27 ready : IN std_logic;
28 rst : IN std_logic; --asynch in of DCM
29 -- status:
30 shifting : IN std_logic;
31 LOCKED : OUT std_logic; -- when is this going high?
32 PSDONE : OUT std_logic; -- will pulse once, if phase shifting was done.
33 direction : OUT std_logic; -- corresponds to 'PSINCDEC'
34 reset_DCM : OUT std_logic; -- asynch in: orders us, to reset the DCM
35 -- interface to: w5300_modul.vhd
36 shift_phase : OUT std_logic
37 );
38
39-- Declarations
40
41END phase_shifter_tester ;
42
43--
44ARCHITECTURE beha OF phase_shifter_tester IS
45constant DIVIDER : integer := 25;
46 signal bla : std_logic := '0';
47 signal Z: integer range 0 to DIVIDER - 1;
48 signal Y: integer range 0 to DIVIDER - 1;
49 signal ping : std_logic := '0';
50 signal locken : std_logic := '1';
51BEGIN
52
53LOCKED <= '1' and locken;
54
55
56 process
57 begin
58 direction <= '1';
59 shift_phase <='0';
60 reset_DCM <= '0';
61
62
63
64 wait for 1us;
65 shift_phase <='1';
66 wait for 100ns;
67 shift_phase <='0';
68 wait for 1us;
69 shift_phase <='1';
70 wait for 100ns;
71 shift_phase <='0';
72 wait for 1us;
73 shift_phase <='1';
74 wait for 100ns;
75 shift_phase <='0';
76
77 wait for 1us;
78 reset_DCM <='1';
79 wait for 500ns;
80 reset_DCM <='0';
81
82 end process;
83
84 -- DCM PSDONE simulation
85 -- after DCM receives PSEN high it will start shifting and then .. after a while rise PSDONE for 1 cycle.
86 -- let's see how to simulate this here.
87
88 clk_proc: process (clk)
89
90 begin
91
92 if rising_edge(clk) then
93 if (PSEN = '1') then
94 bla <= '1';
95 end if;
96
97 if (bla = '1') then
98 if (Z < DIVIDER - 1) then
99 Z <= Z + 1;
100 else
101 Z <= 0;
102 bla <= '0';
103 end if;
104 if (Z = 0) then
105 PSDONE <= '0';
106 end if;
107 if (Z = DIVIDER -2 ) then
108 PSDONE <= '1';
109
110 end if;
111 if (Z = DIVIDER -1 ) then
112 PSDONE <= '0';
113
114 end if;
115
116 end if; --bla =1
117
118 end if;
119 end process clk_proc;
120
121 process (clk)
122 begin
123 if (rst = '1') then
124 ping <= '1';
125 locken <= '0';
126 end if;
127
128 if rising_edge(clk) then
129 if (ping = '1') then
130 if (Y < DIVIDER - 1) then
131 Y <= Y + 1;
132 else
133 Y <= 0;
134 ping <= '0';
135 end if;
136
137
138 if (Y = DIVIDER -1 ) then
139 locken <= '1';
140
141 end if;
142
143 end if; --bla =1
144
145 end if;
146 end process;
147
148
149
150
151END ARCHITECTURE beha;
152
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