source: firmware/FAD/FACT_FAD_TB_lib/hdl/refclk_counter_tb_struct.vhd@ 14288

Last change on this file since 14288 was 11755, checked in by neise, 13 years ago
reinit of this svn repos .... it was all too messy deleted the old folders and restarted with FACT_FAD_lib only. (well and the testbenches)
File size: 2.9 KB
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1-- VHDL Entity FACT_FAD_TB_lib.REFCLK_counter_tb.symbol
2--
3-- Created:
4-- by - daqct3.UNKNOWN (IHP110)
5-- at - 18:11:15 03.03.2011
6--
7-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
8--
9
10
11ENTITY REFCLK_counter_tb IS
12 GENERIC(
13 FREQ_UPPER_LIMIT : integer := 3000;
14 FREQ_LOWER_LIMIT : integer := 300
15 );
16-- Declarations
17
18END REFCLK_counter_tb ;
19
20--
21-- VHDL Architecture FACT_FAD_TB_lib.REFCLK_counter_tb.struct
22--
23-- Created:
24-- by - daqct3.UNKNOWN (IHP110)
25-- at - 18:11:15 03.03.2011
26--
27-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
28--
29LIBRARY ieee;
30USE ieee.std_logic_1164.ALL;
31USE IEEE.NUMERIC_STD.ALL;
32LIBRARY FACT_FAD_lib;
33USE FACT_FAD_lib.fad_definitions.ALL;
34USE ieee.std_logic_unsigned.all;
35
36LIBRARY FACT_FAD_lib;
37LIBRARY FACT_FAD_TB_lib;
38
39ARCHITECTURE struct OF REFCLK_counter_tb IS
40
41 -- Architecture declarations
42
43 -- Internal signal declarations
44 SIGNAL alarm_refclk_too_high : std_logic;
45 SIGNAL alarm_refclk_too_low : std_logic;
46 SIGNAL clk : std_logic := '0';
47 SIGNAL counter_result : std_logic_vector(11 DOWNTO 0);
48 SIGNAL refclk_in : std_logic;
49
50
51 -- Component Declarations
52 COMPONENT REFCLK_counter
53 PORT (
54 clk : IN std_logic;
55 refclk_in : IN std_logic;
56 alarm_refclk_too_high : OUT std_logic := '0';
57 alarm_refclk_too_low : OUT std_logic := '0';
58 counter_result : OUT std_logic_vector (11 DOWNTO 0) := (others => '0')
59 );
60 END COMPONENT;
61 COMPONENT REFCLK_counter_tester
62 PORT (
63 alarm_refclk_too_high : IN std_logic ;
64 alarm_refclk_too_low : IN std_logic ;
65 counter_result : IN std_logic_vector (11 DOWNTO 0);
66 clk : OUT std_logic ;
67 refclk_in : OUT std_logic
68 );
69 END COMPONENT;
70
71 -- Optional embedded configurations
72 -- pragma synthesis_off
73 FOR ALL : REFCLK_counter USE ENTITY FACT_FAD_lib.REFCLK_counter;
74 FOR ALL : REFCLK_counter_tester USE ENTITY FACT_FAD_TB_lib.REFCLK_counter_tester;
75 -- pragma synthesis_on
76
77
78BEGIN
79
80 -- Instance port mappings.
81 U_0 : REFCLK_counter
82 PORT MAP (
83 clk => clk,
84 refclk_in => refclk_in,
85 counter_result => counter_result,
86 alarm_refclk_too_high => alarm_refclk_too_high,
87 alarm_refclk_too_low => alarm_refclk_too_low
88 );
89 U_1 : REFCLK_counter_tester
90 PORT MAP (
91 alarm_refclk_too_high => alarm_refclk_too_high,
92 alarm_refclk_too_low => alarm_refclk_too_low,
93 counter_result => counter_result,
94 clk => clk,
95 refclk_in => refclk_in
96 );
97
98END struct;
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