source: firmware/FAD/FACT_FAD_TB_lib/hdl/spi_ltc2600_tb_struct.vhd@ 17050

-- VHDL Entity FACT_FAD_TB_lib.spi_ltc2600_tb.symbol
--
-- Created:
--          by - dneise.UNKNOWN (E5B-LABOR6)
--          at - 20:11:25 03.02.2011
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
--


ENTITY spi_ltc2600_tb IS
-- Declarations

END spi_ltc2600_tb ;

--
-- VHDL Architecture FACT_FAD_TB_lib.spi_ltc2600_tb.struct
--
-- Created:
--          by - dneise.UNKNOWN (E5B-LABOR6)
--          at - 20:11:25 03.02.2011
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.all;

LIBRARY FACT_FAD_lib;
LIBRARY FACT_FAD_TB_lib;

ARCHITECTURE struct OF spi_ltc2600_tb IS

   -- Architecture declarations

   -- Internal signal declarations
   SIGNAL CS       : std_logic;
   SIGNAL MISO     : std_logic;
   SIGNAL MOSI     : std_logic;
   SIGNAL SCLK     : std_logic;
   SIGNAL address  : std_logic_vector(3 DOWNTO 0);
   SIGNAL busy     : std_logic;
   SIGNAL clk      : std_logic;
   SIGNAL command  : std_logic_vector(3 DOWNTO 0);
   SIGNAL data     : std_logic_vector(15 DOWNTO 0);
   SIGNAL ready    : std_logic;
   SIGNAL transmit : std_logic;


   -- Component Declarations
   COMPONENT spi_ltc2600
   PORT (
      address  : IN     std_logic_vector (3 DOWNTO 0);
      clk      : IN     std_logic;
      command  : IN     std_logic_vector (3 DOWNTO 0);
      data     : IN     std_logic_vector (15 DOWNTO 0);
      transmit : IN     std_logic;
      CS       : OUT    std_logic  := '1';
      MISO     : OUT    std_logic  := 'Z';
      MOSI     : OUT    std_logic  := '0';
      SCLK     : OUT    std_logic  := '0';
      busy     : OUT    std_logic  := '1';
      ready    : OUT    std_logic  := '0'
   );
   END COMPONENT;
   COMPONENT clock_generator
   GENERIC (
      clock_period : time := 20 ns;
      reset_time   : time := 50 ns
   );
   PORT (
      clk : OUT    std_logic  := '0';
      rst : OUT    std_logic  := '0'
   );
   END COMPONENT;
   COMPONENT spi_ltc2600_tester
   PORT (
      CS       : IN     std_logic ;
      MISO     : IN     std_logic ;
      MOSI     : IN     std_logic ;
      SCLK     : IN     std_logic ;
      busy     : IN     std_logic ;
      ready    : IN     std_logic ;
      address  : OUT    std_logic_vector (3 DOWNTO 0);
      command  : OUT    std_logic_vector (3 DOWNTO 0);
      data     : OUT    std_logic_vector (15 DOWNTO 0);
      transmit : OUT    std_logic 
   );
   END COMPONENT;

   -- Optional embedded configurations
   -- pragma synthesis_off
   FOR ALL : clock_generator USE ENTITY FACT_FAD_TB_lib.clock_generator;
   FOR ALL : spi_ltc2600 USE ENTITY FACT_FAD_lib.spi_ltc2600;
   FOR ALL : spi_ltc2600_tester USE ENTITY FACT_FAD_TB_lib.spi_ltc2600_tester;
   -- pragma synthesis_on


BEGIN

   -- Instance port mappings.
   U_0 : spi_ltc2600
      PORT MAP (
         clk      => clk,
         SCLK     => SCLK,
         CS       => CS,
         MOSI     => MOSI,
         MISO     => MISO,
         transmit => transmit,
         command  => command,
         address  => address,
         data     => data,
         ready    => ready,
         busy     => busy
      );
   U_2 : clock_generator
      GENERIC MAP (
         clock_period => 20 ns,
         reset_time   => 50 ns
      )
      PORT MAP (
         clk => clk,
         rst => OPEN
      );
   U_1 : spi_ltc2600_tester
      PORT MAP (
         CS       => CS,
         MISO     => MISO,
         MOSI     => MOSI,
         SCLK     => SCLK,
         busy     => busy,
         ready    => ready,
         address  => address,
         command  => command,
         data     => data,
         transmit => transmit
      );

END struct;