source: firmware/FAD/FACT_FAD_TB_lib/hdl/spi_max6662_tb_struct.vhd@ 17873

Last change on this file since 17873 was 11755, checked in by neise, 13 years ago
reinit of this svn repos .... it was all too messy deleted the old folders and restarted with FACT_FAD_lib only. (well and the testbenches)
File size: 4.8 KB
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1-- VHDL Entity FACT_FAD_TB_lib.spi_max6662_tb.symbol
2--
3-- Created:
4-- by - dneise.UNKNOWN (E5B-LABOR6)
5-- at - 19:20:17 03.02.2011
6--
7-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
8--
9
10
11ENTITY spi_max6662_tb IS
12 GENERIC(
13 SPI_CLK_DIVIDER : integer := 25;
14 SCLK_CYCLES : integer := 24
15 );
16-- Declarations
17
18END spi_max6662_tb ;
19
20--
21-- VHDL Architecture FACT_FAD_TB_lib.spi_max6662_tb.struct
22--
23-- Created:
24-- by - dneise.UNKNOWN (E5B-LABOR6)
25-- at - 19:20:17 03.02.2011
26--
27-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
28--
29LIBRARY ieee;
30USE ieee.std_logic_1164.ALL;
31USE ieee.std_logic_arith.ALL;
32USE ieee.std_logic_unsigned.all;
33LIBRARY FACT_FAD_lib;
34USE FACT_FAD_lib.fad_definitions.all;
35
36LIBRARY FACT_FAD_lib;
37LIBRARY FACT_FAD_TB_lib;
38
39ARCHITECTURE struct OF spi_max6662_tb IS
40
41 -- Architecture declarations
42
43 -- Internal signal declarations
44 SIGNAL CS : std_logic;
45 SIGNAL MOSI : std_logic := '0';
46 SIGNAL SCLK : std_logic;
47 SIGNAL busy : std_logic;
48 SIGNAL clk : std_logic;
49 SIGNAL data : std_logic_vector(15 DOWNTO 0);
50 SIGNAL read_temp_register : std_logic;
51 SIGNAL ready : std_logic;
52 SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0);
53 SIGNAL sio : std_logic;
54
55
56 -- Component Declarations
57 COMPONENT spi_max6662
58 PORT (
59 clk : IN std_logic;
60 read_temp_register : IN std_logic;
61 CS : OUT std_logic := '1';
62 MOSI : OUT std_logic := '0';
63 SCLK : OUT std_logic := '0';
64 busy : OUT std_logic := '1';
65 data : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
66 ready : OUT std_logic := '0';
67 MISO : INOUT std_logic := 'Z'
68 );
69 END COMPONENT;
70 COMPONENT clock_generator
71 GENERIC (
72 clock_period : time := 20 ns;
73 reset_time : time := 50 ns
74 );
75 PORT (
76 clk : OUT std_logic := '0';
77 rst : OUT std_logic := '0'
78 );
79 END COMPONENT;
80 COMPONENT max6662_emulator
81 GENERIC (
82 DRS_TEMPERATURE : integer := 51
83 );
84 PORT (
85 sclk : IN std_logic ;
86 sio : INOUT std_logic ;
87 sensor_cs : IN std_logic_vector (3 DOWNTO 0)
88 );
89 END COMPONENT;
90 COMPONENT spi_max6662_tester
91 PORT (
92 CS : IN std_logic ;
93 MOSI : IN std_logic ;
94 SCLK : IN std_logic ;
95 busy : IN std_logic ;
96 data : IN std_logic_vector (15 DOWNTO 0);
97 ready : IN std_logic ;
98 read_temp_register : OUT std_logic
99 );
100 END COMPONENT;
101
102 -- Optional embedded configurations
103 -- pragma synthesis_off
104 FOR ALL : clock_generator USE ENTITY FACT_FAD_TB_lib.clock_generator;
105 FOR ALL : max6662_emulator USE ENTITY FACT_FAD_TB_lib.max6662_emulator;
106 FOR ALL : spi_max6662 USE ENTITY FACT_FAD_lib.spi_max6662;
107 FOR ALL : spi_max6662_tester USE ENTITY FACT_FAD_TB_lib.spi_max6662_tester;
108 -- pragma synthesis_on
109
110
111BEGIN
112 -- Architecture concurrent statements
113 -- HDL Embedded Text Block 1 eb1
114 sensor_cs <= (CS,CS,CS,CS);
115
116
117 -- Instance port mappings.
118 U_0 : spi_max6662
119 PORT MAP (
120 clk => clk,
121 SCLK => SCLK,
122 CS => CS,
123 MOSI => MOSI,
124 MISO => sio,
125 read_temp_register => read_temp_register,
126 data => data,
127 ready => ready,
128 busy => busy
129 );
130 -- synthesis translate_off
131 U_2 : clock_generator
132 GENERIC MAP (
133 clock_period => 20 ns,
134 reset_time => 50 ns
135 )
136 PORT MAP (
137 clk => clk,
138 rst => OPEN
139 );
140 U_3 : max6662_emulator
141 GENERIC MAP (
142 DRS_TEMPERATURE => 51
143 )
144 PORT MAP (
145 sclk => SCLK,
146 sio => sio,
147 sensor_cs => sensor_cs
148 );
149 U_1 : spi_max6662_tester
150 PORT MAP (
151 CS => CS,
152 MOSI => MOSI,
153 SCLK => SCLK,
154 busy => busy,
155 data => data,
156 ready => ready,
157 read_temp_register => read_temp_register
158 );
159
160END struct;
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