source: firmware/FAD/FACT_FAD_TB_lib/hdl/spi_max6662_tester_beha.vhd

--
-- VHDL Architecture FACT_FAD_TB_lib.spi_max6662_tester.beha
--
-- Created:
--          by - dneise.UNKNOWN (E5B-LABOR6)
--          at - 14:21:59 31.01.2011
--
-- using Mentor Graphics HDL Designer(TM) 2009.2 (Build 10)
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.all;

ENTITY spi_max6662_tester IS
   PORT( 
      CS                 : IN     std_logic;
      MOSI               : IN     std_logic;
      SCLK               : IN     std_logic;
      busy               : IN     std_logic;
      data               : IN     std_logic_vector (15 DOWNTO 0);
      ready              : IN     std_logic;
      read_temp_register : OUT    std_logic
   );

-- Declarations

END spi_max6662_tester ;

--
ARCHITECTURE beha OF spi_max6662_tester IS
BEGIN

  process
  begin
    read_temp_register <= '0';
    wait for 5000ns;
    read_temp_register <= '1';
    wait for 50ns;
    read_temp_register <= '0';
    wait for 20us;
    read_temp_register <= '1';
    wait for 50ns;
    read_temp_register <= '0';
    wait;
  end process ;
  
END ARCHITECTURE beha;