--
-- VHDL Architecture FACT_FAD_TB_lib.simple_trigger.beha
--
-- Created:
--          by - FPGA_Developer.UNKNOWN (EEPC8)
--          at - 14:01:15 10.02.2010
--
-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.NUMERIC_STD.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library FACT_FAD_lib;
use FACT_FAD_lib.fad_definitions.all;

entity trigger_generator is
   generic( 
      TRIGGER_RATE : time := 1 ms;
      PULSE_WIDTH  : time := 20 ns
   );
   port( 
      trigger : out    std_logic
   );
end trigger_generator ;

architecture beha of trigger_generator is
begin
  
  trigger_proc: process
  begin
    trigger <= '0';
    wait for TRIGGER_RATE;
    --trigger <= '1';
    wait for PULSE_WIDTH;
    trigger <= '0';
    --wait;
  end process trigger_proc;
end architecture beha;