DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
dmPackageRefs [
(DmPackageRef
library "ieee"
unitName "std_logic_1164"
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(DmPackageRef
library "ieee"
unitName "std_logic_arith"
)
(DmPackageRef
library "ieee"
unitName "std_logic_unsigned"
)
(DmPackageRef
library "FACT_FAD_lib"
unitName "fad_definitions"
)
(DmPackageRef
library "ieee"
unitName "std_logic_textio"
)
(DmPackageRef
library "std"
unitName "textio"
)
]
instances [
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name "I_mainTB_FPGA"
duLibraryName "FACT_FAD_lib"
duName "FAD_main"
elements [
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value "15"
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mwi 0
uid 233,0
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(Instance
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duLibraryName "FACT_FAD_TB_lib"
duName "clock_generator"
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mwi 0
uid 274,0
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(Instance
name "I_mainTB_max6662"
duLibraryName "FACT_FAD_TB_lib"
duName "max6662_emulator"
elements [
(GiElement
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type "integer"
value "51"
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mwi 0
uid 362,0
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(Instance
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duLibraryName "FACT_FAD_TB_lib"
duName "trigger_generator"
elements [
(GiElement
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type "time"
value "1 ms"
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(GiElement
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type "time"
value "20 ns"
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mwi 0
uid 414,0
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(Instance
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duLibraryName "FACT_FAD_TB_lib"
duName "adc_emulator"
elements [
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type "string"
value "\"../memory_files/analog_input_ch0.txt\""
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mwi 0
uid 508,0
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(Instance
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duLibraryName "FACT_FAD_TB_lib"
duName "clock_generator"
elements [
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mwi 0
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duName "w5300_emulator"
elements [
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duName "FAD_main_with_w53002"
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embeddedInstances [
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number "1"
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(EmbeddedInstance
name "eb_mainTB_adc"
number "2"
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(EmbeddedInstance
name "eb_mainTB_adc1"
number "3"
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libraryRefs [
"ieee"
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version "29.1"
appVersion "2009.2 (Build 10)"
noEmbeddedEditors 1
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value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hdl"
)
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value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
)
(vvPair
variable "SideDataDesignDir"
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)
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variable "SideDataUserDir"
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variable "d"
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variable "d_logical"
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variable "date"
value "01.06.2011"
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(vvPair
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variable "language"
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variable "library"
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(vvPair
variable "library_downstream_ISEPARInvoke"
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(vvPair
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(vvPair
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(vvPair
variable "package_name"
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variable "project_name"
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(vvPair
variable "series"
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(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
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(vvPair
variable "task_LeonardoPath"
value "<TBD>"
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(vvPair
variable "task_ModelSimPath"
value "C:\\modeltech_6.6a\\win32"
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(vvPair
variable "task_NC-SimPath"
value "<TBD>"
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(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
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(vvPair
variable "task_QuestaSimPath"
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variable "task_VCSPath"
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variable "time"
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variable "unit"
value "fad_main_tb"
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variable "version"
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(vvPair
variable "view"
value "struct"
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(vvPair
variable "year"
value "2011"
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variable "yy"
value "11"
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)
)
thePort (LogicalPort
decl (Decl
n "wiz_int"
t "std_logic"
o 15
suid 31,0
)
)
)
*25 (CptPort
uid 157,0
ps "OnEdgeStrategy"
shape (Triangle
uid 158,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,22625,81000,23375"
)
tg (CPTG
uid 159,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 160,0
va (VaSet
)
xt "82000,22500,86800,23500"
st "CLK_25_PS"
blo "82000,23300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "CLK_25_PS"
t "std_logic"
o 17
suid 35,0
)
)
)
*26 (CptPort
uid 161,0
ps "OnEdgeStrategy"
shape (Triangle
uid 162,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,21625,81000,22375"
)
tg (CPTG
uid 163,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 164,0
va (VaSet
)
xt "82000,21500,85300,22500"
st "CLK_50"
blo "82000,22300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "CLK_50"
t "std_logic"
preAdd 0
posAdd 0
o 18
suid 37,0
)
)
)
*27 (CptPort
uid 165,0
ps "OnEdgeStrategy"
shape (Triangle
uid 166,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,20625,81000,21375"
)
tg (CPTG
uid 167,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 168,0
va (VaSet
)
xt "82000,20500,83900,21500"
st "CLK"
blo "82000,21300"
)
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_logic"
o 1
suid 38,0
)
)
)
*28 (CptPort
uid 169,0
ps "OnEdgeStrategy"
shape (Triangle
uid 170,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,41625,81000,42375"
)
tg (CPTG
uid 171,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 172,0
va (VaSet
)
xt "82000,41500,91300,42500"
st "adc_otr_array : (3:0)"
blo "82000,42300"
)
)
thePort (LogicalPort
decl (Decl
n "adc_otr_array"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 9
suid 40,0
)
)
)
*29 (CptPort
uid 173,0
ps "OnEdgeStrategy"
shape (Triangle
uid 174,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,47625,81000,48375"
)
tg (CPTG
uid 175,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 176,0
va (VaSet
)
xt "82000,47500,88900,48500"
st "adc_data_array"
blo "82000,48300"
)
)
thePort (LogicalPort
decl (Decl
n "adc_data_array"
t "adc_data_array_type"
o 8
suid 41,0
)
)
)
*30 (CptPort
uid 177,0
ps "OnEdgeStrategy"
shape (Triangle
uid 178,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,61625,81000,62375"
)
tg (CPTG
uid 179,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 180,0
va (VaSet
)
xt "82000,61500,91500,62500"
st "drs_channel_id : (3:0)"
blo "82000,62300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_channel_id"
t "std_logic_vector"
b "(3 downto 0)"
o 35
suid 48,0
i "(others => '0')"
)
)
)
*31 (CptPort
uid 181,0
ps "OnEdgeStrategy"
shape (Triangle
uid 182,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,66625,81000,67375"
)
tg (CPTG
uid 183,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 184,0
va (VaSet
)
xt "82000,66500,87200,67500"
st "drs_dwrite"
blo "82000,67300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_dwrite"
t "std_logic"
o 36
suid 49,0
i "'1'"
)
)
)
*32 (CptPort
uid 185,0
ps "OnEdgeStrategy"
shape (Triangle
uid 186,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,57625,81000,58375"
)
tg (CPTG
uid 187,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 188,0
va (VaSet
)
xt "82000,57500,87800,58500"
st "SROUT_in_0"
blo "82000,58300"
)
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_0"
t "std_logic"
o 4
suid 52,0
)
)
)
*33 (CptPort
uid 189,0
ps "OnEdgeStrategy"
shape (Triangle
uid 190,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,58625,81000,59375"
)
tg (CPTG
uid 191,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 192,0
va (VaSet
)
xt "82000,58500,87700,59500"
st "SROUT_in_1"
blo "82000,59300"
)
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_1"
t "std_logic"
o 5
suid 53,0
)
)
)
*34 (CptPort
uid 193,0
ps "OnEdgeStrategy"
shape (Triangle
uid 194,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,59625,81000,60375"
)
tg (CPTG
uid 195,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 196,0
va (VaSet
)
xt "82000,59500,87800,60500"
st "SROUT_in_2"
blo "82000,60300"
)
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_2"
t "std_logic"
o 6
suid 54,0
)
)
)
*35 (CptPort
uid 197,0
ps "OnEdgeStrategy"
shape (Triangle
uid 198,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,60625,81000,61375"
)
tg (CPTG
uid 199,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 200,0
va (VaSet
)
xt "82000,60500,87800,61500"
st "SROUT_in_3"
blo "82000,61300"
)
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_3"
t "std_logic"
o 7
suid 55,0
)
)
)
*36 (CptPort
uid 201,0
ps "OnEdgeStrategy"
shape (Triangle
uid 202,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,63625,81000,64375"
)
tg (CPTG
uid 203,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 204,0
va (VaSet
)
xt "82000,63500,86200,64500"
st "RSRLOAD"
blo "82000,64300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "RSRLOAD"
t "std_logic"
o 23
suid 56,0
i "'0'"
)
)
)
*37 (CptPort
uid 205,0
ps "OnEdgeStrategy"
shape (Triangle
uid 206,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,64625,81000,65375"
)
tg (CPTG
uid 207,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 208,0
va (VaSet
)
xt "82000,64500,84900,65500"
st "SRCLK"
blo "82000,65300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "SRCLK"
t "std_logic"
o 24
suid 57,0
i "'0'"
)
)
)
*38 (CptPort
uid 209,0
ps "OnEdgeStrategy"
shape (Triangle
uid 210,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,50625,109750,51375"
)
tg (CPTG
uid 211,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 212,0
va (VaSet
)
xt "106100,50500,108000,51500"
st "sclk"
ju 2
blo "108000,51300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sclk"
t "std_logic"
o 42
suid 62,0
)
)
)
*39 (CptPort
uid 213,0
ps "OnEdgeStrategy"
shape (Diamond
uid 214,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,51625,109750,52375"
)
tg (CPTG
uid 215,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 216,0
va (VaSet
)
xt "106600,51500,108000,52500"
st "sio"
ju 2
blo "108000,52300"
)
)
thePort (LogicalPort
m 2
decl (Decl
n "sio"
t "std_logic"
preAdd 0
posAdd 0
o 52
suid 63,0
)
)
)
*40 (CptPort
uid 217,0
ps "OnEdgeStrategy"
shape (Triangle
uid 218,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,39625,109750,40375"
)
tg (CPTG
uid 219,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 220,0
va (VaSet
)
xt "105000,39500,108000,40500"
st "dac_cs"
ju 2
blo "108000,40300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dac_cs"
t "std_logic"
o 31
suid 64,0
)
)
)
*41 (CptPort
uid 221,0
ps "OnEdgeStrategy"
shape (Triangle
uid 222,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,41625,109750,42375"
)
tg (CPTG
uid 223,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 224,0
va (VaSet
)
xt "101000,41500,108000,42500"
st "sensor_cs : (3:0)"
ju 2
blo "108000,42300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sensor_cs"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 43
suid 65,0
)
)
)
*42 (CptPort
uid 225,0
ps "OnEdgeStrategy"
shape (Triangle
uid 226,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,52625,109750,53375"
)
tg (CPTG
uid 227,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 228,0
va (VaSet
)
xt "106000,52500,108000,53500"
st "mosi"
ju 2
blo "108000,53300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "mosi"
t "std_logic"
o 40
suid 66,0
i "'0'"
)
)
)
*43 (CptPort
uid 229,0
ps "OnEdgeStrategy"
shape (Triangle
uid 230,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,65625,81000,66375"
)
tg (CPTG
uid 231,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 232,0
va (VaSet
)
xt "82000,65500,85200,66500"
st "denable"
blo "82000,66300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "denable"
t "std_logic"
eolc "-- default domino wave off"
posAdd 0
o 34
suid 67,0
i "'0'"
)
)
)
*44 (CptPort
uid 1395,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1396,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,73625,109750,74375"
)
tg (CPTG
uid 1397,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1398,0
va (VaSet
)
xt "98000,73500,108000,74500"
st "alarm_refclk_too_high"
ju 2
blo "108000,74300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "alarm_refclk_too_high"
t "std_logic"
o 27
suid 95,0
)
)
)
*45 (CptPort
uid 1399,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1400,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,74625,109750,75375"
)
tg (CPTG
uid 1401,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1402,0
va (VaSet
)
xt "98400,74500,108000,75500"
st "alarm_refclk_too_low"
ju 2
blo "108000,75300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "alarm_refclk_too_low"
t "std_logic"
posAdd 0
o 28
suid 96,0
)
)
)
*46 (CptPort
uid 1403,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1404,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,79625,109750,80375"
)
tg (CPTG
uid 1405,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1406,0
va (VaSet
)
xt "105300,79500,108000,80500"
st "amber"
ju 2
blo "108000,80300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "amber"
t "std_logic"
o 29
suid 87,0
)
)
)
*47 (CptPort
uid 1407,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1408,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,76625,109750,77375"
)
tg (CPTG
uid 1409,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1410,0
va (VaSet
)
xt "98400,76500,108000,77500"
st "counter_result : (11:0)"
ju 2
blo "108000,77300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "counter_result"
t "std_logic_vector"
b "(11 DOWNTO 0)"
o 30
suid 94,0
)
)
)
*48 (CptPort
uid 1411,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1412,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,74625,81000,75375"
)
tg (CPTG
uid 1413,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1414,0
va (VaSet
)
xt "82000,74500,87500,75500"
st "D_T_in : (1:0)"
blo "82000,75300"
)
)
thePort (LogicalPort
decl (Decl
n "D_T_in"
t "std_logic_vector"
b "(1 DOWNTO 0)"
o 2
suid 91,0
)
)
)
*49 (CptPort
uid 1415,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1416,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,75625,81000,76375"
)
tg (CPTG
uid 1417,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1418,0
va (VaSet
)
xt "82000,75500,88100,76500"
st "drs_refclk_in"
blo "82000,76300"
)
)
thePort (LogicalPort
decl (Decl
n "drs_refclk_in"
t "std_logic"
eolc "-- used to check if DRS REFCLK exsists, if not DENABLE inhibit"
o 12
suid 92,0
)
)
)
*50 (CptPort
uid 1419,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1420,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,77625,109750,78375"
)
tg (CPTG
uid 1421,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1422,0
va (VaSet
)
xt "105600,77500,108000,78500"
st "green"
ju 2
blo "108000,78300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "green"
t "std_logic"
o 37
suid 86,0
)
)
)
*51 (CptPort
uid 1423,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1424,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,76625,81000,77375"
)
tg (CPTG
uid 1425,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1426,0
va (VaSet
)
xt "82000,76500,88700,77500"
st "plllock_in : (3:0)"
blo "82000,77300"
)
)
thePort (LogicalPort
decl (Decl
n "plllock_in"
t "std_logic_vector"
b "(3 DOWNTO 0)"
eolc "-- high level, if dominowave is running and DRS PLL locked"
o 13
suid 93,0
)
)
)
*52 (CptPort
uid 1427,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1428,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,78625,109750,79375"
)
tg (CPTG
uid 1429,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1430,0
va (VaSet
)
xt "106300,78500,108000,79500"
st "red"
ju 2
blo "108000,79300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "red"
t "std_logic"
o 41
suid 88,0
)
)
)
*53 (CptPort
uid 1431,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1432,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,71625,81000,72375"
)
tg (CPTG
uid 1433,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1434,0
va (VaSet
)
xt "82000,71500,86200,72500"
st "SRIN_out"
blo "82000,72300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "SRIN_out"
t "std_logic"
o 25
suid 85,0
i "'0'"
)
)
)
*54 (CptPort
uid 1678,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1679,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,23625,81000,24375"
)
tg (CPTG
uid 1680,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1681,0
va (VaSet
)
xt "82000,23500,86000,24500"
st "ADC_CLK"
blo "82000,24300"
)
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "ADC_CLK"
t "std_logic"
o 16
suid 97,0
)
)
)
*55 (CptPort
uid 2651,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2652,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,80625,109750,81375"
)
tg (CPTG
uid 2653,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2654,0
va (VaSet
)
xt "97600,80500,108000,81500"
st "debug_data_ram_empty"
ju 2
blo "108000,81300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "debug_data_ram_empty"
t "std_logic"
o 32
suid 104,0
)
)
)
*56 (CptPort
uid 2655,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2656,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,81625,109750,82375"
)
tg (CPTG
uid 2657,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2658,0
va (VaSet
)
xt "100500,81500,108000,82500"
st "debug_data_valid"
ju 2
blo "108000,82300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "debug_data_valid"
t "std_logic"
o 33
suid 105,0
)
)
)
*57 (CptPort
uid 2659,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2660,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,82625,109750,83375"
)
tg (CPTG
uid 2661,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2662,0
va (VaSet
)
xt "101100,82500,108000,83500"
st "DG_state : (7:0)"
ju 2
blo "108000,83300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "DG_state"
t "std_logic_vector"
b "(7 downto 0)"
prec "-- for debugging"
preAdd 0
o 19
suid 108,0
)
)
)
*58 (CptPort
uid 2663,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2664,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,77625,81000,78375"
)
tg (CPTG
uid 2665,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2666,0
va (VaSet
)
xt "82000,77500,90100,78500"
st "FTM_RS485_rx_d"
blo "82000,78300"
)
)
thePort (LogicalPort
decl (Decl
n "FTM_RS485_rx_d"
t "std_logic"
o 3
suid 99,0
)
)
)
*59 (CptPort
uid 2667,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2668,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,83625,109750,84375"
)
tg (CPTG
uid 2669,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2670,0
va (VaSet
)
xt "99600,83500,108000,84500"
st "FTM_RS485_rx_en"
ju 2
blo "108000,84300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "FTM_RS485_rx_en"
t "std_logic"
o 20
suid 101,0
)
)
)
*60 (CptPort
uid 2671,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2672,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,84625,109750,85375"
)
tg (CPTG
uid 2673,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2674,0
va (VaSet
)
xt "99900,84500,108000,85500"
st "FTM_RS485_tx_d"
ju 2
blo "108000,85300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "FTM_RS485_tx_d"
t "std_logic"
o 21
suid 100,0
)
)
)
*61 (CptPort
uid 2675,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2676,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,85625,109750,86375"
)
tg (CPTG
uid 2677,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2678,0
va (VaSet
)
xt "99600,85500,108000,86500"
st "FTM_RS485_tx_en"
ju 2
blo "108000,86300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "FTM_RS485_tx_en"
t "std_logic"
o 22
suid 102,0
)
)
)
*62 (CptPort
uid 2679,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2680,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,86625,109750,87375"
)
tg (CPTG
uid 2681,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2682,0
va (VaSet
)
xt "96600,86500,108000,87500"
st "mem_manager_state : (3:0)"
ju 2
blo "108000,87300"
)
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "mem_manager_state"
t "std_logic_vector"
b "(3 DOWNTO 0)"
eolc "-- state is encoded here ... useful for debugging."
posAdd 0
o 39
suid 106,0
)
)
)
*63 (CptPort
uid 2683,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2684,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,87625,109750,88375"
)
tg (CPTG
uid 2685,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2686,0
va (VaSet
)
xt "102400,87500,108000,88500"
st "trigger_veto"
ju 2
blo "108000,88300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "trigger_veto"
t "std_logic"
o 45
suid 98,0
i "'1'"
)
)
)
*64 (CptPort
uid 2687,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2688,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,88625,109750,89375"
)
tg (CPTG
uid 2689,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2690,0
va (VaSet
)
xt "99600,88500,108000,89500"
st "w5300_state : (7:0)"
ju 2
blo "108000,89300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "w5300_state"
t "std_logic_vector"
b "(7 DOWNTO 0)"
eolc "-- state is encoded here ... useful for debugging."
posAdd 0
o 46
suid 103,0
)
)
)
*65 (CptPort
uid 2924,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2925,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,89625,109750,90375"
)
tg (CPTG
uid 2926,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2927,0
va (VaSet
)
xt "96100,89500,108000,90500"
st "socket_tx_free_out : (16:0)"
ju 2
blo "108000,90300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "socket_tx_free_out"
t "std_logic_vector"
b "(16 DOWNTO 0)"
eolc "-- 17bit value .. that's true"
posAdd 0
o 44
suid 109,0
)
)
)
]
shape (Rectangle
uid 234,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "81000,19000,109000,91000"
)
oxt "15000,-8000,43000,46000"
ttg (MlTextGroup
uid 235,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*66 (Text
uid 236,0
va (VaSet
font "Arial,8,1"
)
xt "83200,81000,89400,82000"
st "FACT_FAD_lib"
blo "83200,81800"
tm "BdLibraryNameMgr"
)
*67 (Text
uid 237,0
va (VaSet
font "Arial,8,1"
)
xt "83200,82000,87400,83000"
st "FAD_main"
blo "83200,82800"
tm "CptNameMgr"
)
*68 (Text
uid 238,0
va (VaSet
font "Arial,8,1"
)
xt "83200,83000,90000,84000"
st "I_mainTB_FPGA"
blo "83200,83800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 239,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 240,0
text (MLText
uid 241,0
va (VaSet
font "Courier New,8,0"
)
xt "81000,18200,101000,19000"
st "RAMADDRWIDTH64b = 15    ( integer )  "
)
header ""
)
elements [
(GiElement
name "RAMADDRWIDTH64b"
type "integer"
value "15"
)
]
)
viewicon (ZoomableIcon
uid 242,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "81250,89250,82750,90750"
iconName "BlockDiagram.png"
iconMaskName "BlockDiagram.msk"
ftype 1
)
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*69 (SaComponent
uid 274,0
optionalChildren [
*70 (CptPort
uid 266,0
ps "OnEdgeStrategy"
shape (Triangle
uid 267,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "58000,20625,58750,21375"
)
tg (CPTG
uid 268,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 269,0
va (VaSet
)
xt "55700,20500,57000,21500"
st "clk"
ju 2
blo "57000,21300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "clk"
t "STD_LOGIC"
o 1
i "'0'"
)
)
)
*71 (CptPort
uid 270,0
ps "OnEdgeStrategy"
shape (Triangle
uid 271,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "58000,21625,58750,22375"
)
tg (CPTG
uid 272,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 273,0
va (VaSet
)
xt "55700,21500,57000,22500"
st "rst"
ju 2
blo "57000,22300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "rst"
t "STD_LOGIC"
o 2
i "'0'"
)
)
)
]
shape (Rectangle
uid 275,0
va (VaSet
vasetType 1
fg "0,49152,49152"
lineColor "0,0,50000"
lineWidth 2
)
xt "50000,19000,58000,24000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 276,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*72 (Text
uid 277,0
va (VaSet
font "Arial,8,1"
)
xt "50150,24000,57850,25000"
st "FACT_FAD_TB_lib"
blo "50150,24800"
tm "BdLibraryNameMgr"
)
*73 (Text
uid 278,0
va (VaSet
font "Arial,8,1"
)
xt "50150,25000,56850,26000"
st "clock_generator"
blo "50150,25800"
tm "CptNameMgr"
)
*74 (Text
uid 279,0
va (VaSet
font "Arial,8,1"
)
xt "50150,26000,56750,27000"
st "I_mainTB_clock"
blo "50150,26800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 280,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 281,0
text (MLText
uid 282,0
va (VaSet
font "Courier New,8,0"
)
xt "50000,17400,68500,19000"
st "clock_period = 20 ns    ( time )  
reset_time   = 50 ns    ( time )  "
)
header ""
)
elements [
(GiElement
name "clock_period"
type "time"
value "20 ns"
)
(GiElement
name "reset_time"
type "time"
value "50 ns"
)
]
)
viewicon (ZoomableIcon
uid 283,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "50250,22250,51750,23750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*75 (Net
uid 284,0
decl (Decl
n "clk"
t "STD_LOGIC"
preAdd 0
posAdd 0
o 1
suid 1,0
)
declText (MLText
uid 285,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,46200,-68000,47000"
st "SIGNAL clk                   : STD_LOGIC"
)
)
*76 (Net
uid 316,0
decl (Decl
n "wiz_addr"
t "std_logic_vector"
b "(9 DOWNTO 0)"
o 2
suid 2,0
)
declText (MLText
uid 317,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,63800,-58500,64600"
st "SIGNAL wiz_addr              : std_logic_vector(9 DOWNTO 0)"
)
)
*77 (Net
uid 322,0
decl (Decl
n "wiz_data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 3
suid 3,0
)
declText (MLText
uid 323,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,65400,-58000,66200"
st "SIGNAL wiz_data              : std_logic_vector(15 DOWNTO 0)"
)
)
*78 (Net
uid 328,0
decl (Decl
n "wiz_rd"
t "std_logic"
o 4
suid 4,0
i "'1'"
)
declText (MLText
uid 329,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,67000,-55000,67800"
st "SIGNAL wiz_rd                : std_logic                    := '1'"
)
)
*79 (Net
uid 334,0
decl (Decl
n "wiz_wr"
t "std_logic"
o 5
suid 5,0
i "'1'"
)
declText (MLText
uid 335,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,68600,-55000,69400"
st "SIGNAL wiz_wr                : std_logic                    := '1'"
)
)
*80 (SaComponent
uid 362,0
optionalChildren [
*81 (CptPort
uid 350,0
ps "OnEdgeStrategy"
shape (Triangle
uid 351,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "122250,50625,123000,51375"
)
tg (CPTG
uid 352,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 353,0
va (VaSet
)
xt "124000,50500,125700,51500"
st "sclk"
blo "124000,51300"
)
)
thePort (LogicalPort
decl (Decl
n "sclk"
t "std_logic"
preAdd 0
posAdd 0
o 1
suid 1,0
)
)
)
*82 (CptPort
uid 354,0
ps "OnEdgeStrategy"
shape (Diamond
uid 355,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "122250,51625,123000,52375"
)
tg (CPTG
uid 356,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 357,0
va (VaSet
)
xt "124000,51500,125400,52500"
st "sio"
blo "124000,52300"
)
)
thePort (LogicalPort
m 2
decl (Decl
n "sio"
t "std_logic"
preAdd 0
posAdd 0
o 2
suid 2,0
)
)
)
*83 (CptPort
uid 358,0
ps "OnEdgeStrategy"
shape (Triangle
uid 359,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "122250,47625,123000,48375"
)
tg (CPTG
uid 360,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 361,0
va (VaSet
)
xt "124000,47500,130500,48500"
st "sensor_cs : (3:0)"
blo "124000,48300"
)
)
thePort (LogicalPort
decl (Decl
n "sensor_cs"
t "std_logic_vector"
b "(3 downto 0)"
preAdd 0
posAdd 0
o 3
suid 3,0
)
)
)
]
shape (Rectangle
uid 363,0
va (VaSet
vasetType 1
fg "0,49152,49152"
lineColor "0,0,50000"
lineWidth 2
)
xt "123000,46000,133000,56000"
)
oxt "30000,3000,40000,13000"
ttg (MlTextGroup
uid 364,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*84 (Text
uid 365,0
va (VaSet
font "Arial,8,1"
)
xt "123200,56000,130900,57000"
st "FACT_FAD_TB_lib"
blo "123200,56800"
tm "BdLibraryNameMgr"
)
*85 (Text
uid 366,0
va (VaSet
font "Arial,8,1"
)
xt "123200,57000,130800,58000"
st "max6662_emulator"
blo "123200,57800"
tm "CptNameMgr"
)
*86 (Text
uid 367,0
va (VaSet
font "Arial,8,1"
)
xt "123200,58000,131000,59000"
st "I_mainTB_max6662"
blo "123200,58800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 368,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 369,0
text (MLText
uid 370,0
va (VaSet
font "Courier New,8,0"
)
xt "123000,45200,143000,46000"
st "DRS_TEMPERATURE = 51    ( integer )  "
)
header ""
)
elements [
(GiElement
name "DRS_TEMPERATURE"
type "integer"
value "51"
)
]
)
viewicon (ZoomableIcon
uid 371,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "123250,54250,124750,55750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
sIVOD 1
)
archFileType "UNKNOWN"
)
*87 (Net
uid 372,0
decl (Decl
n "sensor_cs"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 6
suid 6,0
)
declText (MLText
uid 373,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,59000,-58500,59800"
st "SIGNAL sensor_cs             : std_logic_vector(3 DOWNTO 0)"
)
)
*88 (Net
uid 378,0
decl (Decl
n "sclk"
t "std_logic"
o 7
suid 7,0
)
declText (MLText
uid 379,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,58200,-68000,59000"
st "SIGNAL sclk                  : std_logic"
)
)
*89 (Net
uid 384,0
decl (Decl
n "sio"
t "std_logic"
preAdd 0
posAdd 0
o 8
suid 8,0
)
declText (MLText
uid 385,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,59800,-68000,60600"
st "SIGNAL sio                   : std_logic"
)
)
*90 (SaComponent
uid 414,0
optionalChildren [
*91 (CptPort
uid 410,0
ps "OnEdgeStrategy"
shape (Triangle
uid 411,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "58000,31625,58750,32375"
)
tg (CPTG
uid 412,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 413,0
va (VaSet
)
xt "54200,31500,57000,32500"
st "trigger"
ju 2
blo "57000,32300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "trigger"
t "std_logic"
preAdd 0
posAdd 0
o 1
suid 1,0
)
)
)
]
shape (Rectangle
uid 415,0
va (VaSet
vasetType 1
fg "0,49152,49152"
lineColor "0,0,50000"
lineWidth 2
)
xt "50000,30000,58000,36000"
)
oxt "19000,4000,29000,14000"
ttg (MlTextGroup
uid 416,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*92 (Text
uid 417,0
va (VaSet
font "Arial,8,1"
)
xt "50200,36000,57900,37000"
st "FACT_FAD_TB_lib"
blo "50200,36800"
tm "BdLibraryNameMgr"
)
*93 (Text
uid 418,0
va (VaSet
font "Arial,8,1"
)
xt "50200,37000,57500,38000"
st "trigger_generator"
blo "50200,37800"
tm "CptNameMgr"
)
*94 (Text
uid 419,0
va (VaSet
font "Arial,8,1"
)
xt "50200,38000,57400,39000"
st "I_mainTB_trigger"
blo "50200,38800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 420,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 421,0
text (MLText
uid 422,0
va (VaSet
font "Courier New,8,0"
)
xt "50000,28400,68500,30000"
st "TRIGGER_RATE = 1 ms     ( time )  
PULSE_WIDTH  = 20 ns    ( time )  "
)
header ""
)
elements [
(GiElement
name "TRIGGER_RATE"
type "time"
value "1 ms"
)
(GiElement
name "PULSE_WIDTH"
type "time"
value "20 ns"
)
]
)
viewicon (ZoomableIcon
uid 423,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "50250,34250,51750,35750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
sIVOD 1
)
archFileType "UNKNOWN"
)
*95 (Net
uid 424,0
decl (Decl
n "trigger"
t "std_logic"
preAdd 0
posAdd 0
o 9
suid 9,0
)
declText (MLText
uid 425,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,61400,-68000,62200"
st "SIGNAL trigger               : std_logic"
)
)
*96 (HdlText
uid 430,0
optionalChildren [
*97 (EmbeddedText
uid 436,0
commentText (CommentText
uid 437,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 438,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "50000,45000,60000,49000"
)
oxt "0,0,18000,5000"
text (MLText
uid 439,0
va (VaSet
)
xt "50200,45200,60200,48200"
st "
-- eb_ID 1: hard-wired IDs
board_id <= \"0101\";
crate_id <= \"01\";

"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 4000
visibleWidth 10000
)
)
)
]
shape (Rectangle
uid 431,0
va (VaSet
vasetType 1
fg "65535,65535,37120"
lineColor "0,0,32768"
lineWidth 2
)
xt "50000,40000,58000,45000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 432,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*98 (Text
uid 433,0
va (VaSet
font "Arial,8,1"
)
xt "51150,41000,57350,42000"
st "eb_mainTB_ID"
blo "51150,41800"
tm "HdlTextNameMgr"
)
*99 (Text
uid 434,0
va (VaSet
font "Arial,8,1"
)
xt "51150,42000,51950,43000"
st "1"
blo "51150,42800"
tm "HdlTextNumberMgr"
)
]
)
viewicon (ZoomableIcon
uid 435,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "50250,43250,51750,44750"
iconName "TextFile.png"
iconMaskName "TextFile.msk"
ftype 21
)
viewiconposition 0
)
*100 (Net
uid 440,0
decl (Decl
n "board_id"
t "std_logic_vector"
b "(3 downto 0)"
preAdd 0
posAdd 0
o 10
suid 10,0
)
declText (MLText
uid 441,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,45400,-58500,46200"
st "SIGNAL board_id              : std_logic_vector(3 downto 0)"
)
)
*101 (Net
uid 448,0
decl (Decl
n "crate_id"
t "std_logic_vector"
b "(1 downto 0)"
o 11
suid 11,0
)
declText (MLText
uid 449,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,47800,-58500,48600"
st "SIGNAL crate_id              : std_logic_vector(1 downto 0)"
)
)
*102 (SaComponent
uid 508,0
optionalChildren [
*103 (CptPort
uid 489,0
ps "OnEdgeStrategy"
shape (Triangle
uid 490,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "29250,52625,30000,53375"
)
tg (CPTG
uid 491,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 492,0
va (VaSet
)
xt "31000,52500,32300,53500"
st "clk"
blo "31000,53300"
)
)
thePort (LogicalPort
decl (Decl
n "clk"
t "STD_LOGIC"
preAdd 0
posAdd 0
o 1
suid 1,0
)
)
)
*104 (CptPort
uid 493,0
ps "OnEdgeStrategy"
shape (Triangle
uid 494,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,54625,40750,55375"
)
tg (CPTG
uid 495,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 496,0
va (VaSet
)
xt "34200,54500,39000,55500"
st "data : (11:0)"
ju 2
blo "39000,55300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "data"
t "STD_LOGIC_VECTOR"
b "(11 DOWNTO 0)"
preAdd 0
posAdd 0
o 2
suid 2,0
)
)
)
*105 (CptPort
uid 497,0
ps "OnEdgeStrategy"
shape (Triangle
uid 498,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,52625,40750,53375"
)
tg (CPTG
uid 499,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 500,0
va (VaSet
)
xt "37700,52500,39000,53500"
st "otr"
ju 2
blo "39000,53300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "otr"
t "STD_LOGIC"
preAdd 0
posAdd 0
o 3
suid 3,0
)
)
)
*106 (CptPort
uid 501,0
ps "OnEdgeStrategy"
shape (Triangle
uid 502,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,53625,40750,54375"
)
tg (CPTG
uid 503,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 504,0
va (VaSet
)
xt "37400,53500,39000,54500"
st "oeb"
ju 2
blo "39000,54300"
)
)
thePort (LogicalPort
decl (Decl
n "oeb"
t "STD_LOGIC"
preAdd 0
posAdd 0
o 4
suid 4,0
)
)
)
]
shape (Rectangle
uid 509,0
va (VaSet
vasetType 1
fg "0,49152,49152"
lineColor "0,0,50000"
lineWidth 2
)
xt "30000,51000,40000,58000"
)
oxt "29000,7000,39000,17000"
ttg (MlTextGroup
uid 510,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*107 (Text
uid 511,0
va (VaSet
font "Arial,8,1"
)
xt "30200,58000,37900,59000"
st "FACT_FAD_TB_lib"
blo "30200,58800"
tm "BdLibraryNameMgr"
)
*108 (Text
uid 512,0
va (VaSet
font "Arial,8,1"
)
xt "30200,59000,36000,60000"
st "adc_emulator"
blo "30200,59800"
tm "CptNameMgr"
)
*109 (Text
uid 513,0
va (VaSet
font "Arial,8,1"
)
xt "30200,60000,36200,61000"
st "I_mainTB_adc"
blo "30200,60800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 514,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 515,0
text (MLText
uid 516,0
va (VaSet
font "Courier New,8,0"
)
xt "30000,50200,65500,51000"
st "INPUT_FILE = \"../memory_files/analog_input_ch0.txt\"    ( string )  "
)
header ""
)
elements [
(GiElement
name "INPUT_FILE"
type "string"
value "\"../memory_files/analog_input_ch0.txt\""
)
]
)
viewicon (ZoomableIcon
uid 517,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "30250,56250,31750,57750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
sIVOD 1
)
archFileType "UNKNOWN"
)
*110 (HdlText
uid 518,0
optionalChildren [
*111 (EmbeddedText
uid 524,0
commentText (CommentText
uid 525,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 526,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "50000,57000,62000,67000"
)
oxt "0,0,18000,5000"
text (MLText
uid 527,0
va (VaSet
)
xt "50200,57200,62100,66200"
st "
-- eb_adc 2: ADC routing
adc_data_array(0) <= adc_data;
adc_data_array(1) <= adc_data;
adc_data_array(2) <= adc_data;
adc_data_array(3) <= adc_data;
adc_otr_array(0) <= adc_otr;
adc_otr_array(1) <= adc_otr;
adc_otr_array(2) <= adc_otr;
adc_otr_array(3) <= adc_otr;

"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 10000
visibleWidth 12000
)
)
)
]
shape (Rectangle
uid 519,0
va (VaSet
vasetType 1
fg "65535,65535,37120"
lineColor "0,0,32768"
lineWidth 2
)
xt "50000,51000,58000,57000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 520,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*112 (Text
uid 521,0
va (VaSet
font "Arial,8,1"
)
xt "51150,52000,57850,53000"
st "eb_mainTB_adc"
blo "51150,52800"
tm "HdlTextNameMgr"
)
*113 (Text
uid 522,0
va (VaSet
font "Arial,8,1"
)
xt "51150,53000,51950,54000"
st "2"
blo "51150,53800"
tm "HdlTextNumberMgr"
)
]
)
viewicon (ZoomableIcon
uid 523,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "50250,55250,51750,56750"
iconName "TextFile.png"
iconMaskName "TextFile.msk"
ftype 21
)
viewiconposition 0
)
*114 (Net
uid 528,0
decl (Decl
n "adc_otr_array"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 12
suid 12,0
)
declText (MLText
uid 529,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,42200,-58500,43000"
st "SIGNAL adc_otr_array         : std_logic_vector(3 DOWNTO 0)"
)
)
*115 (Net
uid 536,0
decl (Decl
n "adc_data_array"
t "adc_data_array_type"
o 13
suid 13,0
)
declText (MLText
uid 537,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,39800,-63000,40600"
st "SIGNAL adc_data_array        : adc_data_array_type"
)
)
*116 (Net
uid 544,0
decl (Decl
n "adc_oeb"
t "std_logic"
preAdd 0
posAdd 0
o 14
suid 14,0
)
declText (MLText
uid 545,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,40600,-68000,41400"
st "SIGNAL adc_oeb               : std_logic"
)
)
*117 (Net
uid 560,0
decl (Decl
n "adc_otr"
t "STD_LOGIC"
preAdd 0
posAdd 0
o 16
suid 16,0
)
declText (MLText
uid 561,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,41400,-68000,42200"
st "SIGNAL adc_otr               : STD_LOGIC"
)
)
*118 (Net
uid 568,0
decl (Decl
n "adc_data"
t "std_logic_vector"
b "(11 DOWNTO 0)"
preAdd 0
posAdd 0
o 17
suid 17,0
)
declText (MLText
uid 569,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,39000,-58000,39800"
st "SIGNAL adc_data              : std_logic_vector(11 DOWNTO 0)"
)
)
*119 (Net
uid 767,0
decl (Decl
n "wiz_reset"
t "std_logic"
o 21
suid 23,0
i "'1'"
)
declText (MLText
uid 768,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,67800,-55000,68600"
st "SIGNAL wiz_reset             : std_logic                    := '1'"
)
)
*120 (Net
uid 775,0
decl (Decl
n "led"
t "std_logic_vector"
b "(7 DOWNTO 0)"
posAdd 0
o 22
suid 24,0
i "(OTHERS => '0')"
)
declText (MLText
uid 776,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,54200,-49000,55000"
st "SIGNAL led                   : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')"
)
)
*121 (Net
uid 783,0
decl (Decl
n "wiz_cs"
t "std_logic"
o 23
suid 25,0
i "'1'"
)
declText (MLText
uid 784,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,64600,-55000,65400"
st "SIGNAL wiz_cs                : std_logic                    := '1'"
)
)
*122 (Net
uid 791,0
decl (Decl
n "wiz_int"
t "std_logic"
o 24
suid 26,0
)
declText (MLText
uid 792,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,66200,-68000,67000"
st "SIGNAL wiz_int               : std_logic"
)
)
*123 (Net
uid 799,0
decl (Decl
n "dac_cs"
t "std_logic"
o 25
suid 27,0
)
declText (MLText
uid 800,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,48600,-68000,49400"
st "SIGNAL dac_cs                : std_logic"
)
)
*124 (Net
uid 807,0
decl (Decl
n "mosi"
t "std_logic"
o 26
suid 28,0
i "'0'"
)
declText (MLText
uid 808,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,55800,-55000,56600"
st "SIGNAL mosi                  : std_logic                    := '0'"
)
)
*125 (Net
uid 815,0
decl (Decl
n "denable"
t "std_logic"
eolc "-- default domino wave off"
posAdd 0
o 27
suid 29,0
i "'0'"
)
declText (MLText
uid 816,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,51000,-41500,51800"
st "SIGNAL denable               : std_logic                    := '0' -- default domino wave off"
)
)
*126 (Net
uid 823,0
decl (Decl
n "CLK_25_PS"
t "std_logic"
o 28
suid 30,0
)
declText (MLText
uid 824,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,25400,-68000,26200"
st "SIGNAL CLK_25_PS             : std_logic"
)
)
*127 (Net
uid 831,0
decl (Decl
n "CLK_50"
t "std_logic"
o 29
suid 31,0
)
declText (MLText
uid 832,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,26200,-68000,27000"
st "SIGNAL CLK_50                : std_logic"
)
)
*128 (Net
uid 839,0
decl (Decl
n "drs_channel_id"
t "std_logic_vector"
b "(3 downto 0)"
o 30
suid 32,0
i "(others => '0')"
)
declText (MLText
uid 840,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,51800,-49000,52600"
st "SIGNAL drs_channel_id        : std_logic_vector(3 downto 0) := (others => '0')"
)
)
*129 (Net
uid 847,0
decl (Decl
n "drs_dwrite"
t "std_logic"
o 31
suid 33,0
i "'1'"
)
declText (MLText
uid 848,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,52600,-55000,53400"
st "SIGNAL drs_dwrite            : std_logic                    := '1'"
)
)
*130 (Net
uid 855,0
decl (Decl
n "RSRLOAD"
t "std_logic"
o 32
suid 34,0
i "'0'"
)
declText (MLText
uid 856,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,33400,-55000,34200"
st "SIGNAL RSRLOAD               : std_logic                    := '0'"
)
)
*131 (Net
uid 863,0
decl (Decl
n "SRCLK"
t "std_logic"
o 33
suid 35,0
i "'0'"
)
declText (MLText
uid 864,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,34200,-55000,35000"
st "SIGNAL SRCLK                 : std_logic                    := '0'"
)
)
*132 (Net
uid 871,0
decl (Decl
n "SROUT_in_0"
t "std_logic"
o 30
suid 36,0
)
declText (MLText
uid 872,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,35800,-68000,36600"
st "SIGNAL SROUT_in_0            : std_logic"
)
)
*133 (Net
uid 879,0
decl (Decl
n "SROUT_in_1"
t "std_logic"
o 31
suid 37,0
)
declText (MLText
uid 880,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,36600,-68000,37400"
st "SIGNAL SROUT_in_1            : std_logic"
)
)
*134 (Net
uid 887,0
decl (Decl
n "SROUT_in_2"
t "std_logic"
o 32
suid 38,0
)
declText (MLText
uid 888,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,37400,-68000,38200"
st "SIGNAL SROUT_in_2            : std_logic"
)
)
*135 (Net
uid 895,0
decl (Decl
n "SROUT_in_3"
t "std_logic"
o 33
suid 39,0
)
declText (MLText
uid 896,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,38200,-68000,39000"
st "SIGNAL SROUT_in_3            : std_logic"
)
)
*136 (Net
uid 1435,0
decl (Decl
n "SRIN_out"
t "std_logic"
o 34
suid 40,0
i "'0'"
)
declText (MLText
uid 1436,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,35000,-55000,35800"
st "SIGNAL SRIN_out              : std_logic                    := '0'"
)
)
*137 (Net
uid 1443,0
decl (Decl
n "amber"
t "std_logic"
o 35
suid 41,0
)
declText (MLText
uid 1444,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,44600,-68000,45400"
st "SIGNAL amber                 : std_logic"
)
)
*138 (Net
uid 1451,0
decl (Decl
n "red"
t "std_logic"
o 36
suid 42,0
)
declText (MLText
uid 1452,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,57400,-68000,58200"
st "SIGNAL red                   : std_logic"
)
)
*139 (Net
uid 1459,0
decl (Decl
n "green"
t "std_logic"
o 37
suid 43,0
)
declText (MLText
uid 1460,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,53400,-68000,54200"
st "SIGNAL green                 : std_logic"
)
)
*140 (Net
uid 1467,0
decl (Decl
n "counter_result"
t "std_logic_vector"
b "(11 DOWNTO 0)"
o 38
suid 44,0
)
declText (MLText
uid 1468,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,47000,-58000,47800"
st "SIGNAL counter_result        : std_logic_vector(11 DOWNTO 0)"
)
)
*141 (Net
uid 1475,0
decl (Decl
n "alarm_refclk_too_low"
t "std_logic"
posAdd 0
o 39
suid 45,0
)
declText (MLText
uid 1476,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,43800,-68000,44600"
st "SIGNAL alarm_refclk_too_low  : std_logic"
)
)
*142 (Net
uid 1483,0
decl (Decl
n "alarm_refclk_too_high"
t "std_logic"
o 40
suid 46,0
)
declText (MLText
uid 1484,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,43000,-68000,43800"
st "SIGNAL alarm_refclk_too_high : std_logic"
)
)
*143 (HdlText
uid 1491,0
optionalChildren [
*144 (EmbeddedText
uid 1497,0
commentText (CommentText
uid 1498,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 1499,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "27000,72000,41000,77000"
)
oxt "0,0,18000,5000"
text (MLText
uid 1500,0
va (VaSet
)
xt "27200,72200,39400,77200"
st "

D_T_in(1 downto 0) <= \"00\";
plllock_in(3 downto 0) <= \"1111\";
SROUT_in_0 <= '1';
SROUT_in_1 <= '0';
SROUT_in_2 <= '1';
SROUT_in_3 <= '0';

"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 5000
visibleWidth 14000
)
)
)
]
shape (Rectangle
uid 1492,0
va (VaSet
vasetType 1
fg "65535,65535,37120"
lineColor "0,0,32768"
lineWidth 2
)
xt "27000,69000,35000,72000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 1493,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*145 (Text
uid 1494,0
va (VaSet
font "Arial,8,1"
)
xt "28150,69000,35250,70000"
st "eb_mainTB_adc1"
blo "28150,69800"
tm "HdlTextNameMgr"
)
*146 (Text
uid 1495,0
va (VaSet
font "Arial,8,1"
)
xt "28150,70000,28950,71000"
st "3"
blo "28150,70800"
tm "HdlTextNumberMgr"
)
]
)
viewicon (ZoomableIcon
uid 1496,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "27250,70250,28750,71750"
iconName "TextFile.png"
iconMaskName "TextFile.msk"
ftype 21
)
viewiconposition 0
)
*147 (Net
uid 1501,0
decl (Decl
n "D_T_in"
t "std_logic_vector"
b "(1 DOWNTO 0)"
o 41
suid 47,0
)
declText (MLText
uid 1502,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,28600,-58500,29400"
st "SIGNAL D_T_in                : std_logic_vector(1 DOWNTO 0)"
)
)
*148 (SaComponent
uid 1509,0
optionalChildren [
*149 (CptPort
uid 1519,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1520,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "66000,78625,66750,79375"
)
tg (CPTG
uid 1521,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1522,0
va (VaSet
)
xt "63700,78500,65000,79500"
st "clk"
ju 2
blo "65000,79300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "clk"
t "STD_LOGIC"
o 1
i "'0'"
)
)
)
*150 (CptPort
uid 1523,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1524,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "66000,79625,66750,80375"
)
tg (CPTG
uid 1525,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1526,0
va (VaSet
)
xt "63700,79500,65000,80500"
st "rst"
ju 2
blo "65000,80300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "rst"
t "STD_LOGIC"
o 2
i "'0'"
)
)
)
]
shape (Rectangle
uid 1510,0
va (VaSet
vasetType 1
fg "0,49152,49152"
lineColor "0,0,50000"
lineWidth 2
)
xt "55000,77000,66000,82000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 1511,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*151 (Text
uid 1512,0
va (VaSet
font "Arial,8,1"
)
xt "56150,78000,63850,79000"
st "FACT_FAD_TB_lib"
blo "56150,78800"
tm "BdLibraryNameMgr"
)
*152 (Text
uid 1513,0
va (VaSet
font "Arial,8,1"
)
xt "56150,79000,62850,80000"
st "clock_generator"
blo "56150,79800"
tm "CptNameMgr"
)
*153 (Text
uid 1514,0
va (VaSet
font "Arial,8,1"
)
xt "56150,80000,63150,81000"
st "I_mainTB_clock1"
blo "56150,80800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1515,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1516,0
text (MLText
uid 1517,0
va (VaSet
font "Courier New,8,0"
)
xt "55000,82400,73000,84000"
st "clock_period = 1 us    ( time )  
reset_time   = 1 us    ( time )  "
)
header ""
)
elements [
(GiElement
name "clock_period"
type "time"
value "1 us"
)
(GiElement
name "reset_time"
type "time"
value "1 us"
)
]
)
viewicon (ZoomableIcon
uid 1518,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "55250,80250,56750,81750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*154 (Net
uid 1559,0
decl (Decl
n "plllock_in"
t "std_logic_vector"
b "(3 DOWNTO 0)"
eolc "-- high level, if dominowave is running and DRS PLL locked"
o 43
suid 49,0
)
declText (MLText
uid 1560,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,56600,-29000,57400"
st "SIGNAL plllock_in            : std_logic_vector(3 DOWNTO 0) -- high level, if dominowave is running and DRS PLL locked"
)
)
*155 (Net
uid 1682,0
lang 2
decl (Decl
n "ADC_CLK"
t "std_logic"
o 44
suid 50,0
)
declText (MLText
uid 1683,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,24600,-68000,25400"
st "SIGNAL ADC_CLK               : std_logic"
)
)
*156 (Net
uid 2001,0
decl (Decl
n "REF_CLK"
t "STD_LOGIC"
o 42
suid 51,0
i "'0'"
)
declText (MLText
uid 2002,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,32600,-55000,33400"
st "SIGNAL REF_CLK               : STD_LOGIC                    := '0'"
)
)
*157 (SaComponent
uid 2336,0
optionalChildren [
*158 (CptPort
uid 2315,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2316,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "122250,20625,123000,21375"
)
tg (CPTG
uid 2317,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2318,0
va (VaSet
)
xt "124000,20500,129100,21500"
st "addr : (9:0)"
blo "124000,21300"
)
)
thePort (LogicalPort
decl (Decl
n "addr"
t "std_logic_vector"
b "(9 DOWNTO 0)"
preAdd 0
posAdd 0
o 2
suid 1,0
)
)
)
*159 (CptPort
uid 2319,0
ps "OnEdgeStrategy"
shape (Diamond
uid 2320,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "122250,21625,123000,22375"
)
tg (CPTG
uid 2321,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2322,0
va (VaSet
)
xt "124000,21500,129400,22500"
st "data : (15:0)"
blo "124000,22300"
)
)
thePort (LogicalPort
m 2
decl (Decl
n "data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
preAdd 0
posAdd 0
o 3
suid 2,0
)
)
)
*160 (CptPort
uid 2323,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2324,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "122250,24625,123000,25375"
)
tg (CPTG
uid 2325,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2326,0
va (VaSet
)
xt "124000,24500,125300,25500"
st "rd"
blo "124000,25300"
)
)
thePort (LogicalPort
decl (Decl
n "rd"
t "std_logic"
preAdd 0
posAdd 0
o 4
suid 3,0
)
)
)
*161 (CptPort
uid 2327,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2328,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "122250,25625,123000,26375"
)
tg (CPTG
uid 2329,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2330,0
va (VaSet
)
xt "124000,25500,125400,26500"
st "wr"
blo "124000,26300"
)
)
thePort (LogicalPort
decl (Decl
n "wr"
t "std_logic"
preAdd 0
posAdd 0
o 6
suid 4,0
)
)
)
*162 (CptPort
uid 2331,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2332,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "122250,26625,123000,27375"
)
tg (CPTG
uid 2333,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2334,0
va (VaSet
)
xt "124000,26500,125400,27500"
st "int"
blo "124000,27300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "int"
t "std_logic"
o 1
suid 5,0
i "'1'"
)
)
)
*163 (CptPort
uid 2548,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2549,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "122250,27625,123000,28375"
)
tg (CPTG
uid 2550,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2551,0
va (VaSet
)
xt "124000,27500,125200,28500"
st "cs"
blo "124000,28300"
)
)
thePort (LogicalPort
decl (Decl
n "cs"
t "std_logic"
o 5
suid 6,0
)
)
)
]
shape (Rectangle
uid 2337,0
va (VaSet
vasetType 1
fg "0,49152,49152"
lineColor "0,0,50000"
lineWidth 2
)
xt "123000,19000,133000,31000"
)
oxt "29000,0,39000,12000"
ttg (MlTextGroup
uid 2338,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*164 (Text
uid 2339,0
va (VaSet
font "Arial,8,1"
)
xt "123200,31000,130900,32000"
st "FACT_FAD_TB_lib"
blo "123200,31800"
tm "BdLibraryNameMgr"
)
*165 (Text
uid 2340,0
va (VaSet
font "Arial,8,1"
)
xt "123200,32000,129800,33000"
st "w5300_emulator"
blo "123200,32800"
tm "CptNameMgr"
)
*166 (Text
uid 2341,0
va (VaSet
font "Arial,8,1"
)
xt "123200,33000,130000,34000"
st "I_mainTB_w5300"
blo "123200,33800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 2342,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 2343,0
text (MLText
uid 2344,0
va (VaSet
font "Courier New,8,0"
)
xt "123000,18000,123000,18000"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 2345,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "123250,29250,124750,30750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*167 (Net
uid 2705,0
decl (Decl
n "debug_data_ram_empty"
t "std_logic"
o 45
suid 53,0
)
declText (MLText
uid 2706,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,49400,-68000,50200"
st "SIGNAL debug_data_ram_empty  : std_logic"
)
)
*168 (Net
uid 2713,0
decl (Decl
n "debug_data_valid"
t "std_logic"
o 46
suid 54,0
)
declText (MLText
uid 2714,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,50200,-68000,51000"
st "SIGNAL debug_data_valid      : std_logic"
)
)
*169 (Net
uid 2721,0
decl (Decl
n "DG_state"
t "std_logic_vector"
b "(7 downto 0)"
prec "-- for debugging"
preAdd 0
o 47
suid 55,0
)
declText (MLText
uid 2722,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,27000,-58500,28600"
st "-- for debugging
SIGNAL DG_state              : std_logic_vector(7 downto 0)"
)
)
*170 (Net
uid 2729,0
decl (Decl
n "FTM_RS485_rx_en"
t "std_logic"
o 48
suid 56,0
)
declText (MLText
uid 2730,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,30200,-68000,31000"
st "SIGNAL FTM_RS485_rx_en       : std_logic"
)
)
*171 (Net
uid 2737,0
decl (Decl
n "FTM_RS485_tx_d"
t "std_logic"
o 49
suid 57,0
)
declText (MLText
uid 2738,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,31000,-68000,31800"
st "SIGNAL FTM_RS485_tx_d        : std_logic"
)
)
*172 (Net
uid 2745,0
decl (Decl
n "FTM_RS485_tx_en"
t "std_logic"
o 50
suid 58,0
)
declText (MLText
uid 2746,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,31800,-68000,32600"
st "SIGNAL FTM_RS485_tx_en       : std_logic"
)
)
*173 (Net
uid 2753,0
lang 2
decl (Decl
n "mem_manager_state"
t "std_logic_vector"
b "(3 DOWNTO 0)"
eolc "-- state is encoded here ... useful for debugging."
posAdd 0
o 51
suid 59,0
)
declText (MLText
uid 2754,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,55000,-33000,55800"
st "SIGNAL mem_manager_state     : std_logic_vector(3 DOWNTO 0) -- state is encoded here ... useful for debugging."
)
)
*174 (Net
uid 2761,0
decl (Decl
n "trigger_veto"
t "std_logic"
o 52
suid 60,0
i "'1'"
)
declText (MLText
uid 2762,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,62200,-55000,63000"
st "SIGNAL trigger_veto          : std_logic                    := '1'"
)
)
*175 (Net
uid 2769,0
decl (Decl
n "w5300_state"
t "std_logic_vector"
b "(7 DOWNTO 0)"
eolc "-- state is encoded here ... useful for debugging."
posAdd 0
o 53
suid 61,0
)
declText (MLText
uid 2770,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,63000,-33000,63800"
st "SIGNAL w5300_state           : std_logic_vector(7 DOWNTO 0) -- state is encoded here ... useful for debugging."
)
)
*176 (Net
uid 2777,0
decl (Decl
n "FTM_RS485_rx_d"
t "std_logic"
o 54
suid 62,0
)
declText (MLText
uid 2778,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,29400,-68000,30200"
st "SIGNAL FTM_RS485_rx_d        : std_logic"
)
)
*177 (Net
uid 2942,0
decl (Decl
n "socket_tx_free_out"
t "std_logic_vector"
b "(16 DOWNTO 0)"
eolc "-- 17bit value .. that's true"
posAdd 0
o 55
suid 64,0
)
declText (MLText
uid 2943,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,60600,-43000,61400"
st "SIGNAL socket_tx_free_out    : std_logic_vector(16 DOWNTO 0) -- 17bit value .. that's true"
)
)
*178 (SaComponent
uid 3285,0
optionalChildren [
*179 (CptPort
uid 3073,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3074,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "168000,19625,168750,20375"
)
tg (CPTG
uid 3075,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3076,0
va (VaSet
)
xt "163400,19500,167000,20500"
st "wiz_reset"
ju 2
blo "167000,20300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "wiz_reset"
t "std_logic"
o 50
suid 2,0
i "'1'"
)
)
)
*180 (CptPort
uid 3077,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3078,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "168000,65625,168750,66375"
)
tg (CPTG
uid 3079,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3080,0
va (VaSet
)
xt "163000,65500,167000,66500"
st "led : (7:0)"
ju 2
blo "167000,66300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "led"
t "std_logic_vector"
b "(7 DOWNTO 0)"
posAdd 0
o 38
suid 7,0
i "(OTHERS => '0')"
)
)
)
*181 (CptPort
uid 3081,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3082,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "139250,27625,140000,28375"
)
tg (CPTG
uid 3083,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3084,0
va (VaSet
)
xt "141000,27500,143800,28500"
st "trigger"
blo "141000,28300"
)
)
thePort (LogicalPort
decl (Decl
n "trigger"
t "std_logic"
preAdd 0
posAdd 0
o 14
suid 18,0
)
)
)
*182 (CptPort
uid 3085,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3086,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "139250,38625,140000,39375"
)
tg (CPTG
uid 3087,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3088,0
va (VaSet
)
xt "141000,38500,144200,39500"
st "adc_oeb"
blo "141000,39300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "adc_oeb"
t "std_logic"
o 26
suid 21,0
i "'1'"
)
)
)
*183 (CptPort
uid 3089,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3090,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "139250,29625,140000,30375"
)
tg (CPTG
uid 3091,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3092,0
va (VaSet
)
xt "141000,29500,146900,30500"
st "board_id : (3:0)"
blo "141000,30300"
)
)
thePort (LogicalPort
decl (Decl
n "board_id"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 10
suid 24,0
)
)
)
*184 (CptPort
uid 3093,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3094,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "139250,30625,140000,31375"
)
tg (CPTG
uid 3095,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3096,0
va (VaSet
)
xt "141000,30500,146700,31500"
st "crate_id : (1:0)"
blo "141000,31300"
)
)
thePort (LogicalPort
decl (Decl
n "crate_id"
t "std_logic_vector"
b "(1 DOWNTO 0)"
o 11
suid 25,0
)
)
)
*185 (CptPort
uid 3097,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3098,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "168000,16625,168750,17375"
)
tg (CPTG
uid 3099,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3100,0
va (VaSet
)
xt "161000,16500,167000,17500"
st "wiz_addr : (9:0)"
ju 2
blo "167000,17300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "wiz_addr"
t "std_logic_vector"
b "(9 DOWNTO 0)"
o 47
suid 26,0
)
)
)
*186 (CptPort
uid 3101,0
ps "OnEdgeStrategy"
shape (Diamond
uid 3102,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "168000,17625,168750,18375"
)
tg (CPTG
uid 3103,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3104,0
va (VaSet
)
xt "160700,17500,167000,18500"
st "wiz_data : (15:0)"
ju 2
blo "167000,18300"
)
)
thePort (LogicalPort
m 2
decl (Decl
n "wiz_data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 53
suid 27,0
)
)
)
*187 (CptPort
uid 3105,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3106,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "168000,23625,168750,24375"
)
tg (CPTG
uid 3107,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3108,0
va (VaSet
)
xt "164300,23500,167000,24500"
st "wiz_cs"
ju 2
blo "167000,24300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "wiz_cs"
t "std_logic"
o 48
suid 28,0
i "'1'"
)
)
)
*188 (CptPort
uid 3109,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3110,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "168000,21625,168750,22375"
)
tg (CPTG
uid 3111,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3112,0
va (VaSet
)
xt "164300,21500,167000,22500"
st "wiz_wr"
ju 2
blo "167000,22300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "wiz_wr"
t "std_logic"
o 51
suid 29,0
i "'1'"
)
)
)
*189 (CptPort
uid 3113,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3114,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "168000,20625,168750,21375"
)
tg (CPTG
uid 3115,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3116,0
va (VaSet
)
xt "164400,20500,167000,21500"
st "wiz_rd"
ju 2
blo "167000,21300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "wiz_rd"
t "std_logic"
o 49
suid 30,0
i "'1'"
)
)
)
*190 (CptPort
uid 3117,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3118,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "168000,22625,168750,23375"
)
tg (CPTG
uid 3119,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3120,0
va (VaSet
)
xt "164300,22500,167000,23500"
st "wiz_int"
ju 2
blo "167000,23300"
)
)
thePort (LogicalPort
decl (Decl
n "wiz_int"
t "std_logic"
o 15
suid 31,0
)
)
)
*191 (CptPort
uid 3121,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3122,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "139250,18625,140000,19375"
)
tg (CPTG
uid 3123,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3124,0
va (VaSet
)
xt "141000,18500,145500,19500"
st "CLK_25_PS"
blo "141000,19300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "CLK_25_PS"
t "std_logic"
o 17
suid 35,0
)
)
)
*192 (CptPort
uid 3125,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3126,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "139250,17625,140000,18375"
)
tg (CPTG
uid 3127,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3128,0
va (VaSet
)
xt "141000,17500,144100,18500"
st "CLK_50"
blo "141000,18300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "CLK_50"
t "std_logic"
preAdd 0
posAdd 0
o 18
suid 37,0
)
)
)
*193 (CptPort
uid 3129,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3130,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "139250,16625,140000,17375"
)
tg (CPTG
uid 3131,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3132,0
va (VaSet
)
xt "141000,16500,142900,17500"
st "CLK"
blo "141000,17300"
)
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_logic"
o 1
suid 38,0
)
)
)
*194 (CptPort
uid 3133,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3134,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "139250,37625,140000,38375"
)
tg (CPTG
uid 3135,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3136,0
va (VaSet
)
xt "141000,37500,149000,38500"
st "adc_otr_array : (3:0)"
blo "141000,38300"
)
)
thePort (LogicalPort
decl (Decl
n "adc_otr_array"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 9
suid 40,0
)
)
)
*195 (CptPort
uid 3137,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3138,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "139250,43625,140000,44375"
)
tg (CPTG
uid 3139,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3140,0
va (VaSet
)
xt "141000,43500,146900,44500"
st "adc_data_array"
blo "141000,44300"
)
)
thePort (LogicalPort
decl (Decl
n "adc_data_array"
t "adc_data_array_type"
o 8
suid 41,0
)
)
)
*196 (CptPort
uid 3141,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3142,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "139250,57625,140000,58375"
)
tg (CPTG
uid 3143,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3144,0
va (VaSet
)
xt "141000,57500,149500,58500"
st "drs_channel_id : (3:0)"
blo "141000,58300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_channel_id"
t "std_logic_vector"
b "(3 downto 0)"
o 35
suid 48,0
i "(others => '0')"
)
)
)
*197 (CptPort
uid 3145,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3146,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "139250,62625,140000,63375"
)
tg (CPTG
uid 3147,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3148,0
va (VaSet
)
xt "141000,62500,145300,63500"
st "drs_dwrite"
blo "141000,63300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_dwrite"
t "std_logic"
o 36
suid 49,0
i "'1'"
)
)
)
*198 (CptPort
uid 3149,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3150,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "139250,53625,140000,54375"
)
tg (CPTG
uid 3151,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3152,0
va (VaSet
)
xt "141000,53500,146400,54500"
st "SROUT_in_0"
blo "141000,54300"
)
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_0"
t "std_logic"
o 4
suid 52,0
)
)
)
*199 (CptPort
uid 3153,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3154,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "139250,54625,140000,55375"
)
tg (CPTG
uid 3155,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3156,0
va (VaSet
)
xt "141000,54500,146400,55500"
st "SROUT_in_1"
blo "141000,55300"
)
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_1"
t "std_logic"
o 5
suid 53,0
)
)
)
*200 (CptPort
uid 3157,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3158,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "139250,55625,140000,56375"
)
tg (CPTG
uid 3159,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3160,0
va (VaSet
)
xt "141000,55500,146400,56500"
st "SROUT_in_2"
blo "141000,56300"
)
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_2"
t "std_logic"
o 6
suid 54,0
)
)
)
*201 (CptPort
uid 3161,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3162,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "139250,56625,140000,57375"
)
tg (CPTG
uid 3163,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3164,0
va (VaSet
)
xt "141000,56500,146400,57500"
st "SROUT_in_3"
blo "141000,57300"
)
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_3"
t "std_logic"
o 7
suid 55,0
)
)
)
*202 (CptPort
uid 3165,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3166,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "139250,59625,140000,60375"
)
tg (CPTG
uid 3167,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3168,0
va (VaSet
)
xt "141000,59500,145200,60500"
st "RSRLOAD"
blo "141000,60300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "RSRLOAD"
t "std_logic"
o 23
suid 56,0
i "'0'"
)
)
)
*203 (CptPort
uid 3169,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3170,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "139250,60625,140000,61375"
)
tg (CPTG
uid 3171,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3172,0
va (VaSet
)
xt "141000,60500,144000,61500"
st "SRCLK"
blo "141000,61300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "SRCLK"
t "std_logic"
o 24
suid 57,0
i "'0'"
)
)
)
*204 (CptPort
uid 3173,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3174,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "168000,46625,168750,47375"
)
tg (CPTG
uid 3175,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3176,0
va (VaSet
)
xt "165300,46500,167000,47500"
st "sclk"
ju 2
blo "167000,47300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sclk"
t "std_logic"
o 42
suid 62,0
)
)
)
*205 (CptPort
uid 3177,0
ps "OnEdgeStrategy"
shape (Diamond
uid 3178,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "168000,47625,168750,48375"
)
tg (CPTG
uid 3179,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3180,0
va (VaSet
)
xt "165600,47500,167000,48500"
st "sio"
ju 2
blo "167000,48300"
)
)
thePort (LogicalPort
m 2
decl (Decl
n "sio"
t "std_logic"
preAdd 0
posAdd 0
o 52
suid 63,0
)
)
)
*206 (CptPort
uid 3181,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3182,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "168000,35625,168750,36375"
)
tg (CPTG
uid 3183,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3184,0
va (VaSet
)
xt "164200,35500,167000,36500"
st "dac_cs"
ju 2
blo "167000,36300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dac_cs"
t "std_logic"
o 31
suid 64,0
)
)
)
*207 (CptPort
uid 3185,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3186,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "168000,37625,168750,38375"
)
tg (CPTG
uid 3187,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3188,0
va (VaSet
)
xt "160500,37500,167000,38500"
st "sensor_cs : (3:0)"
ju 2
blo "167000,38300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sensor_cs"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 43
suid 65,0
)
)
)
*208 (CptPort
uid 3189,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3190,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "168000,48625,168750,49375"
)
tg (CPTG
uid 3191,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3192,0
va (VaSet
)
xt "165000,48500,167000,49500"
st "mosi"
ju 2
blo "167000,49300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "mosi"
t "std_logic"
o 40
suid 66,0
i "'0'"
)
)
)
*209 (CptPort
uid 3193,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3194,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "139250,61625,140000,62375"
)
tg (CPTG
uid 3195,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3196,0
va (VaSet
)
xt "141000,61500,144000,62500"
st "denable"
blo "141000,62300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "denable"
t "std_logic"
eolc "-- default domino wave off"
posAdd 0
o 34
suid 67,0
i "'0'"
)
)
)
*210 (CptPort
uid 3197,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3198,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "139250,67625,140000,68375"
)
tg (CPTG
uid 3199,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3200,0
va (VaSet
)
xt "141000,67500,144700,68500"
st "SRIN_out"
blo "141000,68300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "SRIN_out"
t "std_logic"
o 25
suid 85,0
i "'0'"
)
)
)
*211 (CptPort
uid 3201,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3202,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "168000,73625,168750,74375"
)
tg (CPTG
uid 3203,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3204,0
va (VaSet
)
xt "164600,73500,167000,74500"
st "green"
ju 2
blo "167000,74300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "green"
t "std_logic"
o 37
suid 86,0
)
)
)
*212 (CptPort
uid 3205,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3206,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "168000,75625,168750,76375"
)
tg (CPTG
uid 3207,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3208,0
va (VaSet
)
xt "164500,75500,167000,76500"
st "amber"
ju 2
blo "167000,76300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "amber"
t "std_logic"
o 29
suid 87,0
)
)
)
*213 (CptPort
uid 3209,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3210,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "168000,74625,168750,75375"
)
tg (CPTG
uid 3211,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3212,0
va (VaSet
)
xt "165500,74500,167000,75500"
st "red"
ju 2
blo "167000,75300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "red"
t "std_logic"
o 41
suid 88,0
)
)
)
*214 (CptPort
uid 3213,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3214,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "139250,70625,140000,71375"
)
tg (CPTG
uid 3215,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3216,0
va (VaSet
)
xt "141000,70500,146500,71500"
st "D_T_in : (1:0)"
blo "141000,71300"
)
)
thePort (LogicalPort
decl (Decl
n "D_T_in"
t "std_logic_vector"
b "(1 DOWNTO 0)"
o 2
suid 91,0
)
)
)
*215 (CptPort
uid 3217,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3218,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "139250,71625,140000,72375"
)
tg (CPTG
uid 3219,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3220,0
va (VaSet
)
xt "141000,71500,146100,72500"
st "drs_refclk_in"
blo "141000,72300"
)
)
thePort (LogicalPort
decl (Decl
n "drs_refclk_in"
t "std_logic"
eolc "-- used to check if DRS REFCLK exsists, if not DENABLE inhibit"
o 12
suid 92,0
)
)
)
*216 (CptPort
uid 3221,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3222,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "139250,72625,140000,73375"
)
tg (CPTG
uid 3223,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3224,0
va (VaSet
)
xt "141000,72500,147100,73500"
st "plllock_in : (3:0)"
blo "141000,73300"
)
)
thePort (LogicalPort
decl (Decl
n "plllock_in"
t "std_logic_vector"
b "(3 DOWNTO 0)"
eolc "-- high level, if dominowave is running and DRS PLL locked"
o 13
suid 93,0
)
)
)
*217 (CptPort
uid 3225,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3226,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "168000,72625,168750,73375"
)
tg (CPTG
uid 3227,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3228,0
va (VaSet
)
xt "158400,72500,167000,73500"
st "counter_result : (11:0)"
ju 2
blo "167000,73300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "counter_result"
t "std_logic_vector"
b "(11 DOWNTO 0)"
o 30
suid 94,0
)
)
)
*218 (CptPort
uid 3229,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3230,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "168000,69625,168750,70375"
)
tg (CPTG
uid 3231,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3232,0
va (VaSet
)
xt "158400,69500,167000,70500"
st "alarm_refclk_too_high"
ju 2
blo "167000,70300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "alarm_refclk_too_high"
t "std_logic"
o 27
suid 95,0
)
)
)
*219 (CptPort
uid 3233,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3234,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "168000,70625,168750,71375"
)
tg (CPTG
uid 3235,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3236,0
va (VaSet
)
xt "158800,70500,167000,71500"
st "alarm_refclk_too_low"
ju 2
blo "167000,71300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "alarm_refclk_too_low"
t "std_logic"
posAdd 0
o 28
suid 96,0
)
)
)
*220 (CptPort
uid 3237,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3238,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "139250,19625,140000,20375"
)
tg (CPTG
uid 3239,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3240,0
va (VaSet
)
xt "141000,19500,145000,20500"
st "ADC_CLK"
blo "141000,20300"
)
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "ADC_CLK"
t "std_logic"
o 16
suid 97,0
)
)
)
*221 (CptPort
uid 3241,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3242,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "168000,83625,168750,84375"
)
tg (CPTG
uid 3243,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3244,0
va (VaSet
)
xt "162100,83500,167000,84500"
st "trigger_veto"
ju 2
blo "167000,84300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "trigger_veto"
t "std_logic"
o 45
suid 98,0
i "'1'"
)
)
)
*222 (CptPort
uid 3245,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3246,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "139250,73625,140000,74375"
)
tg (CPTG
uid 3247,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3248,0
va (VaSet
)
xt "141000,73500,148000,74500"
st "FTM_RS485_rx_d"
blo "141000,74300"
)
)
thePort (LogicalPort
decl (Decl
n "FTM_RS485_rx_d"
t "std_logic"
o 3
suid 99,0
)
)
)
*223 (CptPort
uid 3249,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3250,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "168000,80625,168750,81375"
)
tg (CPTG
uid 3251,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3252,0
va (VaSet
)
xt "160100,80500,167000,81500"
st "FTM_RS485_tx_d"
ju 2
blo "167000,81300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "FTM_RS485_tx_d"
t "std_logic"
o 21
suid 100,0
)
)
)
*224 (CptPort
uid 3253,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3254,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "168000,79625,168750,80375"
)
tg (CPTG
uid 3255,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3256,0
va (VaSet
)
xt "159600,79500,167000,80500"
st "FTM_RS485_rx_en"
ju 2
blo "167000,80300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "FTM_RS485_rx_en"
t "std_logic"
o 20
suid 101,0
)
)
)
*225 (CptPort
uid 3257,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3258,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "168000,81625,168750,82375"
)
tg (CPTG
uid 3259,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3260,0
va (VaSet
)
xt "159700,81500,167000,82500"
st "FTM_RS485_tx_en"
ju 2
blo "167000,82300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "FTM_RS485_tx_en"
t "std_logic"
o 22
suid 102,0
)
)
)
*226 (CptPort
uid 3261,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3262,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "168000,84625,168750,85375"
)
tg (CPTG
uid 3263,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3264,0
va (VaSet
)
xt "159900,84500,167000,85500"
st "w5300_state : (7:0)"
ju 2
blo "167000,85300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "w5300_state"
t "std_logic_vector"
b "(7 DOWNTO 0)"
eolc "-- state is encoded here ... useful for debugging."
posAdd 0
o 46
suid 103,0
)
)
)
*227 (CptPort
uid 3265,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3266,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "168000,76625,168750,77375"
)
tg (CPTG
uid 3267,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3268,0
va (VaSet
)
xt "157900,76500,167000,77500"
st "debug_data_ram_empty"
ju 2
blo "167000,77300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "debug_data_ram_empty"
t "std_logic"
o 32
suid 104,0
)
)
)
*228 (CptPort
uid 3269,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3270,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "168000,77625,168750,78375"
)
tg (CPTG
uid 3271,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3272,0
va (VaSet
)
xt "160400,77500,167000,78500"
st "debug_data_valid"
ju 2
blo "167000,78300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "debug_data_valid"
t "std_logic"
o 33
suid 105,0
)
)
)
*229 (CptPort
uid 3273,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3274,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "168000,82625,168750,83375"
)
tg (CPTG
uid 3275,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3276,0
va (VaSet
)
xt "156600,82500,167000,83500"
st "mem_manager_state : (3:0)"
ju 2
blo "167000,83300"
)
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "mem_manager_state"
t "std_logic_vector"
b "(3 DOWNTO 0)"
eolc "-- state is encoded here ... useful for debugging."
posAdd 0
o 39
suid 106,0
)
)
)
*230 (CptPort
uid 3277,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3278,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "168000,78625,168750,79375"
)
tg (CPTG
uid 3279,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3280,0
va (VaSet
)
xt "160800,78500,167000,79500"
st "DG_state : (7:0)"
ju 2
blo "167000,79300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "DG_state"
t "std_logic_vector"
b "(7 downto 0)"
prec "-- for debugging"
preAdd 0
o 19
suid 108,0
)
)
)
*231 (CptPort
uid 3281,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3282,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "168000,85625,168750,86375"
)
tg (CPTG
uid 3283,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3284,0
va (VaSet
)
xt "157100,85500,167000,86500"
st "socket_tx_free_out : (16:0)"
ju 2
blo "167000,86300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "socket_tx_free_out"
t "std_logic_vector"
b "(16 DOWNTO 0)"
eolc "-- 17bit value .. that's true"
posAdd 0
o 44
suid 109,0
)
)
)
]
shape (Rectangle
uid 3286,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "140000,15000,168000,87000"
)
oxt "15000,-8000,43000,80000"
ttg (MlTextGroup
uid 3287,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*232 (Text
uid 3288,0
va (VaSet
font "Arial,8,1"
)
xt "144200,80000,150400,81000"
st "FACT_FAD_lib"
blo "144200,80800"
tm "BdLibraryNameMgr"
)
*233 (Text
uid 3289,0
va (VaSet
font "Arial,8,1"
)
xt "144200,81000,154000,82000"
st "FAD_main_with_w53002"
blo "144200,81800"
tm "CptNameMgr"
)
*234 (Text
uid 3290,0
va (VaSet
font "Arial,8,1"
)
xt "144200,82000,145200,83000"
st "I0"
blo "144200,82800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 3291,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 3292,0
text (MLText
uid 3293,0
va (VaSet
font "Courier New,8,0"
)
xt "142000,14200,162000,15000"
st "RAMADDRWIDTH64b = 15    ( integer )  
"
)
header ""
)
elements [
(GiElement
name "RAMADDRWIDTH64b"
type "integer"
value "15"
)
]
)
viewicon (ZoomableIcon
uid 3294,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "140250,85250,141750,86750"
iconName "BlockDiagram.png"
iconMaskName "BlockDiagram.msk"
ftype 1
)
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*235 (Wire
uid 286,0
shape (OrthoPolyLine
uid 287,0
va (VaSet
vasetType 3
)
xt "58750,21000,80250,21000"
pts [
"58750,21000"
"80250,21000"
]
)
start &70
end &27
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 288,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 289,0
va (VaSet
)
xt "71000,20000,72300,21000"
st "clk"
blo "71000,20800"
tm "WireNameMgr"
)
)
on &75
)
*236 (Wire
uid 318,0
shape (OrthoPolyLine
uid 319,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "109750,21000,122250,21000"
pts [
"109750,21000"
"122250,21000"
]
)
start &19
end &158
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 320,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 321,0
va (VaSet
)
xt "111000,20000,117000,21000"
st "wiz_addr : (9:0)"
blo "111000,20800"
tm "WireNameMgr"
)
)
on &76
)
*237 (Wire
uid 324,0
shape (OrthoPolyLine
uid 325,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "109750,22000,122250,22000"
pts [
"109750,22000"
"122250,22000"
]
)
start &20
end &159
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 326,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 327,0
va (VaSet
)
xt "111000,21000,117300,22000"
st "wiz_data : (15:0)"
blo "111000,21800"
tm "WireNameMgr"
)
)
on &77
)
*238 (Wire
uid 330,0
shape (OrthoPolyLine
uid 331,0
va (VaSet
vasetType 3
)
xt "109750,25000,122250,25000"
pts [
"109750,25000"
"122250,25000"
]
)
start &23
end &160
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 332,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 333,0
va (VaSet
)
xt "111000,24000,113600,25000"
st "wiz_rd"
blo "111000,24800"
tm "WireNameMgr"
)
)
on &78
)
*239 (Wire
uid 336,0
shape (OrthoPolyLine
uid 337,0
va (VaSet
vasetType 3
)
xt "109750,26000,122250,26000"
pts [
"109750,26000"
"122250,26000"
]
)
start &22
end &161
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 338,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 339,0
va (VaSet
)
xt "111000,25000,113700,26000"
st "wiz_wr"
blo "111000,25800"
tm "WireNameMgr"
)
)
on &79
)
*240 (Wire
uid 374,0
shape (OrthoPolyLine
uid 375,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "109750,42000,122250,48000"
pts [
"109750,42000"
"120000,42000"
"120000,48000"
"122250,48000"
]
)
start &41
end &83
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 376,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 377,0
va (VaSet
)
xt "111000,41000,117500,42000"
st "sensor_cs : (3:0)"
blo "111000,41800"
tm "WireNameMgr"
)
)
on &87
)
*241 (Wire
uid 380,0
shape (OrthoPolyLine
uid 381,0
va (VaSet
vasetType 3
)
xt "109750,51000,122250,51000"
pts [
"109750,51000"
"122250,51000"
]
)
start &38
end &81
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 382,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 383,0
va (VaSet
)
xt "111000,50000,112700,51000"
st "sclk"
blo "111000,50800"
tm "WireNameMgr"
)
)
on &88
)
*242 (Wire
uid 386,0
shape (OrthoPolyLine
uid 387,0
va (VaSet
vasetType 3
)
xt "109750,52000,122250,52000"
pts [
"109750,52000"
"122250,52000"
]
)
start &39
end &82
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 388,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 389,0
va (VaSet
)
xt "111000,51000,112400,52000"
st "sio"
blo "111000,51800"
tm "WireNameMgr"
)
)
on &89
)
*243 (Wire
uid 426,0
shape (OrthoPolyLine
uid 427,0
va (VaSet
vasetType 3
)
xt "58750,32000,80250,32000"
pts [
"58750,32000"
"80250,32000"
]
)
start &91
end &15
sat 32
eat 32
st 0
sf 1
tg (WTG
uid 428,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 429,0
va (VaSet
)
xt "71000,31000,73800,32000"
st "trigger"
blo "71000,31800"
tm "WireNameMgr"
)
)
on &95
)
*244 (Wire
uid 442,0
shape (OrthoPolyLine
uid 443,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "58000,34000,80250,42000"
pts [
"80250,34000"
"64000,34000"
"64000,42000"
"58000,42000"
]
)
start &17
end &96
sat 32
eat 2
sty 1
st 0
sf 1
si 0
tg (WTG
uid 446,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 447,0
va (VaSet
)
xt "71000,33000,76900,34000"
st "board_id : (3:0)"
blo "71000,33800"
tm "WireNameMgr"
)
)
on &100
)
*245 (Wire
uid 450,0
shape (OrthoPolyLine
uid 451,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "58000,35000,80250,43000"
pts [
"80250,35000"
"65000,35000"
"65000,43000"
"58000,43000"
]
)
start &18
end &96
sat 32
eat 2
sty 1
st 0
sf 1
si 0
tg (WTG
uid 454,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 455,0
va (VaSet
)
xt "71000,34000,76700,35000"
st "crate_id : (1:0)"
blo "71000,34800"
tm "WireNameMgr"
)
)
on &101
)
*246 (Wire
uid 530,0
shape (OrthoPolyLine
uid 531,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "58000,42000,80250,53000"
pts [
"80250,42000"
"68000,42000"
"68000,53000"
"58000,53000"
]
)
start &28
end &110
sat 32
eat 2
sty 1
st 0
sf 1
si 0
tg (WTG
uid 534,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 535,0
va (VaSet
)
xt "71000,41000,79000,42000"
st "adc_otr_array : (3:0)"
blo "71000,41800"
tm "WireNameMgr"
)
)
on &114
)
*247 (Wire
uid 538,0
shape (OrthoPolyLine
uid 539,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "58000,48000,80250,55000"
pts [
"80250,48000"
"70000,48000"
"70000,55000"
"58000,55000"
]
)
start &29
end &110
sat 32
eat 2
sty 1
st 0
sf 1
si 0
tg (WTG
uid 542,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 543,0
va (VaSet
)
xt "71000,47000,76900,48000"
st "adc_data_array"
blo "71000,47800"
tm "WireNameMgr"
)
)
on &115
)
*248 (Wire
uid 546,0
shape (OrthoPolyLine
uid 547,0
va (VaSet
vasetType 3
)
xt "58000,43000,80250,54000"
pts [
"80250,43000"
"69000,43000"
"69000,54000"
"58000,54000"
]
)
start &16
end &110
sat 32
eat 1
st 0
sf 1
si 0
tg (WTG
uid 550,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 551,0
va (VaSet
)
xt "71000,42000,74200,43000"
st "adc_oeb"
blo "71000,42800"
tm "WireNameMgr"
)
)
on &116
)
*249 (Wire
uid 554,0
shape (OrthoPolyLine
uid 555,0
va (VaSet
vasetType 3
)
xt "40750,54000,50000,54000"
pts [
"50000,54000"
"40750,54000"
]
)
start &110
end &106
sat 2
eat 32
st 0
sf 1
tg (WTG
uid 558,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 559,0
va (VaSet
)
xt "42000,53000,45200,54000"
st "adc_oeb"
blo "42000,53800"
tm "WireNameMgr"
)
)
on &116
)
*250 (Wire
uid 562,0
shape (OrthoPolyLine
uid 563,0
va (VaSet
vasetType 3
)
xt "40750,53000,50000,53000"
pts [
"40750,53000"
"50000,53000"
]
)
start &105
end &110
sat 32
eat 1
st 0
sf 1
tg (WTG
uid 566,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 567,0
va (VaSet
)
xt "42000,52000,44900,53000"
st "adc_otr"
blo "42000,52800"
tm "WireNameMgr"
)
)
on &117
)
*251 (Wire
uid 570,0
shape (OrthoPolyLine
uid 571,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "40750,55000,50000,55000"
pts [
"40750,55000"
"50000,55000"
]
)
start &104
end &110
sat 32
eat 1
sty 1
st 0
sf 1
tg (WTG
uid 574,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 575,0
va (VaSet
)
xt "42000,54000,48400,55000"
st "adc_data : (11:0)"
blo "42000,54800"
tm "WireNameMgr"
)
)
on &118
)
*252 (Wire
uid 578,0
shape (OrthoPolyLine
uid 579,0
va (VaSet
vasetType 3
)
xt "24000,53000,29250,53000"
pts [
"29250,53000"
"24000,53000"
]
)
start &103
sat 32
eat 16
st 0
sf 1
tg (WTG
uid 582,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 583,0
va (VaSet
)
xt "25000,52000,29000,53000"
st "ADC_CLK"
blo "25000,52800"
tm "WireNameMgr"
)
)
on &155
)
*253 (Wire
uid 769,0
shape (OrthoPolyLine
uid 770,0
va (VaSet
vasetType 3
)
xt "109750,24000,116000,24000"
pts [
"109750,24000"
"116000,24000"
]
)
start &13
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 773,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 774,0
va (VaSet
)
xt "111000,23000,114600,24000"
st "wiz_reset"
blo "111000,23800"
tm "WireNameMgr"
)
)
on &119
)
*254 (Wire
uid 777,0
shape (OrthoPolyLine
uid 778,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "109750,70000,116000,70000"
pts [
"109750,70000"
"116000,70000"
]
)
start &14
sat 32
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 781,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 782,0
va (VaSet
)
xt "111000,69000,115000,70000"
st "led : (7:0)"
blo "111000,69800"
tm "WireNameMgr"
)
)
on &120
)
*255 (Wire
uid 785,0
shape (OrthoPolyLine
uid 786,0
va (VaSet
vasetType 3
)
xt "109750,28000,122250,28000"
pts [
"109750,28000"
"122250,28000"
]
)
start &21
end &163
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 789,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 790,0
va (VaSet
)
xt "111000,27000,113700,28000"
st "wiz_cs"
blo "111000,27800"
tm "WireNameMgr"
)
)
on &121
)
*256 (Wire
uid 793,0
shape (OrthoPolyLine
uid 794,0
va (VaSet
vasetType 3
)
xt "109750,27000,122250,27000"
pts [
"122250,27000"
"109750,27000"
]
)
start &162
end &24
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 797,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 798,0
va (VaSet
)
xt "111000,26000,113700,27000"
st "wiz_int"
blo "111000,26800"
tm "WireNameMgr"
)
)
on &122
)
*257 (Wire
uid 801,0
shape (OrthoPolyLine
uid 802,0
va (VaSet
vasetType 3
)
xt "109750,40000,116000,40000"
pts [
"109750,40000"
"116000,40000"
]
)
start &40
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 805,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 806,0
va (VaSet
)
xt "111000,39000,113800,40000"
st "dac_cs"
blo "111000,39800"
tm "WireNameMgr"
)
)
on &123
)
*258 (Wire
uid 809,0
shape (OrthoPolyLine
uid 810,0
va (VaSet
vasetType 3
)
xt "109750,53000,116000,53000"
pts [
"109750,53000"
"116000,53000"
]
)
start &42
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 813,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 814,0
va (VaSet
)
xt "111000,52000,113000,53000"
st "mosi"
blo "111000,52800"
tm "WireNameMgr"
)
)
on &124
)
*259 (Wire
uid 817,0
shape (OrthoPolyLine
uid 818,0
va (VaSet
vasetType 3
)
xt "70000,66000,80250,66000"
pts [
"80250,66000"
"70000,66000"
]
)
start &43
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 821,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 822,0
va (VaSet
)
xt "71000,65000,74000,66000"
st "denable"
blo "71000,65800"
tm "WireNameMgr"
)
)
on &125
)
*260 (Wire
uid 825,0
shape (OrthoPolyLine
uid 826,0
va (VaSet
vasetType 3
)
xt "70000,23000,80250,23000"
pts [
"80250,23000"
"70000,23000"
]
)
start &25
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 829,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 830,0
va (VaSet
)
xt "71000,22000,75500,23000"
st "CLK_25_PS"
blo "71000,22800"
tm "WireNameMgr"
)
)
on &126
)
*261 (Wire
uid 833,0
shape (OrthoPolyLine
uid 834,0
va (VaSet
vasetType 3
)
xt "70000,22000,80250,22000"
pts [
"80250,22000"
"70000,22000"
]
)
start &26
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 837,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 838,0
va (VaSet
)
xt "71000,21000,74100,22000"
st "CLK_50"
blo "71000,21800"
tm "WireNameMgr"
)
)
on &127
)
*262 (Wire
uid 841,0
shape (OrthoPolyLine
uid 842,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "70000,62000,80250,62000"
pts [
"80250,62000"
"70000,62000"
]
)
start &30
sat 32
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 845,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 846,0
va (VaSet
)
xt "71000,61000,79500,62000"
st "drs_channel_id : (3:0)"
blo "71000,61800"
tm "WireNameMgr"
)
)
on &128
)
*263 (Wire
uid 849,0
shape (OrthoPolyLine
uid 850,0
va (VaSet
vasetType 3
)
xt "70000,67000,80250,67000"
pts [
"80250,67000"
"70000,67000"
]
)
start &31
ss 0
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 853,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 854,0
va (VaSet
)
xt "71000,66000,75300,67000"
st "drs_dwrite"
blo "71000,66800"
tm "WireNameMgr"
)
)
on &129
)
*264 (Wire
uid 857,0
shape (OrthoPolyLine
uid 858,0
va (VaSet
vasetType 3
)
xt "70000,64000,80250,64000"
pts [
"80250,64000"
"70000,64000"
]
)
start &36
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 861,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 862,0
va (VaSet
)
xt "71000,63000,75200,64000"
st "RSRLOAD"
blo "71000,63800"
tm "WireNameMgr"
)
)
on &130
)
*265 (Wire
uid 865,0
shape (OrthoPolyLine
uid 866,0
va (VaSet
vasetType 3
)
xt "70000,65000,80250,65000"
pts [
"80250,65000"
"70000,65000"
]
)
start &37
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 869,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 870,0
va (VaSet
)
xt "71000,64000,74000,65000"
st "SRCLK"
blo "71000,64800"
tm "WireNameMgr"
)
)
on &131
)
*266 (Wire
uid 873,0
shape (OrthoPolyLine
uid 874,0
va (VaSet
vasetType 3
)
xt "70000,58000,80250,58000"
pts [
"70000,58000"
"80250,58000"
]
)
end &32
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 877,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 878,0
va (VaSet
)
xt "71000,57000,76400,58000"
st "SROUT_in_0"
blo "71000,57800"
tm "WireNameMgr"
)
)
on &132
)
*267 (Wire
uid 881,0
shape (OrthoPolyLine
uid 882,0
va (VaSet
vasetType 3
)
xt "70000,59000,80250,59000"
pts [
"70000,59000"
"80250,59000"
]
)
end &33
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 885,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 886,0
va (VaSet
)
xt "71000,58000,76400,59000"
st "SROUT_in_1"
blo "71000,58800"
tm "WireNameMgr"
)
)
on &133
)
*268 (Wire
uid 889,0
shape (OrthoPolyLine
uid 890,0
va (VaSet
vasetType 3
)
xt "70000,60000,80250,60000"
pts [
"70000,60000"
"80250,60000"
]
)
end &34
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 893,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 894,0
va (VaSet
)
xt "71000,59000,76400,60000"
st "SROUT_in_2"
blo "71000,59800"
tm "WireNameMgr"
)
)
on &134
)
*269 (Wire
uid 897,0
shape (OrthoPolyLine
uid 898,0
va (VaSet
vasetType 3
)
xt "70000,61000,80250,61000"
pts [
"70000,61000"
"80250,61000"
]
)
end &35
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 901,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 902,0
va (VaSet
)
xt "71000,60000,76400,61000"
st "SROUT_in_3"
blo "71000,60800"
tm "WireNameMgr"
)
)
on &135
)
*270 (Wire
uid 1437,0
shape (OrthoPolyLine
uid 1438,0
va (VaSet
vasetType 3
)
xt "73000,72000,80250,72000"
pts [
"80250,72000"
"73000,72000"
]
)
start &53
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 1441,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1442,0
va (VaSet
)
xt "76000,72000,79700,73000"
st "SRIN_out"
blo "76000,72800"
tm "WireNameMgr"
)
)
on &136
)
*271 (Wire
uid 1445,0
shape (OrthoPolyLine
uid 1446,0
va (VaSet
vasetType 3
)
xt "109750,80000,115000,80000"
pts [
"109750,80000"
"115000,80000"
]
)
start &46
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 1449,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1450,0
va (VaSet
)
xt "111000,79000,113500,80000"
st "amber"
blo "111000,79800"
tm "WireNameMgr"
)
)
on &137
)
*272 (Wire
uid 1453,0
shape (OrthoPolyLine
uid 1454,0
va (VaSet
vasetType 3
)
xt "109750,79000,114000,79000"
pts [
"109750,79000"
"114000,79000"
]
)
start &52
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 1457,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1458,0
va (VaSet
)
xt "111000,78000,112500,79000"
st "red"
blo "111000,78800"
tm "WireNameMgr"
)
)
on &138
)
*273 (Wire
uid 1461,0
shape (OrthoPolyLine
uid 1462,0
va (VaSet
vasetType 3
)
xt "109750,78000,114000,78000"
pts [
"109750,78000"
"114000,78000"
]
)
start &50
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 1465,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1466,0
va (VaSet
)
xt "111000,77000,113400,78000"
st "green"
blo "111000,77800"
tm "WireNameMgr"
)
)
on &139
)
*274 (Wire
uid 1469,0
shape (OrthoPolyLine
uid 1470,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "109750,77000,121000,77000"
pts [
"109750,77000"
"121000,77000"
]
)
start &47
sat 32
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 1473,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1474,0
va (VaSet
)
xt "111000,76000,119600,77000"
st "counter_result : (11:0)"
blo "111000,76800"
tm "WireNameMgr"
)
)
on &140
)
*275 (Wire
uid 1477,0
shape (OrthoPolyLine
uid 1478,0
va (VaSet
vasetType 3
)
xt "109750,75000,120000,75000"
pts [
"109750,75000"
"120000,75000"
]
)
start &45
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 1481,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1482,0
va (VaSet
)
xt "111000,74000,119200,75000"
st "alarm_refclk_too_low"
blo "111000,74800"
tm "WireNameMgr"
)
)
on &141
)
*276 (Wire
uid 1485,0
shape (OrthoPolyLine
uid 1486,0
va (VaSet
vasetType 3
)
xt "109750,74000,121000,74000"
pts [
"109750,74000"
"121000,74000"
]
)
start &44
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 1489,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1490,0
va (VaSet
)
xt "111000,73000,119600,74000"
st "alarm_refclk_too_high"
blo "111000,73800"
tm "WireNameMgr"
)
)
on &142
)
*277 (Wire
uid 1503,0
shape (OrthoPolyLine
uid 1504,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "73000,75000,80250,75000"
pts [
"73000,75000"
"80250,75000"
]
)
end &48
sat 16
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 1507,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1508,0
va (VaSet
)
xt "74000,74000,79500,75000"
st "D_T_in : (1:0)"
blo "74000,74800"
tm "WireNameMgr"
)
)
on &147
)
*278 (Wire
uid 1529,0
shape (OrthoPolyLine
uid 1530,0
va (VaSet
vasetType 3
)
xt "66750,76000,80250,79000"
pts [
"66750,79000"
"70000,79000"
"70000,76000"
"80250,76000"
]
)
start &149
end &49
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 1531,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1532,0
va (VaSet
)
xt "68750,78000,72650,79000"
st "REF_CLK"
blo "68750,78800"
tm "WireNameMgr"
)
)
on &156
)
*279 (Wire
uid 1533,0
shape (OrthoPolyLine
uid 1534,0
va (VaSet
vasetType 3
)
xt "35000,70000,45000,70000"
pts [
"35000,70000"
"45000,70000"
]
)
start &143
sat 2
eat 16
st 0
sf 1
si 0
tg (WTG
uid 1539,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1540,0
va (VaSet
)
xt "37000,69000,42500,70000"
st "D_T_in : (1:0)"
blo "37000,69800"
tm "WireNameMgr"
)
)
on &147
)
*280 (Wire
uid 1561,0
shape (OrthoPolyLine
uid 1562,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "72000,77000,80250,77000"
pts [
"72000,77000"
"80250,77000"
]
)
end &51
sat 16
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 1565,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1566,0
va (VaSet
)
xt "73000,76000,79100,77000"
st "plllock_in : (3:0)"
blo "73000,76800"
tm "WireNameMgr"
)
)
on &154
)
*281 (Wire
uid 1567,0
shape (OrthoPolyLine
uid 1568,0
va (VaSet
vasetType 3
)
xt "35000,71000,45000,71000"
pts [
"35000,71000"
"45000,71000"
]
)
start &143
sat 2
eat 16
st 0
sf 1
si 0
tg (WTG
uid 1573,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1574,0
va (VaSet
)
xt "37000,70000,43100,71000"
st "plllock_in : (3:0)"
blo "37000,70800"
tm "WireNameMgr"
)
)
on &154
)
*282 (Wire
uid 1684,0
shape (OrthoPolyLine
uid 1685,0
va (VaSet
vasetType 3
)
xt "70000,24000,80250,24000"
pts [
"80250,24000"
"70000,24000"
]
)
start &54
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 1688,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1689,0
va (VaSet
)
xt "71000,23000,75000,24000"
st "ADC_CLK"
blo "71000,23800"
tm "WireNameMgr"
)
)
on &155
)
*283 (Wire
uid 2707,0
shape (OrthoPolyLine
uid 2708,0
va (VaSet
vasetType 3
)
xt "109750,81000,122000,81000"
pts [
"109750,81000"
"122000,81000"
]
)
start &55
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 2711,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2712,0
va (VaSet
)
xt "111000,80000,121400,81000"
st "debug_data_ram_empty"
blo "111000,80800"
tm "WireNameMgr"
)
)
on &167
)
*284 (Wire
uid 2715,0
shape (OrthoPolyLine
uid 2716,0
va (VaSet
vasetType 3
)
xt "109750,82000,120000,82000"
pts [
"109750,82000"
"120000,82000"
]
)
start &56
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 2719,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2720,0
va (VaSet
)
xt "111000,81000,118500,82000"
st "debug_data_valid"
blo "111000,81800"
tm "WireNameMgr"
)
)
on &168
)
*285 (Wire
uid 2723,0
shape (OrthoPolyLine
uid 2724,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "109750,83000,119000,83000"
pts [
"109750,83000"
"119000,83000"
]
)
start &57
sat 32
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 2727,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2728,0
va (VaSet
)
xt "111000,82000,117900,83000"
st "DG_state : (7:0)"
blo "111000,82800"
tm "WireNameMgr"
)
)
on &169
)
*286 (Wire
uid 2731,0
shape (OrthoPolyLine
uid 2732,0
va (VaSet
vasetType 3
)
xt "109750,84000,120000,84000"
pts [
"109750,84000"
"120000,84000"
]
)
start &59
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 2735,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2736,0
va (VaSet
)
xt "111000,83000,119400,84000"
st "FTM_RS485_rx_en"
blo "111000,83800"
tm "WireNameMgr"
)
)
on &170
)
*287 (Wire
uid 2739,0
shape (OrthoPolyLine
uid 2740,0
va (VaSet
vasetType 3
)
xt "109750,85000,120000,85000"
pts [
"109750,85000"
"120000,85000"
]
)
start &60
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 2743,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2744,0
va (VaSet
)
xt "111000,84000,119100,85000"
st "FTM_RS485_tx_d"
blo "111000,84800"
tm "WireNameMgr"
)
)
on &171
)
*288 (Wire
uid 2747,0
shape (OrthoPolyLine
uid 2748,0
va (VaSet
vasetType 3
)
xt "109750,86000,120000,86000"
pts [
"109750,86000"
"120000,86000"
]
)
start &61
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 2751,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2752,0
va (VaSet
)
xt "111000,85000,119400,86000"
st "FTM_RS485_tx_en"
blo "111000,85800"
tm "WireNameMgr"
)
)
on &172
)
*289 (Wire
uid 2755,0
shape (OrthoPolyLine
uid 2756,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "109750,87000,123000,87000"
pts [
"109750,87000"
"123000,87000"
]
)
start &62
sat 32
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 2759,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2760,0
va (VaSet
)
xt "111000,86000,122400,87000"
st "mem_manager_state : (3:0)"
blo "111000,86800"
tm "WireNameMgr"
)
)
on &173
)
*290 (Wire
uid 2763,0
shape (OrthoPolyLine
uid 2764,0
va (VaSet
vasetType 3
)
xt "109750,88000,118000,88000"
pts [
"109750,88000"
"118000,88000"
]
)
start &63
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 2767,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2768,0
va (VaSet
)
xt "111000,87000,116600,88000"
st "trigger_veto"
blo "111000,87800"
tm "WireNameMgr"
)
)
on &174
)
*291 (Wire
uid 2771,0
shape (OrthoPolyLine
uid 2772,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "109750,89000,120000,89000"
pts [
"109750,89000"
"120000,89000"
]
)
start &64
sat 32
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 2775,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2776,0
va (VaSet
)
xt "111000,88000,119400,89000"
st "w5300_state : (7:0)"
blo "111000,88800"
tm "WireNameMgr"
)
)
on &175
)
*292 (Wire
uid 2779,0
shape (OrthoPolyLine
uid 2780,0
va (VaSet
vasetType 3
)
xt "74000,78000,80250,82000"
pts [
"74000,82000"
"80250,78000"
]
)
end &58
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 2783,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2784,0
va (VaSet
)
xt "73000,80000,81100,81000"
st "FTM_RS485_rx_d"
blo "73000,80800"
tm "WireNameMgr"
)
)
on &176
)
*293 (Wire
uid 2944,0
shape (OrthoPolyLine
uid 2945,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "109750,90000,124000,90000"
pts [
"109750,90000"
"124000,90000"
]
)
start &65
sat 32
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 2948,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2949,0
va (VaSet
)
xt "111000,89000,122900,90000"
st "socket_tx_free_out : (16:0)"
blo "111000,89800"
tm "WireNameMgr"
)
)
on &177
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 1
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *294 (PackageList
uid 41,0
stg "VerticalLayoutStrategy"
textVec [
*295 (Text
uid 42,0
va (VaSet
font "arial,8,1"
)
xt "-87000,0,-81600,1000"
st "Package List"
blo "-87000,800"
)
*296 (MLText
uid 43,0
va (VaSet
)
xt "-87000,1000,-72500,11000"
st "LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

LIBRARY FACT_FAD_lib;
USE FACT_FAD_lib.fad_definitions.all;
USE ieee.std_logic_textio.all;
LIBRARY std;
USE std.textio.all;"
tm "PackageList"
)
]
)
compDirBlock (MlTextGroup
uid 44,0
stg "VerticalLayoutStrategy"
textVec [
*297 (Text
uid 45,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,0,28100,1000"
st "Compiler Directives"
blo "20000,800"
)
*298 (Text
uid 46,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,1000,29600,2000"
st "Pre-module directives:"
blo "20000,1800"
)
*299 (MLText
uid 47,0
va (VaSet
isHidden 1
)
xt "20000,2000,27500,4000"
st "`resetall
`timescale 1ns/10ps"
tm "BdCompilerDirectivesTextMgr"
)
*300 (Text
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n "board_id"
t "std_logic_vector"
b "(3 downto 0)"
preAdd 0
posAdd 0
o 10
suid 10,0
)
)
uid 458,0
)
*348 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "crate_id"
t "std_logic_vector"
b "(1 downto 0)"
o 11
suid 11,0
)
)
uid 460,0
)
*349 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "adc_otr_array"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 12
suid 12,0
)
)
uid 584,0
)
*350 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "adc_data_array"
t "adc_data_array_type"
o 13
suid 13,0
)
)
uid 586,0
)
*351 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "adc_oeb"
t "std_logic"
preAdd 0
posAdd 0
o 14
suid 14,0
)
)
uid 588,0
)
*352 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "adc_otr"
t "STD_LOGIC"
preAdd 0
posAdd 0
o 16
suid 16,0
)
)
uid 590,0
)
*353 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "adc_data"
t "std_logic_vector"
b "(11 DOWNTO 0)"
preAdd 0
posAdd 0
o 17
suid 17,0
)
)
uid 592,0
)
*354 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "wiz_reset"
t "std_logic"
o 21
suid 23,0
i "'1'"
)
)
uid 903,0
)
*355 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "led"
t "std_logic_vector"
b "(7 DOWNTO 0)"
posAdd 0
o 22
suid 24,0
i "(OTHERS => '0')"
)
)
uid 905,0
)
*356 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "wiz_cs"
t "std_logic"
o 23
suid 25,0
i "'1'"
)
)
uid 907,0
)
*357 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "wiz_int"
t "std_logic"
o 24
suid 26,0
)
)
uid 909,0
)
*358 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "dac_cs"
t "std_logic"
o 25
suid 27,0
)
)
uid 911,0
)
*359 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "mosi"
t "std_logic"
o 26
suid 28,0
i "'0'"
)
)
uid 913,0
)
*360 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "denable"
t "std_logic"
eolc "-- default domino wave off"
posAdd 0
o 27
suid 29,0
i "'0'"
)
)
uid 915,0
)
*361 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "CLK_25_PS"
t "std_logic"
o 28
suid 30,0
)
)
uid 917,0
)
*362 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "CLK_50"
t "std_logic"
o 29
suid 31,0
)
)
uid 919,0
)
*363 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "drs_channel_id"
t "std_logic_vector"
b "(3 downto 0)"
o 30
suid 32,0
i "(others => '0')"
)
)
uid 921,0
)
*364 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "drs_dwrite"
t "std_logic"
o 31
suid 33,0
i "'1'"
)
)
uid 923,0
)
*365 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "RSRLOAD"
t "std_logic"
o 32
suid 34,0
i "'0'"
)
)
uid 925,0
)
*366 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "SRCLK"
t "std_logic"
o 33
suid 35,0
i "'0'"
)
)
uid 927,0
)
*367 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "SROUT_in_0"
t "std_logic"
o 30
suid 36,0
)
)
uid 929,0
)
*368 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "SROUT_in_1"
t "std_logic"
o 31
suid 37,0
)
)
uid 931,0
)
*369 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "SROUT_in_2"
t "std_logic"
o 32
suid 38,0
)
)
uid 933,0
)
*370 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "SROUT_in_3"
t "std_logic"
o 33
suid 39,0
)
)
uid 935,0
)
*371 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "SRIN_out"
t "std_logic"
o 34
suid 40,0
i "'0'"
)
)
uid 1541,0
)
*372 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "amber"
t "std_logic"
o 35
suid 41,0
)
)
uid 1543,0
)
*373 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "red"
t "std_logic"
o 36
suid 42,0
)
)
uid 1545,0
)
*374 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "green"
t "std_logic"
o 37
suid 43,0
)
)
uid 1547,0
)
*375 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "counter_result"
t "std_logic_vector"
b "(11 DOWNTO 0)"
o 38
suid 44,0
)
)
uid 1549,0
)
*376 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "alarm_refclk_too_low"
t "std_logic"
posAdd 0
o 39
suid 45,0
)
)
uid 1551,0
)
*377 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "alarm_refclk_too_high"
t "std_logic"
o 40
suid 46,0
)
)
uid 1553,0
)
*378 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "D_T_in"
t "std_logic_vector"
b "(1 DOWNTO 0)"
o 41
suid 47,0
)
)
uid 1555,0
)
*379 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "plllock_in"
t "std_logic_vector"
b "(3 DOWNTO 0)"
eolc "-- high level, if dominowave is running and DRS PLL locked"
o 43
suid 49,0
)
)
uid 1575,0
)
*380 (LeafLogPort
port (LogicalPort
lang 2
m 4
decl (Decl
n "ADC_CLK"
t "std_logic"
o 44
suid 50,0
)
)
uid 1690,0
)
*381 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "REF_CLK"
t "STD_LOGIC"
o 42
suid 51,0
i "'0'"
)
)
uid 2003,0
)
*382 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "debug_data_ram_empty"
t "std_logic"
o 45
suid 53,0
)
)
uid 2785,0
)
*383 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "debug_data_valid"
t "std_logic"
o 46
suid 54,0
)
)
uid 2787,0
)
*384 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "DG_state"
t "std_logic_vector"
b "(7 downto 0)"
prec "-- for debugging"
preAdd 0
o 47
suid 55,0
)
)
uid 2789,0
)
*385 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "FTM_RS485_rx_en"
t "std_logic"
o 48
suid 56,0
)
)
uid 2791,0
)
*386 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "FTM_RS485_tx_d"
t "std_logic"
o 49
suid 57,0
)
)
uid 2793,0
)
*387 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "FTM_RS485_tx_en"
t "std_logic"
o 50
suid 58,0
)
)
uid 2795,0
)
*388 (LeafLogPort
port (LogicalPort
lang 2
m 4
decl (Decl
n "mem_manager_state"
t "std_logic_vector"
b "(3 DOWNTO 0)"
eolc "-- state is encoded here ... useful for debugging."
posAdd 0
o 51
suid 59,0
)
)
uid 2797,0
)
*389 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "trigger_veto"
t "std_logic"
o 52
suid 60,0
i "'1'"
)
)
uid 2799,0
)
*390 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "w5300_state"
t "std_logic_vector"
b "(7 DOWNTO 0)"
eolc "-- state is encoded here ... useful for debugging."
posAdd 0
o 53
suid 61,0
)
)
uid 2801,0
)
*391 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "FTM_RS485_rx_d"
t "std_logic"
o 54
suid 62,0
)
)
uid 2803,0
)
*392 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "socket_tx_free_out"
t "std_logic_vector"
b "(16 DOWNTO 0)"
eolc "-- 17bit value .. that's true"
posAdd 0
o 55
suid 64,0
)
)
uid 2950,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 67,0
optionalChildren [
*393 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *394 (MRCItem
litem &325
pos 55
dimension 20
)
uid 69,0
optionalChildren [
*395 (MRCItem
litem &326
pos 0
dimension 20
uid 70,0
)
*396 (MRCItem
litem &327
pos 1
dimension 23
uid 71,0
)
*397 (MRCItem
litem &328
pos 2
hidden 1
dimension 20
uid 72,0
)
*398 (MRCItem
litem &338
pos 0
dimension 20
uid 341,0
)
*399 (MRCItem
litem &339
pos 1
dimension 20
uid 343,0
)
*400 (MRCItem
litem &340
pos 2
dimension 20
uid 345,0
)
*401 (MRCItem
litem &341
pos 3
dimension 20
uid 347,0
)
*402 (MRCItem
litem &342
pos 4
dimension 20
uid 349,0
)
*403 (MRCItem
litem &343
pos 5
dimension 20
uid 405,0
)
*404 (MRCItem
litem &344
pos 6
dimension 20
uid 407,0
)
*405 (MRCItem
litem &345
pos 7
dimension 20
uid 409,0
)
*406 (MRCItem
litem &346
pos 8
dimension 20
uid 457,0
)
*407 (MRCItem
litem &347
pos 9
dimension 20
uid 459,0
)
*408 (MRCItem
litem &348
pos 10
dimension 20
uid 461,0
)
*409 (MRCItem
litem &349
pos 11
dimension 20
uid 585,0
)
*410 (MRCItem
litem &350
pos 12
dimension 20
uid 587,0
)
*411 (MRCItem
litem &351
pos 13
dimension 20
uid 589,0
)
*412 (MRCItem
litem &352
pos 14
dimension 20
uid 591,0
)
*413 (MRCItem
litem &353
pos 15
dimension 20
uid 593,0
)
*414 (MRCItem
litem &354
pos 16
dimension 20
uid 904,0
)
*415 (MRCItem
litem &355
pos 17
dimension 20
uid 906,0
)
*416 (MRCItem
litem &356
pos 18
dimension 20
uid 908,0
)
*417 (MRCItem
litem &357
pos 19
dimension 20
uid 910,0
)
*418 (MRCItem
litem &358
pos 20
dimension 20
uid 912,0
)
*419 (MRCItem
litem &359
pos 21
dimension 20
uid 914,0
)
*420 (MRCItem
litem &360
pos 22
dimension 20
uid 916,0
)
*421 (MRCItem
litem &361
pos 23
dimension 20
uid 918,0
)
*422 (MRCItem
litem &362
pos 24
dimension 20
uid 920,0
)
*423 (MRCItem
litem &363
pos 25
dimension 20
uid 922,0
)
*424 (MRCItem
litem &364
pos 26
dimension 20
uid 924,0
)
*425 (MRCItem
litem &365
pos 27
dimension 20
uid 926,0
)
*426 (MRCItem
litem &366
pos 28
dimension 20
uid 928,0
)
*427 (MRCItem
litem &367
pos 29
dimension 20
uid 930,0
)
*428 (MRCItem
litem &368
pos 30
dimension 20
uid 932,0
)
*429 (MRCItem
litem &369
pos 31
dimension 20
uid 934,0
)
*430 (MRCItem
litem &370
pos 32
dimension 20
uid 936,0
)
*431 (MRCItem
litem &371
pos 33
dimension 20
uid 1542,0
)
*432 (MRCItem
litem &372
pos 34
dimension 20
uid 1544,0
)
*433 (MRCItem
litem &373
pos 35
dimension 20
uid 1546,0
)
*434 (MRCItem
litem &374
pos 36
dimension 20
uid 1548,0
)
*435 (MRCItem
litem &375
pos 37
dimension 20
uid 1550,0
)
*436 (MRCItem
litem &376
pos 38
dimension 20
uid 1552,0
)
*437 (MRCItem
litem &377
pos 39
dimension 20
uid 1554,0
)
*438 (MRCItem
litem &378
pos 40
dimension 20
uid 1556,0
)
*439 (MRCItem
litem &379
pos 41
dimension 20
uid 1576,0
)
*440 (MRCItem
litem &380
pos 42
dimension 20
uid 1691,0
)
*441 (MRCItem
litem &381
pos 43
dimension 20
uid 2004,0
)
*442 (MRCItem
litem &382
pos 44
dimension 20
uid 2786,0
)
*443 (MRCItem
litem &383
pos 45
dimension 20
uid 2788,0
)
*444 (MRCItem
litem &384
pos 46
dimension 20
uid 2790,0
)
*445 (MRCItem
litem &385
pos 47
dimension 20
uid 2792,0
)
*446 (MRCItem
litem &386
pos 48
dimension 20
uid 2794,0
)
*447 (MRCItem
litem &387
pos 49
dimension 20
uid 2796,0
)
*448 (MRCItem
litem &388
pos 50
dimension 20
uid 2798,0
)
*449 (MRCItem
litem &389
pos 51
dimension 20
uid 2800,0
)
*450 (MRCItem
litem &390
pos 52
dimension 20
uid 2802,0
)
*451 (MRCItem
litem &391
pos 53
dimension 20
uid 2804,0
)
*452 (MRCItem
litem &392
pos 54
dimension 20
uid 2951,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 73,0
optionalChildren [
*453 (MRCItem
litem &329
pos 0
dimension 20
uid 74,0
)
*454 (MRCItem
litem &331
pos 1
dimension 50
uid 75,0
)
*455 (MRCItem
litem &332
pos 2
dimension 100
uid 76,0
)
*456 (MRCItem
litem &333
pos 3
dimension 50
uid 77,0
)
*457 (MRCItem
litem &334
pos 4
dimension 100
uid 78,0
)
*458 (MRCItem
litem &335
pos 5
dimension 100
uid 79,0
)
*459 (MRCItem
litem &336
pos 6
dimension 50
uid 80,0
)
*460 (MRCItem
litem &337
pos 7
dimension 80
uid 81,0
)
]
)
fixedCol 4
fixedRow 2
name "Ports"
uid 68,0
vaOverrides [
]
)
]
)
uid 53,0
)
genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *461 (LEmptyRow
)
uid 83,0
optionalChildren [
*462 (RefLabelRowHdr
)
*463 (TitleRowHdr
)
*464 (FilterRowHdr
)
*465 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*466 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*467 (GroupColHdr
tm "GroupColHdrMgr"
)
*468 (NameColHdr
tm "GenericNameColHdrMgr"
)
*469 (TypeColHdr
tm "GenericTypeColHdrMgr"
)
*470 (InitColHdr
tm "GenericValueColHdrMgr"
)
*471 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
)
*472 (EolColHdr
tm "GenericEolColHdrMgr"
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 95,0
optionalChildren [
*473 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *474 (MRCItem
litem &461
pos 0
dimension 20
)
uid 97,0
optionalChildren [
*475 (MRCItem
litem &462
pos 0
dimension 20
uid 98,0
)
*476 (MRCItem
litem &463
pos 1
dimension 23
uid 99,0
)
*477 (MRCItem
litem &464
pos 2
hidden 1
dimension 20
uid 100,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 101,0
optionalChildren [
*478 (MRCItem
litem &465
pos 0
dimension 20
uid 102,0
)
*479 (MRCItem
litem &467
pos 1
dimension 50
uid 103,0
)
*480 (MRCItem
litem &468
pos 2
dimension 100
uid 104,0
)
*481 (MRCItem
litem &469
pos 3
dimension 100
uid 105,0
)
*482 (MRCItem
litem &470
pos 4
dimension 50
uid 106,0
)
*483 (MRCItem
litem &471
pos 5
dimension 50
uid 107,0
)
*484 (MRCItem
litem &472
pos 6
dimension 80
uid 108,0
)
]
)
fixedCol 3
fixedRow 2
name "Ports"
uid 96,0
vaOverrides [
]
)
]
)
uid 82,0
type 1
)
activeModelName "BlockDiag"
)