source: firmware/FAD/FACT_FAD_TB_lib/hds/fad_main_tb_w5300_2/struct.bd

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tm "CptNameMgr"
)
*29 (Text
uid 367,0
va (VaSet
font "Arial,8,1"
)
xt "123200,58000,131000,59000"
st "I_mainTB_max6662"
blo "123200,58800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 368,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 369,0
text (MLText
uid 370,0
va (VaSet
font "Courier New,8,0"
)
xt "123000,45200,143000,46000"
st "DRS_TEMPERATURE = 51    ( integer )  "
)
header ""
)
elements [
(GiElement
name "DRS_TEMPERATURE"
type "integer"
value "51"
)
]
)
viewicon (ZoomableIcon
uid 371,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "123250,54250,124750,55750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
sIVOD 1
)
archFileType "UNKNOWN"
)
*30 (Net
uid 372,0
decl (Decl
n "sensor_cs"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 6
suid 6,0
)
declText (MLText
uid 373,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,59000,-58500,59800"
st "SIGNAL sensor_cs             : std_logic_vector(3 DOWNTO 0)
"
)
)
*31 (Net
uid 378,0
decl (Decl
n "sclk"
t "std_logic"
o 7
suid 7,0
)
declText (MLText
uid 379,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,58200,-68000,59000"
st "SIGNAL sclk                  : std_logic
"
)
)
*32 (Net
uid 384,0
decl (Decl
n "sio"
t "std_logic"
preAdd 0
posAdd 0
o 8
suid 8,0
)
declText (MLText
uid 385,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,59800,-68000,60600"
st "SIGNAL sio                   : std_logic
"
)
)
*33 (SaComponent
uid 414,0
optionalChildren [
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uid 410,0
ps "OnEdgeStrategy"
shape (Triangle
uid 411,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "58000,31625,58750,32375"
)
tg (CPTG
uid 412,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 413,0
va (VaSet
)
xt "54200,31500,57000,32500"
st "trigger"
ju 2
blo "57000,32300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "trigger"
t "std_logic"
preAdd 0
posAdd 0
o 1
suid 1,0
)
)
)
]
shape (Rectangle
uid 415,0
va (VaSet
vasetType 1
fg "0,49152,49152"
lineColor "0,0,50000"
lineWidth 2
)
xt "50000,30000,58000,36000"
)
oxt "19000,4000,29000,14000"
ttg (MlTextGroup
uid 416,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*35 (Text
uid 417,0
va (VaSet
font "Arial,8,1"
)
xt "50200,36000,57900,37000"
st "FACT_FAD_TB_lib"
blo "50200,36800"
tm "BdLibraryNameMgr"
)
*36 (Text
uid 418,0
va (VaSet
font "Arial,8,1"
)
xt "50200,37000,57500,38000"
st "trigger_generator"
blo "50200,37800"
tm "CptNameMgr"
)
*37 (Text
uid 419,0
va (VaSet
font "Arial,8,1"
)
xt "50200,38000,57400,39000"
st "I_mainTB_trigger"
blo "50200,38800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 420,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 421,0
text (MLText
uid 422,0
va (VaSet
font "Courier New,8,0"
)
xt "50000,28400,68500,30000"
st "TRIGGER_RATE = 1 ms     ( time )  
PULSE_WIDTH  = 20 ns    ( time )  "
)
header ""
)
elements [
(GiElement
name "TRIGGER_RATE"
type "time"
value "1 ms"
)
(GiElement
name "PULSE_WIDTH"
type "time"
value "20 ns"
)
]
)
viewicon (ZoomableIcon
uid 423,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "50250,34250,51750,35750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
sIVOD 1
)
archFileType "UNKNOWN"
)
*38 (Net
uid 424,0
decl (Decl
n "trigger"
t "std_logic"
preAdd 0
posAdd 0
o 9
suid 9,0
)
declText (MLText
uid 425,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,61400,-68000,62200"
st "SIGNAL trigger               : std_logic
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)
)
*39 (HdlText
uid 430,0
optionalChildren [
*40 (EmbeddedText
uid 436,0
commentText (CommentText
uid 437,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 438,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "50000,45000,60000,49000"
)
oxt "0,0,18000,5000"
text (MLText
uid 439,0
va (VaSet
)
xt "50200,45200,60200,48200"
st "
-- eb_ID 1: hard-wired IDs
board_id <= \"0101\";
crate_id <= \"01\";

"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 4000
visibleWidth 10000
)
)
)
]
shape (Rectangle
uid 431,0
va (VaSet
vasetType 1
fg "65535,65535,37120"
lineColor "0,0,32768"
lineWidth 2
)
xt "50000,40000,58000,45000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 432,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*41 (Text
uid 433,0
va (VaSet
font "Arial,8,1"
)
xt "51150,41000,57350,42000"
st "eb_mainTB_ID"
blo "51150,41800"
tm "HdlTextNameMgr"
)
*42 (Text
uid 434,0
va (VaSet
font "Arial,8,1"
)
xt "51150,42000,51950,43000"
st "1"
blo "51150,42800"
tm "HdlTextNumberMgr"
)
]
)
viewicon (ZoomableIcon
uid 435,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "50250,43250,51750,44750"
iconName "TextFile.png"
iconMaskName "TextFile.msk"
ftype 21
)
viewiconposition 0
)
*43 (Net
uid 440,0
decl (Decl
n "board_id"
t "std_logic_vector"
b "(3 downto 0)"
preAdd 0
posAdd 0
o 10
suid 10,0
)
declText (MLText
uid 441,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,45400,-58500,46200"
st "SIGNAL board_id              : std_logic_vector(3 downto 0)
"
)
)
*44 (Net
uid 448,0
decl (Decl
n "crate_id"
t "std_logic_vector"
b "(1 downto 0)"
o 11
suid 11,0
)
declText (MLText
uid 449,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,47800,-58500,48600"
st "SIGNAL crate_id              : std_logic_vector(1 downto 0)
"
)
)
*45 (SaComponent
uid 508,0
optionalChildren [
*46 (CptPort
uid 489,0
ps "OnEdgeStrategy"
shape (Triangle
uid 490,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "29250,52625,30000,53375"
)
tg (CPTG
uid 491,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 492,0
va (VaSet
)
xt "31000,52500,32300,53500"
st "clk"
blo "31000,53300"
)
)
thePort (LogicalPort
decl (Decl
n "clk"
t "STD_LOGIC"
preAdd 0
posAdd 0
o 1
suid 1,0
)
)
)
*47 (CptPort
uid 493,0
ps "OnEdgeStrategy"
shape (Triangle
uid 494,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,54625,40750,55375"
)
tg (CPTG
uid 495,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 496,0
va (VaSet
)
xt "34200,54500,39000,55500"
st "data : (11:0)"
ju 2
blo "39000,55300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "data"
t "STD_LOGIC_VECTOR"
b "(11 DOWNTO 0)"
preAdd 0
posAdd 0
o 2
suid 2,0
)
)
)
*48 (CptPort
uid 497,0
ps "OnEdgeStrategy"
shape (Triangle
uid 498,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,52625,40750,53375"
)
tg (CPTG
uid 499,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 500,0
va (VaSet
)
xt "37700,52500,39000,53500"
st "otr"
ju 2
blo "39000,53300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "otr"
t "STD_LOGIC"
preAdd 0
posAdd 0
o 3
suid 3,0
)
)
)
*49 (CptPort
uid 501,0
ps "OnEdgeStrategy"
shape (Triangle
uid 502,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,53625,40750,54375"
)
tg (CPTG
uid 503,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 504,0
va (VaSet
)
xt "37400,53500,39000,54500"
st "oeb"
ju 2
blo "39000,54300"
)
)
thePort (LogicalPort
decl (Decl
n "oeb"
t "STD_LOGIC"
preAdd 0
posAdd 0
o 4
suid 4,0
)
)
)
]
shape (Rectangle
uid 509,0
va (VaSet
vasetType 1
fg "0,49152,49152"
lineColor "0,0,50000"
lineWidth 2
)
xt "30000,51000,40000,58000"
)
oxt "29000,7000,39000,17000"
ttg (MlTextGroup
uid 510,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*50 (Text
uid 511,0
va (VaSet
font "Arial,8,1"
)
xt "30200,58000,37900,59000"
st "FACT_FAD_TB_lib"
blo "30200,58800"
tm "BdLibraryNameMgr"
)
*51 (Text
uid 512,0
va (VaSet
font "Arial,8,1"
)
xt "30200,59000,36000,60000"
st "adc_emulator"
blo "30200,59800"
tm "CptNameMgr"
)
*52 (Text
uid 513,0
va (VaSet
font "Arial,8,1"
)
xt "30200,60000,36200,61000"
st "I_mainTB_adc"
blo "30200,60800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 514,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 515,0
text (MLText
uid 516,0
va (VaSet
font "Courier New,8,0"
)
xt "30000,50200,65500,51000"
st "INPUT_FILE = \"../memory_files/analog_input_ch0.txt\"    ( string )  "
)
header ""
)
elements [
(GiElement
name "INPUT_FILE"
type "string"
value "\"../memory_files/analog_input_ch0.txt\""
)
]
)
viewicon (ZoomableIcon
uid 517,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "30250,56250,31750,57750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
sIVOD 1
)
archFileType "UNKNOWN"
)
*53 (HdlText
uid 518,0
optionalChildren [
*54 (EmbeddedText
uid 524,0
commentText (CommentText
uid 525,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 526,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "50000,57000,62000,67000"
)
oxt "0,0,18000,5000"
text (MLText
uid 527,0
va (VaSet
)
xt "50200,57200,62100,66200"
st "
-- eb_adc 2: ADC routing
adc_data_array(0) <= adc_data;
adc_data_array(1) <= adc_data;
adc_data_array(2) <= adc_data;
adc_data_array(3) <= adc_data;
adc_otr_array(0) <= adc_otr;
adc_otr_array(1) <= adc_otr;
adc_otr_array(2) <= adc_otr;
adc_otr_array(3) <= adc_otr;

"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 10000
visibleWidth 12000
)
)
)
]
shape (Rectangle
uid 519,0
va (VaSet
vasetType 1
fg "65535,65535,37120"
lineColor "0,0,32768"
lineWidth 2
)
xt "50000,51000,58000,57000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 520,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*55 (Text
uid 521,0
va (VaSet
font "Arial,8,1"
)
xt "51150,52000,57850,53000"
st "eb_mainTB_adc"
blo "51150,52800"
tm "HdlTextNameMgr"
)
*56 (Text
uid 522,0
va (VaSet
font "Arial,8,1"
)
xt "51150,53000,51950,54000"
st "2"
blo "51150,53800"
tm "HdlTextNumberMgr"
)
]
)
viewicon (ZoomableIcon
uid 523,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "50250,55250,51750,56750"
iconName "TextFile.png"
iconMaskName "TextFile.msk"
ftype 21
)
viewiconposition 0
)
*57 (Net
uid 528,0
decl (Decl
n "adc_otr_array"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 12
suid 12,0
)
declText (MLText
uid 529,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,42200,-58500,43000"
st "SIGNAL adc_otr_array         : std_logic_vector(3 DOWNTO 0)
"
)
)
*58 (Net
uid 536,0
decl (Decl
n "adc_data_array"
t "adc_data_array_type"
o 13
suid 13,0
)
declText (MLText
uid 537,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,39800,-63000,40600"
st "SIGNAL adc_data_array        : adc_data_array_type
"
)
)
*59 (Net
uid 544,0
decl (Decl
n "adc_oeb"
t "std_logic"
preAdd 0
posAdd 0
o 14
suid 14,0
)
declText (MLText
uid 545,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,40600,-68000,41400"
st "SIGNAL adc_oeb               : std_logic
"
)
)
*60 (Net
uid 560,0
decl (Decl
n "adc_otr"
t "STD_LOGIC"
preAdd 0
posAdd 0
o 16
suid 16,0
)
declText (MLText
uid 561,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,41400,-68000,42200"
st "SIGNAL adc_otr               : STD_LOGIC
"
)
)
*61 (Net
uid 568,0
decl (Decl
n "adc_data"
t "std_logic_vector"
b "(11 DOWNTO 0)"
preAdd 0
posAdd 0
o 17
suid 17,0
)
declText (MLText
uid 569,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,39000,-58000,39800"
st "SIGNAL adc_data              : std_logic_vector(11 DOWNTO 0)
"
)
)
*62 (Net
uid 767,0
decl (Decl
n "wiz_reset"
t "std_logic"
o 21
suid 23,0
i "'1'"
)
declText (MLText
uid 768,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,67800,-55000,68600"
st "SIGNAL wiz_reset             : std_logic                    := '1'
"
)
)
*63 (Net
uid 775,0
decl (Decl
n "led"
t "std_logic_vector"
b "(7 DOWNTO 0)"
posAdd 0
o 22
suid 24,0
i "(OTHERS => '0')"
)
declText (MLText
uid 776,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,54200,-49000,55000"
st "SIGNAL led                   : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')
"
)
)
*64 (Net
uid 783,0
decl (Decl
n "wiz_cs"
t "std_logic"
o 23
suid 25,0
i "'1'"
)
declText (MLText
uid 784,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,64600,-55000,65400"
st "SIGNAL wiz_cs                : std_logic                    := '1'
"
)
)
*65 (Net
uid 791,0
decl (Decl
n "wiz_int"
t "std_logic"
o 24
suid 26,0
)
declText (MLText
uid 792,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,66200,-68000,67000"
st "SIGNAL wiz_int               : std_logic
"
)
)
*66 (Net
uid 799,0
decl (Decl
n "dac_cs"
t "std_logic"
o 25
suid 27,0
)
declText (MLText
uid 800,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,48600,-68000,49400"
st "SIGNAL dac_cs                : std_logic
"
)
)
*67 (Net
uid 807,0
decl (Decl
n "mosi"
t "std_logic"
o 26
suid 28,0
i "'0'"
)
declText (MLText
uid 808,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,55800,-55000,56600"
st "SIGNAL mosi                  : std_logic                    := '0'
"
)
)
*68 (Net
uid 815,0
decl (Decl
n "denable"
t "std_logic"
eolc "-- default domino wave off"
posAdd 0
o 27
suid 29,0
i "'0'"
)
declText (MLText
uid 816,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,51000,-41500,51800"
st "SIGNAL denable               : std_logic                    := '0' -- default domino wave off
"
)
)
*69 (Net
uid 823,0
decl (Decl
n "CLK_25_PS"
t "std_logic"
o 28
suid 30,0
)
declText (MLText
uid 824,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,25400,-68000,26200"
st "SIGNAL CLK_25_PS             : std_logic
"
)
)
*70 (Net
uid 831,0
decl (Decl
n "CLK_50"
t "std_logic"
o 29
suid 31,0
)
declText (MLText
uid 832,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,26200,-68000,27000"
st "SIGNAL CLK_50                : std_logic
"
)
)
*71 (Net
uid 839,0
decl (Decl
n "drs_channel_id"
t "std_logic_vector"
b "(3 downto 0)"
o 30
suid 32,0
i "(others => '0')"
)
declText (MLText
uid 840,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,51800,-49000,52600"
st "SIGNAL drs_channel_id        : std_logic_vector(3 downto 0) := (others => '0')
"
)
)
*72 (Net
uid 847,0
decl (Decl
n "drs_dwrite"
t "std_logic"
o 31
suid 33,0
i "'1'"
)
declText (MLText
uid 848,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,52600,-55000,53400"
st "SIGNAL drs_dwrite            : std_logic                    := '1'
"
)
)
*73 (Net
uid 855,0
decl (Decl
n "RSRLOAD"
t "std_logic"
o 32
suid 34,0
i "'0'"
)
declText (MLText
uid 856,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,33400,-55000,34200"
st "SIGNAL RSRLOAD               : std_logic                    := '0'
"
)
)
*74 (Net
uid 863,0
decl (Decl
n "SRCLK"
t "std_logic"
o 33
suid 35,0
i "'0'"
)
declText (MLText
uid 864,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,34200,-55000,35000"
st "SIGNAL SRCLK                 : std_logic                    := '0'
"
)
)
*75 (Net
uid 871,0
decl (Decl
n "SROUT_in_0"
t "std_logic"
o 30
suid 36,0
)
declText (MLText
uid 872,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,35800,-68000,36600"
st "SIGNAL SROUT_in_0            : std_logic
"
)
)
*76 (Net
uid 879,0
decl (Decl
n "SROUT_in_1"
t "std_logic"
o 31
suid 37,0
)
declText (MLText
uid 880,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,36600,-68000,37400"
st "SIGNAL SROUT_in_1            : std_logic
"
)
)
*77 (Net
uid 887,0
decl (Decl
n "SROUT_in_2"
t "std_logic"
o 32
suid 38,0
)
declText (MLText
uid 888,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,37400,-68000,38200"
st "SIGNAL SROUT_in_2            : std_logic
"
)
)
*78 (Net
uid 895,0
decl (Decl
n "SROUT_in_3"
t "std_logic"
o 33
suid 39,0
)
declText (MLText
uid 896,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,38200,-68000,39000"
st "SIGNAL SROUT_in_3            : std_logic
"
)
)
*79 (Net
uid 1435,0
decl (Decl
n "SRIN_out"
t "std_logic"
o 34
suid 40,0
i "'0'"
)
declText (MLText
uid 1436,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,35000,-55000,35800"
st "SIGNAL SRIN_out              : std_logic                    := '0'
"
)
)
*80 (Net
uid 1443,0
decl (Decl
n "amber"
t "std_logic"
o 35
suid 41,0
)
declText (MLText
uid 1444,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,44600,-68000,45400"
st "SIGNAL amber                 : std_logic
"
)
)
*81 (Net
uid 1451,0
decl (Decl
n "red"
t "std_logic"
o 36
suid 42,0
)
declText (MLText
uid 1452,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,57400,-68000,58200"
st "SIGNAL red                   : std_logic
"
)
)
*82 (Net
uid 1459,0
decl (Decl
n "green"
t "std_logic"
o 37
suid 43,0
)
declText (MLText
uid 1460,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,53400,-68000,54200"
st "SIGNAL green                 : std_logic
"
)
)
*83 (Net
uid 1467,0
decl (Decl
n "counter_result"
t "std_logic_vector"
b "(11 DOWNTO 0)"
o 38
suid 44,0
)
declText (MLText
uid 1468,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,47000,-58000,47800"
st "SIGNAL counter_result        : std_logic_vector(11 DOWNTO 0)
"
)
)
*84 (Net
uid 1475,0
decl (Decl
n "alarm_refclk_too_low"
t "std_logic"
posAdd 0
o 39
suid 45,0
)
declText (MLText
uid 1476,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,43800,-68000,44600"
st "SIGNAL alarm_refclk_too_low  : std_logic
"
)
)
*85 (Net
uid 1483,0
decl (Decl
n "alarm_refclk_too_high"
t "std_logic"
o 40
suid 46,0
)
declText (MLText
uid 1484,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,43000,-68000,43800"
st "SIGNAL alarm_refclk_too_high : std_logic
"
)
)
*86 (HdlText
uid 1491,0
optionalChildren [
*87 (EmbeddedText
uid 1497,0
commentText (CommentText
uid 1498,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 1499,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "27000,72000,41000,77000"
)
oxt "0,0,18000,5000"
text (MLText
uid 1500,0
va (VaSet
)
xt "27200,72200,39400,77200"
st "

D_T_in(1 downto 0) <= \"00\";
plllock_in(3 downto 0) <= \"1111\";
SROUT_in_0 <= '1';
SROUT_in_1 <= '0';
SROUT_in_2 <= '1';
SROUT_in_3 <= '0';

"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 5000
visibleWidth 14000
)
)
)
]
shape (Rectangle
uid 1492,0
va (VaSet
vasetType 1
fg "65535,65535,37120"
lineColor "0,0,32768"
lineWidth 2
)
xt "27000,69000,35000,72000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 1493,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*88 (Text
uid 1494,0
va (VaSet
font "Arial,8,1"
)
xt "28150,69000,35250,70000"
st "eb_mainTB_adc1"
blo "28150,69800"
tm "HdlTextNameMgr"
)
*89 (Text
uid 1495,0
va (VaSet
font "Arial,8,1"
)
xt "28150,70000,28950,71000"
st "3"
blo "28150,70800"
tm "HdlTextNumberMgr"
)
]
)
viewicon (ZoomableIcon
uid 1496,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "27250,70250,28750,71750"
iconName "TextFile.png"
iconMaskName "TextFile.msk"
ftype 21
)
viewiconposition 0
)
*90 (Net
uid 1501,0
decl (Decl
n "D_T_in"
t "std_logic_vector"
b "(1 DOWNTO 0)"
o 41
suid 47,0
)
declText (MLText
uid 1502,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,28600,-58500,29400"
st "SIGNAL D_T_in                : std_logic_vector(1 DOWNTO 0)
"
)
)
*91 (SaComponent
uid 1509,0
optionalChildren [
*92 (CptPort
uid 1519,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1520,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "66000,78625,66750,79375"
)
tg (CPTG
uid 1521,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1522,0
va (VaSet
)
xt "63700,78500,65000,79500"
st "clk"
ju 2
blo "65000,79300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "clk"
t "STD_LOGIC"
o 1
i "'0'"
)
)
)
*93 (CptPort
uid 1523,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1524,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "66000,79625,66750,80375"
)
tg (CPTG
uid 1525,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1526,0
va (VaSet
)
xt "63700,79500,65000,80500"
st "rst"
ju 2
blo "65000,80300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "rst"
t "STD_LOGIC"
o 2
i "'0'"
)
)
)
]
shape (Rectangle
uid 1510,0
va (VaSet
vasetType 1
fg "0,49152,49152"
lineColor "0,0,50000"
lineWidth 2
)
xt "55000,77000,66000,82000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 1511,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*94 (Text
uid 1512,0
va (VaSet
font "Arial,8,1"
)
xt "56150,78000,63850,79000"
st "FACT_FAD_TB_lib"
blo "56150,78800"
tm "BdLibraryNameMgr"
)
*95 (Text
uid 1513,0
va (VaSet
font "Arial,8,1"
)
xt "56150,79000,62850,80000"
st "clock_generator"
blo "56150,79800"
tm "CptNameMgr"
)
*96 (Text
uid 1514,0
va (VaSet
font "Arial,8,1"
)
xt "56150,80000,63150,81000"
st "I_mainTB_clock1"
blo "56150,80800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1515,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1516,0
text (MLText
uid 1517,0
va (VaSet
font "Courier New,8,0"
)
xt "55000,82400,73000,84000"
st "clock_period = 1 us    ( time )  
reset_time   = 1 us    ( time )  "
)
header ""
)
elements [
(GiElement
name "clock_period"
type "time"
value "1 us"
)
(GiElement
name "reset_time"
type "time"
value "1 us"
)
]
)
viewicon (ZoomableIcon
uid 1518,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "55250,80250,56750,81750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*97 (Net
uid 1559,0
decl (Decl
n "plllock_in"
t "std_logic_vector"
b "(3 DOWNTO 0)"
eolc "-- high level, if dominowave is running and DRS PLL locked"
o 43
suid 49,0
)
declText (MLText
uid 1560,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,56600,-29000,57400"
st "SIGNAL plllock_in            : std_logic_vector(3 DOWNTO 0) -- high level, if dominowave is running and DRS PLL locked
"
)
)
*98 (Net
uid 1682,0
lang 2
decl (Decl
n "ADC_CLK"
t "std_logic"
o 44
suid 50,0
)
declText (MLText
uid 1683,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,24600,-68000,25400"
st "SIGNAL ADC_CLK               : std_logic
"
)
)
*99 (Net
uid 2001,0
decl (Decl
n "REF_CLK"
t "STD_LOGIC"
o 42
suid 51,0
i "'0'"
)
declText (MLText
uid 2002,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,32600,-55000,33400"
st "SIGNAL REF_CLK               : STD_LOGIC                    := '0'
"
)
)
*100 (SaComponent
uid 2336,0
optionalChildren [
*101 (CptPort
uid 2315,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2316,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "122250,20625,123000,21375"
)
tg (CPTG
uid 2317,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2318,0
va (VaSet
)
xt "124000,20500,129100,21500"
st "addr : (9:0)"
blo "124000,21300"
)
)
thePort (LogicalPort
decl (Decl
n "addr"
t "std_logic_vector"
b "(9 DOWNTO 0)"
preAdd 0
posAdd 0
o 2
suid 1,0
)
)
)
*102 (CptPort
uid 2319,0
ps "OnEdgeStrategy"
shape (Diamond
uid 2320,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "122250,21625,123000,22375"
)
tg (CPTG
uid 2321,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2322,0
va (VaSet
)
xt "124000,21500,129400,22500"
st "data : (15:0)"
blo "124000,22300"
)
)
thePort (LogicalPort
m 2
decl (Decl
n "data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
preAdd 0
posAdd 0
o 3
suid 2,0
)
)
)
*103 (CptPort
uid 2323,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2324,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "122250,24625,123000,25375"
)
tg (CPTG
uid 2325,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2326,0
va (VaSet
)
xt "124000,24500,125300,25500"
st "rd"
blo "124000,25300"
)
)
thePort (LogicalPort
decl (Decl
n "rd"
t "std_logic"
preAdd 0
posAdd 0
o 4
suid 3,0
)
)
)
*104 (CptPort
uid 2327,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2328,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "122250,25625,123000,26375"
)
tg (CPTG
uid 2329,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2330,0
va (VaSet
)
xt "124000,25500,125400,26500"
st "wr"
blo "124000,26300"
)
)
thePort (LogicalPort
decl (Decl
n "wr"
t "std_logic"
preAdd 0
posAdd 0
o 6
suid 4,0
)
)
)
*105 (CptPort
uid 2331,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2332,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "122250,26625,123000,27375"
)
tg (CPTG
uid 2333,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2334,0
va (VaSet
)
xt "124000,26500,125400,27500"
st "int"
blo "124000,27300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "int"
t "std_logic"
o 1
suid 5,0
i "'1'"
)
)
)
*106 (CptPort
uid 2548,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2549,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "122250,27625,123000,28375"
)
tg (CPTG
uid 2550,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2551,0
va (VaSet
)
xt "124000,27500,125200,28500"
st "cs"
blo "124000,28300"
)
)
thePort (LogicalPort
decl (Decl
n "cs"
t "std_logic"
o 5
suid 6,0
)
)
)
]
shape (Rectangle
uid 2337,0
va (VaSet
vasetType 1
fg "0,49152,49152"
lineColor "0,0,50000"
lineWidth 2
)
xt "123000,19000,133000,31000"
)
oxt "29000,0,39000,12000"
ttg (MlTextGroup
uid 2338,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*107 (Text
uid 2339,0
va (VaSet
font "Arial,8,1"
)
xt "123200,31000,130900,32000"
st "FACT_FAD_TB_lib"
blo "123200,31800"
tm "BdLibraryNameMgr"
)
*108 (Text
uid 2340,0
va (VaSet
font "Arial,8,1"
)
xt "123200,32000,129800,33000"
st "w5300_emulator"
blo "123200,32800"
tm "CptNameMgr"
)
*109 (Text
uid 2341,0
va (VaSet
font "Arial,8,1"
)
xt "123200,33000,130000,34000"
st "I_mainTB_w5300"
blo "123200,33800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 2342,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 2343,0
text (MLText
uid 2344,0
va (VaSet
font "Courier New,8,0"
)
xt "123000,18000,123000,18000"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 2345,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "123250,29250,124750,30750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*110 (Net
uid 2705,0
decl (Decl
n "debug_data_ram_empty"
t "std_logic"
o 45
suid 53,0
)
declText (MLText
uid 2706,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,49400,-68000,50200"
st "SIGNAL debug_data_ram_empty  : std_logic
"
)
)
*111 (Net
uid 2713,0
decl (Decl
n "debug_data_valid"
t "std_logic"
o 46
suid 54,0
)
declText (MLText
uid 2714,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,50200,-68000,51000"
st "SIGNAL debug_data_valid      : std_logic
"
)
)
*112 (Net
uid 2721,0
decl (Decl
n "DG_state"
t "std_logic_vector"
b "(7 downto 0)"
prec "-- for debugging"
preAdd 0
o 47
suid 55,0
)
declText (MLText
uid 2722,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,27000,-58500,28600"
st "-- for debugging
SIGNAL DG_state              : std_logic_vector(7 downto 0)
"
)
)
*113 (Net
uid 2729,0
decl (Decl
n "FTM_RS485_rx_en"
t "std_logic"
o 48
suid 56,0
)
declText (MLText
uid 2730,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,30200,-68000,31000"
st "SIGNAL FTM_RS485_rx_en       : std_logic
"
)
)
*114 (Net
uid 2737,0
decl (Decl
n "FTM_RS485_tx_d"
t "std_logic"
o 49
suid 57,0
)
declText (MLText
uid 2738,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,31000,-68000,31800"
st "SIGNAL FTM_RS485_tx_d        : std_logic
"
)
)
*115 (Net
uid 2745,0
decl (Decl
n "FTM_RS485_tx_en"
t "std_logic"
o 50
suid 58,0
)
declText (MLText
uid 2746,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,31800,-68000,32600"
st "SIGNAL FTM_RS485_tx_en       : std_logic
"
)
)
*116 (Net
uid 2753,0
lang 2
decl (Decl
n "mem_manager_state"
t "std_logic_vector"
b "(3 DOWNTO 0)"
eolc "-- state is encoded here ... useful for debugging."
posAdd 0
o 51
suid 59,0
)
declText (MLText
uid 2754,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,55000,-33000,55800"
st "SIGNAL mem_manager_state     : std_logic_vector(3 DOWNTO 0) -- state is encoded here ... useful for debugging.
"
)
)
*117 (Net
uid 2761,0
decl (Decl
n "trigger_veto"
t "std_logic"
o 52
suid 60,0
i "'1'"
)
declText (MLText
uid 2762,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,62200,-55000,63000"
st "SIGNAL trigger_veto          : std_logic                    := '1'
"
)
)
*118 (Net
uid 2769,0
decl (Decl
n "w5300_state"
t "std_logic_vector"
b "(7 DOWNTO 0)"
eolc "-- state is encoded here ... useful for debugging."
posAdd 0
o 53
suid 61,0
)
declText (MLText
uid 2770,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,63000,-33000,63800"
st "SIGNAL w5300_state           : std_logic_vector(7 DOWNTO 0) -- state is encoded here ... useful for debugging.
"
)
)
*119 (Net
uid 2777,0
decl (Decl
n "FTM_RS485_rx_d"
t "std_logic"
o 54
suid 62,0
)
declText (MLText
uid 2778,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,29400,-68000,30200"
st "SIGNAL FTM_RS485_rx_d        : std_logic
"
)
)
*120 (Net
uid 2942,0
decl (Decl
n "socket_tx_free_out"
t "std_logic_vector"
b "(16 DOWNTO 0)"
eolc "-- 17bit value .. that's true"
posAdd 0
o 55
suid 64,0
)
declText (MLText
uid 2943,0
va (VaSet
font "Courier New,8,0"
)
xt "-90000,60600,-43000,61400"
st "SIGNAL socket_tx_free_out    : std_logic_vector(16 DOWNTO 0) -- 17bit value .. that's true
"
)
)
*121 (SaComponent
uid 3285,0
optionalChildren [
*122 (CptPort
uid 3073,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3074,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,23625,109750,24375"
)
tg (CPTG
uid 3075,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3076,0
va (VaSet
)
xt "104400,23500,108000,24500"
st "wiz_reset"
ju 2
blo "108000,24300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "wiz_reset"
t "std_logic"
o 50
suid 2,0
i "'1'"
)
)
)
*123 (CptPort
uid 3077,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3078,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,69625,109750,70375"
)
tg (CPTG
uid 3079,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3080,0
va (VaSet
)
xt "104000,69500,108000,70500"
st "led : (7:0)"
ju 2
blo "108000,70300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "led"
t "std_logic_vector"
b "(7 DOWNTO 0)"
posAdd 0
o 38
suid 7,0
i "(OTHERS => '0')"
)
)
)
*124 (CptPort
uid 3081,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3082,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,31625,81000,32375"
)
tg (CPTG
uid 3083,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3084,0
va (VaSet
)
xt "82000,31500,84800,32500"
st "trigger"
blo "82000,32300"
)
)
thePort (LogicalPort
decl (Decl
n "trigger"
t "std_logic"
preAdd 0
posAdd 0
o 14
suid 18,0
)
)
)
*125 (CptPort
uid 3085,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3086,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,42625,81000,43375"
)
tg (CPTG
uid 3087,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3088,0
va (VaSet
)
xt "82000,42500,85200,43500"
st "adc_oeb"
blo "82000,43300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "adc_oeb"
t "std_logic"
o 26
suid 21,0
i "'1'"
)
)
)
*126 (CptPort
uid 3089,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3090,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,33625,81000,34375"
)
tg (CPTG
uid 3091,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3092,0
va (VaSet
)
xt "82000,33500,87900,34500"
st "board_id : (3:0)"
blo "82000,34300"
)
)
thePort (LogicalPort
decl (Decl
n "board_id"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 10
suid 24,0
)
)
)
*127 (CptPort
uid 3093,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3094,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,34625,81000,35375"
)
tg (CPTG
uid 3095,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3096,0
va (VaSet
)
xt "82000,34500,87700,35500"
st "crate_id : (1:0)"
blo "82000,35300"
)
)
thePort (LogicalPort
decl (Decl
n "crate_id"
t "std_logic_vector"
b "(1 DOWNTO 0)"
o 11
suid 25,0
)
)
)
*128 (CptPort
uid 3097,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3098,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,20625,109750,21375"
)
tg (CPTG
uid 3099,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3100,0
va (VaSet
)
xt "102000,20500,108000,21500"
st "wiz_addr : (9:0)"
ju 2
blo "108000,21300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "wiz_addr"
t "std_logic_vector"
b "(9 DOWNTO 0)"
o 47
suid 26,0
)
)
)
*129 (CptPort
uid 3101,0
ps "OnEdgeStrategy"
shape (Diamond
uid 3102,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,21625,109750,22375"
)
tg (CPTG
uid 3103,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3104,0
va (VaSet
)
xt "101700,21500,108000,22500"
st "wiz_data : (15:0)"
ju 2
blo "108000,22300"
)
)
thePort (LogicalPort
m 2
decl (Decl
n "wiz_data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 53
suid 27,0
)
)
)
*130 (CptPort
uid 3105,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3106,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,27625,109750,28375"
)
tg (CPTG
uid 3107,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3108,0
va (VaSet
)
xt "105300,27500,108000,28500"
st "wiz_cs"
ju 2
blo "108000,28300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "wiz_cs"
t "std_logic"
o 48
suid 28,0
i "'1'"
)
)
)
*131 (CptPort
uid 3109,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3110,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,25625,109750,26375"
)
tg (CPTG
uid 3111,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3112,0
va (VaSet
)
xt "105300,25500,108000,26500"
st "wiz_wr"
ju 2
blo "108000,26300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "wiz_wr"
t "std_logic"
o 51
suid 29,0
i "'1'"
)
)
)
*132 (CptPort
uid 3113,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3114,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,24625,109750,25375"
)
tg (CPTG
uid 3115,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3116,0
va (VaSet
)
xt "105400,24500,108000,25500"
st "wiz_rd"
ju 2
blo "108000,25300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "wiz_rd"
t "std_logic"
o 49
suid 30,0
i "'1'"
)
)
)
*133 (CptPort
uid 3117,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3118,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,26625,109750,27375"
)
tg (CPTG
uid 3119,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3120,0
va (VaSet
)
xt "105300,26500,108000,27500"
st "wiz_int"
ju 2
blo "108000,27300"
)
)
thePort (LogicalPort
decl (Decl
n "wiz_int"
t "std_logic"
o 15
suid 31,0
)
)
)
*134 (CptPort
uid 3121,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3122,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,22625,81000,23375"
)
tg (CPTG
uid 3123,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3124,0
va (VaSet
)
xt "82000,22500,86500,23500"
st "CLK_25_PS"
blo "82000,23300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "CLK_25_PS"
t "std_logic"
o 17
suid 35,0
)
)
)
*135 (CptPort
uid 3125,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3126,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,21625,81000,22375"
)
tg (CPTG
uid 3127,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3128,0
va (VaSet
)
xt "82000,21500,85100,22500"
st "CLK_50"
blo "82000,22300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "CLK_50"
t "std_logic"
preAdd 0
posAdd 0
o 18
suid 37,0
)
)
)
*136 (CptPort
uid 3129,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3130,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,20625,81000,21375"
)
tg (CPTG
uid 3131,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3132,0
va (VaSet
)
xt "82000,20500,83900,21500"
st "CLK"
blo "82000,21300"
)
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_logic"
o 1
suid 38,0
)
)
)
*137 (CptPort
uid 3133,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3134,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,41625,81000,42375"
)
tg (CPTG
uid 3135,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3136,0
va (VaSet
)
xt "82000,41500,90000,42500"
st "adc_otr_array : (3:0)"
blo "82000,42300"
)
)
thePort (LogicalPort
decl (Decl
n "adc_otr_array"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 9
suid 40,0
)
)
)
*138 (CptPort
uid 3137,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3138,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,47625,81000,48375"
)
tg (CPTG
uid 3139,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3140,0
va (VaSet
)
xt "82000,47500,87900,48500"
st "adc_data_array"
blo "82000,48300"
)
)
thePort (LogicalPort
decl (Decl
n "adc_data_array"
t "adc_data_array_type"
o 8
suid 41,0
)
)
)
*139 (CptPort
uid 3141,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3142,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,61625,81000,62375"
)
tg (CPTG
uid 3143,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3144,0
va (VaSet
)
xt "82000,61500,90500,62500"
st "drs_channel_id : (3:0)"
blo "82000,62300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_channel_id"
t "std_logic_vector"
b "(3 downto 0)"
o 35
suid 48,0
i "(others => '0')"
)
)
)
*140 (CptPort
uid 3145,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3146,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,66625,81000,67375"
)
tg (CPTG
uid 3147,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3148,0
va (VaSet
)
xt "82000,66500,86300,67500"
st "drs_dwrite"
blo "82000,67300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_dwrite"
t "std_logic"
o 36
suid 49,0
i "'1'"
)
)
)
*141 (CptPort
uid 3149,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3150,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,57625,81000,58375"
)
tg (CPTG
uid 3151,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3152,0
va (VaSet
)
xt "82000,57500,87400,58500"
st "SROUT_in_0"
blo "82000,58300"
)
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_0"
t "std_logic"
o 4
suid 52,0
)
)
)
*142 (CptPort
uid 3153,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3154,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,58625,81000,59375"
)
tg (CPTG
uid 3155,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3156,0
va (VaSet
)
xt "82000,58500,87400,59500"
st "SROUT_in_1"
blo "82000,59300"
)
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_1"
t "std_logic"
o 5
suid 53,0
)
)
)
*143 (CptPort
uid 3157,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3158,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,59625,81000,60375"
)
tg (CPTG
uid 3159,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3160,0
va (VaSet
)
xt "82000,59500,87400,60500"
st "SROUT_in_2"
blo "82000,60300"
)
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_2"
t "std_logic"
o 6
suid 54,0
)
)
)
*144 (CptPort
uid 3161,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3162,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,60625,81000,61375"
)
tg (CPTG
uid 3163,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3164,0
va (VaSet
)
xt "82000,60500,87400,61500"
st "SROUT_in_3"
blo "82000,61300"
)
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_3"
t "std_logic"
o 7
suid 55,0
)
)
)
*145 (CptPort
uid 3165,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3166,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,63625,81000,64375"
)
tg (CPTG
uid 3167,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3168,0
va (VaSet
)
xt "82000,63500,86200,64500"
st "RSRLOAD"
blo "82000,64300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "RSRLOAD"
t "std_logic"
o 23
suid 56,0
i "'0'"
)
)
)
*146 (CptPort
uid 3169,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3170,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,64625,81000,65375"
)
tg (CPTG
uid 3171,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3172,0
va (VaSet
)
xt "82000,64500,85000,65500"
st "SRCLK"
blo "82000,65300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "SRCLK"
t "std_logic"
o 24
suid 57,0
i "'0'"
)
)
)
*147 (CptPort
uid 3173,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3174,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,50625,109750,51375"
)
tg (CPTG
uid 3175,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3176,0
va (VaSet
)
xt "106300,50500,108000,51500"
st "sclk"
ju 2
blo "108000,51300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sclk"
t "std_logic"
o 42
suid 62,0
)
)
)
*148 (CptPort
uid 3177,0
ps "OnEdgeStrategy"
shape (Diamond
uid 3178,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,51625,109750,52375"
)
tg (CPTG
uid 3179,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3180,0
va (VaSet
)
xt "106600,51500,108000,52500"
st "sio"
ju 2
blo "108000,52300"
)
)
thePort (LogicalPort
m 2
decl (Decl
n "sio"
t "std_logic"
preAdd 0
posAdd 0
o 52
suid 63,0
)
)
)
*149 (CptPort
uid 3181,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3182,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,39625,109750,40375"
)
tg (CPTG
uid 3183,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3184,0
va (VaSet
)
xt "105200,39500,108000,40500"
st "dac_cs"
ju 2
blo "108000,40300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dac_cs"
t "std_logic"
o 31
suid 64,0
)
)
)
*150 (CptPort
uid 3185,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3186,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,41625,109750,42375"
)
tg (CPTG
uid 3187,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3188,0
va (VaSet
)
xt "101500,41500,108000,42500"
st "sensor_cs : (3:0)"
ju 2
blo "108000,42300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sensor_cs"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 43
suid 65,0
)
)
)
*151 (CptPort
uid 3189,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3190,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,52625,109750,53375"
)
tg (CPTG
uid 3191,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3192,0
va (VaSet
)
xt "106000,52500,108000,53500"
st "mosi"
ju 2
blo "108000,53300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "mosi"
t "std_logic"
o 40
suid 66,0
i "'0'"
)
)
)
*152 (CptPort
uid 3193,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3194,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,65625,81000,66375"
)
tg (CPTG
uid 3195,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3196,0
va (VaSet
)
xt "82000,65500,85000,66500"
st "denable"
blo "82000,66300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "denable"
t "std_logic"
eolc "-- default domino wave off"
posAdd 0
o 34
suid 67,0
i "'0'"
)
)
)
*153 (CptPort
uid 3197,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3198,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,71625,81000,72375"
)
tg (CPTG
uid 3199,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3200,0
va (VaSet
)
xt "82000,71500,85700,72500"
st "SRIN_out"
blo "82000,72300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "SRIN_out"
t "std_logic"
o 25
suid 85,0
i "'0'"
)
)
)
*154 (CptPort
uid 3201,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3202,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,77625,109750,78375"
)
tg (CPTG
uid 3203,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3204,0
va (VaSet
)
xt "105600,77500,108000,78500"
st "green"
ju 2
blo "108000,78300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "green"
t "std_logic"
o 37
suid 86,0
)
)
)
*155 (CptPort
uid 3205,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3206,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,79625,109750,80375"
)
tg (CPTG
uid 3207,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3208,0
va (VaSet
)
xt "105500,79500,108000,80500"
st "amber"
ju 2
blo "108000,80300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "amber"
t "std_logic"
o 29
suid 87,0
)
)
)
*156 (CptPort
uid 3209,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3210,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,78625,109750,79375"
)
tg (CPTG
uid 3211,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3212,0
va (VaSet
)
xt "106500,78500,108000,79500"
st "red"
ju 2
blo "108000,79300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "red"
t "std_logic"
o 41
suid 88,0
)
)
)
*157 (CptPort
uid 3213,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3214,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,74625,81000,75375"
)
tg (CPTG
uid 3215,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3216,0
va (VaSet
)
xt "82000,74500,87500,75500"
st "D_T_in : (1:0)"
blo "82000,75300"
)
)
thePort (LogicalPort
decl (Decl
n "D_T_in"
t "std_logic_vector"
b "(1 DOWNTO 0)"
o 2
suid 91,0
)
)
)
*158 (CptPort
uid 3217,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3218,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,75625,81000,76375"
)
tg (CPTG
uid 3219,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3220,0
va (VaSet
)
xt "82000,75500,87100,76500"
st "drs_refclk_in"
blo "82000,76300"
)
)
thePort (LogicalPort
decl (Decl
n "drs_refclk_in"
t "std_logic"
eolc "-- used to check if DRS REFCLK exsists, if not DENABLE inhibit"
o 12
suid 92,0
)
)
)
*159 (CptPort
uid 3221,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3222,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,76625,81000,77375"
)
tg (CPTG
uid 3223,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3224,0
va (VaSet
)
xt "82000,76500,88100,77500"
st "plllock_in : (3:0)"
blo "82000,77300"
)
)
thePort (LogicalPort
decl (Decl
n "plllock_in"
t "std_logic_vector"
b "(3 DOWNTO 0)"
eolc "-- high level, if dominowave is running and DRS PLL locked"
o 13
suid 93,0
)
)
)
*160 (CptPort
uid 3225,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3226,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,76625,109750,77375"
)
tg (CPTG
uid 3227,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3228,0
va (VaSet
)
xt "99400,76500,108000,77500"
st "counter_result : (11:0)"
ju 2
blo "108000,77300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "counter_result"
t "std_logic_vector"
b "(11 DOWNTO 0)"
o 30
suid 94,0
)
)
)
*161 (CptPort
uid 3229,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3230,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,73625,109750,74375"
)
tg (CPTG
uid 3231,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3232,0
va (VaSet
)
xt "99400,73500,108000,74500"
st "alarm_refclk_too_high"
ju 2
blo "108000,74300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "alarm_refclk_too_high"
t "std_logic"
o 27
suid 95,0
)
)
)
*162 (CptPort
uid 3233,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3234,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,74625,109750,75375"
)
tg (CPTG
uid 3235,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3236,0
va (VaSet
)
xt "99800,74500,108000,75500"
st "alarm_refclk_too_low"
ju 2
blo "108000,75300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "alarm_refclk_too_low"
t "std_logic"
posAdd 0
o 28
suid 96,0
)
)
)
*163 (CptPort
uid 3237,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3238,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,23625,81000,24375"
)
tg (CPTG
uid 3239,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3240,0
va (VaSet
)
xt "82000,23500,86000,24500"
st "ADC_CLK"
blo "82000,24300"
)
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "ADC_CLK"
t "std_logic"
o 16
suid 97,0
)
)
)
*164 (CptPort
uid 3241,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3242,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,87625,109750,88375"
)
tg (CPTG
uid 3243,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3244,0
va (VaSet
)
xt "103100,87500,108000,88500"
st "trigger_veto"
ju 2
blo "108000,88300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "trigger_veto"
t "std_logic"
o 45
suid 98,0
i "'1'"
)
)
)
*165 (CptPort
uid 3245,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3246,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,77625,81000,78375"
)
tg (CPTG
uid 3247,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3248,0
va (VaSet
)
xt "82000,77500,89000,78500"
st "FTM_RS485_rx_d"
blo "82000,78300"
)
)
thePort (LogicalPort
decl (Decl
n "FTM_RS485_rx_d"
t "std_logic"
o 3
suid 99,0
)
)
)
*166 (CptPort
uid 3249,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3250,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,84625,109750,85375"
)
tg (CPTG
uid 3251,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3252,0
va (VaSet
)
xt "101100,84500,108000,85500"
st "FTM_RS485_tx_d"
ju 2
blo "108000,85300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "FTM_RS485_tx_d"
t "std_logic"
o 21
suid 100,0
)
)
)
*167 (CptPort
uid 3253,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3254,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,83625,109750,84375"
)
tg (CPTG
uid 3255,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3256,0
va (VaSet
)
xt "100600,83500,108000,84500"
st "FTM_RS485_rx_en"
ju 2
blo "108000,84300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "FTM_RS485_rx_en"
t "std_logic"
o 20
suid 101,0
)
)
)
*168 (CptPort
uid 3257,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3258,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,85625,109750,86375"
)
tg (CPTG
uid 3259,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3260,0
va (VaSet
)
xt "100700,85500,108000,86500"
st "FTM_RS485_tx_en"
ju 2
blo "108000,86300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "FTM_RS485_tx_en"
t "std_logic"
o 22
suid 102,0
)
)
)
*169 (CptPort
uid 3261,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3262,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,88625,109750,89375"
)
tg (CPTG
uid 3263,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3264,0
va (VaSet
)
xt "100900,88500,108000,89500"
st "w5300_state : (7:0)"
ju 2
blo "108000,89300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "w5300_state"
t "std_logic_vector"
b "(7 DOWNTO 0)"
eolc "-- state is encoded here ... useful for debugging."
posAdd 0
o 46
suid 103,0
)
)
)
*170 (CptPort
uid 3265,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3266,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,80625,109750,81375"
)
tg (CPTG
uid 3267,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3268,0
va (VaSet
)
xt "98900,80500,108000,81500"
st "debug_data_ram_empty"
ju 2
blo "108000,81300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "debug_data_ram_empty"
t "std_logic"
o 32
suid 104,0
)
)
)
*171 (CptPort
uid 3269,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3270,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,81625,109750,82375"
)
tg (CPTG
uid 3271,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3272,0
va (VaSet
)
xt "101400,81500,108000,82500"
st "debug_data_valid"
ju 2
blo "108000,82300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "debug_data_valid"
t "std_logic"
o 33
suid 105,0
)
)
)
*172 (CptPort
uid 3273,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3274,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,86625,109750,87375"
)
tg (CPTG
uid 3275,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3276,0
va (VaSet
)
xt "97600,86500,108000,87500"
st "mem_manager_state : (3:0)"
ju 2
blo "108000,87300"
)
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "mem_manager_state"
t "std_logic_vector"
b "(3 DOWNTO 0)"
eolc "-- state is encoded here ... useful for debugging."
posAdd 0
o 39
suid 106,0
)
)
)
*173 (CptPort
uid 3277,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3278,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,82625,109750,83375"
)
tg (CPTG
uid 3279,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3280,0
va (VaSet
)
xt "101800,82500,108000,83500"
st "DG_state : (7:0)"
ju 2
blo "108000,83300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "DG_state"
t "std_logic_vector"
b "(7 downto 0)"
prec "-- for debugging"
preAdd 0
o 19
suid 108,0
)
)
)
*174 (CptPort
uid 3281,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3282,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,89625,109750,90375"
)
tg (CPTG
uid 3283,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3284,0
va (VaSet
)
xt "98100,89500,108000,90500"
st "socket_tx_free_out : (16:0)"
ju 2
blo "108000,90300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "socket_tx_free_out"
t "std_logic_vector"
b "(16 DOWNTO 0)"
eolc "-- 17bit value .. that's true"
posAdd 0
o 44
suid 109,0
)
)
)
]
shape (Rectangle
uid 3286,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "81000,19000,109000,91000"
)
oxt "15000,-8000,43000,80000"
ttg (MlTextGroup
uid 3287,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*175 (Text
uid 3288,0
va (VaSet
font "Arial,8,1"
)
xt "85200,84000,91400,85000"
st "FACT_FAD_lib"
blo "85200,84800"
tm "BdLibraryNameMgr"
)
*176 (Text
uid 3289,0
va (VaSet
font "Arial,8,1"
)
xt "85200,85000,95000,86000"
st "FAD_main_with_w53002"
blo "85200,85800"
tm "CptNameMgr"
)
*177 (Text
uid 3290,0
va (VaSet
font "Arial,8,1"
)
xt "85200,86000,86200,87000"
st "I0"
blo "85200,86800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 3291,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 3292,0
text (MLText
uid 3293,0
va (VaSet
font "Courier New,8,0"
)
xt "83000,18200,103000,19000"
st "RAMADDRWIDTH64b = 15    ( integer )  "
)
header ""
)
elements [
(GiElement
name "RAMADDRWIDTH64b"
type "integer"
value "15"
)
]
)
viewicon (ZoomableIcon
uid 3294,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "81250,89250,82750,90750"
iconName "BlockDiagram.png"
iconMaskName "BlockDiagram.msk"
ftype 1
)
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*178 (Wire
uid 286,0
shape (OrthoPolyLine
uid 287,0
va (VaSet
vasetType 3
)
xt "58750,21000,80250,21000"
pts [
"58750,21000"
"80250,21000"
]
)
start &13
end &136
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 288,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 289,0
va (VaSet
)
xt "71000,20000,72300,21000"
st "clk"
blo "71000,20800"
tm "WireNameMgr"
)
)
on &18
)
*179 (Wire
uid 318,0
shape (OrthoPolyLine
uid 319,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "109750,21000,122250,21000"
pts [
"109750,21000"
"122250,21000"
]
)
start &128
end &101
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 320,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 321,0
va (VaSet
)
xt "111000,20000,117000,21000"
st "wiz_addr : (9:0)"
blo "111000,20800"
tm "WireNameMgr"
)
)
on &19
)
*180 (Wire
uid 324,0
shape (OrthoPolyLine
uid 325,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "109750,22000,122250,22000"
pts [
"109750,22000"
"122250,22000"
]
)
start &129
end &102
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 326,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 327,0
va (VaSet
)
xt "111000,21000,117300,22000"
st "wiz_data : (15:0)"
blo "111000,21800"
tm "WireNameMgr"
)
)
on &20
)
*181 (Wire
uid 330,0
shape (OrthoPolyLine
uid 331,0
va (VaSet
vasetType 3
)
xt "109750,25000,122250,25000"
pts [
"109750,25000"
"122250,25000"
]
)
start &132
end &103
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 332,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 333,0
va (VaSet
)
xt "111000,24000,113600,25000"
st "wiz_rd"
blo "111000,24800"
tm "WireNameMgr"
)
)
on &21
)
*182 (Wire
uid 336,0
shape (OrthoPolyLine
uid 337,0
va (VaSet
vasetType 3
)
xt "109750,26000,122250,26000"
pts [
"109750,26000"
"122250,26000"
]
)
start &131
end &104
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 338,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 339,0
va (VaSet
)
xt "111000,25000,113700,26000"
st "wiz_wr"
blo "111000,25800"
tm "WireNameMgr"
)
)
on &22
)
*183 (Wire
uid 374,0
shape (OrthoPolyLine
uid 375,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "109750,42000,122250,48000"
pts [
"109750,42000"
"120000,42000"
"120000,48000"
"122250,48000"
]
)
start &150
end &26
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 376,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 377,0
va (VaSet
)
xt "111000,41000,117500,42000"
st "sensor_cs : (3:0)"
blo "111000,41800"
tm "WireNameMgr"
)
)
on &30
)
*184 (Wire
uid 380,0
shape (OrthoPolyLine
uid 381,0
va (VaSet
vasetType 3
)
xt "109750,51000,122250,51000"
pts [
"109750,51000"
"122250,51000"
]
)
start &147
end &24
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 382,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 383,0
va (VaSet
)
xt "111000,50000,112700,51000"
st "sclk"
blo "111000,50800"
tm "WireNameMgr"
)
)
on &31
)
*185 (Wire
uid 386,0
shape (OrthoPolyLine
uid 387,0
va (VaSet
vasetType 3
)
xt "109750,52000,122250,52000"
pts [
"109750,52000"
"122250,52000"
]
)
start &148
end &25
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 388,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 389,0
va (VaSet
)
xt "111000,51000,112400,52000"
st "sio"
blo "111000,51800"
tm "WireNameMgr"
)
)
on &32
)
*186 (Wire
uid 426,0
shape (OrthoPolyLine
uid 427,0
va (VaSet
vasetType 3
)
xt "58750,32000,80250,32000"
pts [
"58750,32000"
"80250,32000"
]
)
start &34
end &124
sat 32
eat 32
st 0
sf 1
tg (WTG
uid 428,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 429,0
va (VaSet
)
xt "71000,31000,73800,32000"
st "trigger"
blo "71000,31800"
tm "WireNameMgr"
)
)
on &38
)
*187 (Wire
uid 442,0
shape (OrthoPolyLine
uid 443,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "58000,34000,80250,42000"
pts [
"80250,34000"
"64000,34000"
"64000,42000"
"58000,42000"
]
)
start &126
end &39
sat 32
eat 2
sty 1
st 0
sf 1
si 0
tg (WTG
uid 446,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 447,0
va (VaSet
)
xt "71000,33000,76900,34000"
st "board_id : (3:0)"
blo "71000,33800"
tm "WireNameMgr"
)
)
on &43
)
*188 (Wire
uid 450,0
shape (OrthoPolyLine
uid 451,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "58000,35000,80250,43000"
pts [
"80250,35000"
"65000,35000"
"65000,43000"
"58000,43000"
]
)
start &127
end &39
sat 32
eat 2
sty 1
st 0
sf 1
si 0
tg (WTG
uid 454,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 455,0
va (VaSet
)
xt "71000,34000,76700,35000"
st "crate_id : (1:0)"
blo "71000,34800"
tm "WireNameMgr"
)
)
on &44
)
*189 (Wire
uid 530,0
shape (OrthoPolyLine
uid 531,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "58000,42000,80250,53000"
pts [
"80250,42000"
"68000,42000"
"68000,53000"
"58000,53000"
]
)
start &137
end &53
sat 32
eat 2
sty 1
st 0
sf 1
si 0
tg (WTG
uid 534,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 535,0
va (VaSet
)
xt "71000,41000,79000,42000"
st "adc_otr_array : (3:0)"
blo "71000,41800"
tm "WireNameMgr"
)
)
on &57
)
*190 (Wire
uid 538,0
shape (OrthoPolyLine
uid 539,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "58000,48000,80250,55000"
pts [
"80250,48000"
"70000,48000"
"70000,55000"
"58000,55000"
]
)
start &138
end &53
sat 32
eat 2
sty 1
st 0
sf 1
si 0
tg (WTG
uid 542,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 543,0
va (VaSet
)
xt "71000,47000,76900,48000"
st "adc_data_array"
blo "71000,47800"
tm "WireNameMgr"
)
)
on &58
)
*191 (Wire
uid 546,0
shape (OrthoPolyLine
uid 547,0
va (VaSet
vasetType 3
)
xt "58000,43000,80250,54000"
pts [
"80250,43000"
"69000,43000"
"69000,54000"
"58000,54000"
]
)
start &125
end &53
sat 32
eat 1
st 0
sf 1
si 0
tg (WTG
uid 550,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 551,0
va (VaSet
)
xt "71000,42000,74200,43000"
st "adc_oeb"
blo "71000,42800"
tm "WireNameMgr"
)
)
on &59
)
*192 (Wire
uid 554,0
shape (OrthoPolyLine
uid 555,0
va (VaSet
vasetType 3
)
xt "40750,54000,50000,54000"
pts [
"50000,54000"
"40750,54000"
]
)
start &53
end &49
sat 2
eat 32
st 0
sf 1
tg (WTG
uid 558,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 559,0
va (VaSet
)
xt "42000,53000,45200,54000"
st "adc_oeb"
blo "42000,53800"
tm "WireNameMgr"
)
)
on &59
)
*193 (Wire
uid 562,0
shape (OrthoPolyLine
uid 563,0
va (VaSet
vasetType 3
)
xt "40750,53000,50000,53000"
pts [
"40750,53000"
"50000,53000"
]
)
start &48
end &53
sat 32
eat 1
st 0
sf 1
tg (WTG
uid 566,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 567,0
va (VaSet
)
xt "42000,52000,44900,53000"
st "adc_otr"
blo "42000,52800"
tm "WireNameMgr"
)
)
on &60
)
*194 (Wire
uid 570,0
shape (OrthoPolyLine
uid 571,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "40750,55000,50000,55000"
pts [
"40750,55000"
"50000,55000"
]
)
start &47
end &53
sat 32
eat 1
sty 1
st 0
sf 1
tg (WTG
uid 574,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 575,0
va (VaSet
)
xt "42000,54000,48400,55000"
st "adc_data : (11:0)"
blo "42000,54800"
tm "WireNameMgr"
)
)
on &61
)
*195 (Wire
uid 578,0
shape (OrthoPolyLine
uid 579,0
va (VaSet
vasetType 3
)
xt "24000,53000,29250,53000"
pts [
"29250,53000"
"24000,53000"
]
)
start &46
sat 32
eat 16
st 0
sf 1
tg (WTG
uid 582,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 583,0
va (VaSet
)
xt "25000,52000,29000,53000"
st "ADC_CLK"
blo "25000,52800"
tm "WireNameMgr"
)
)
on &98
)
*196 (Wire
uid 769,0
shape (OrthoPolyLine
uid 770,0
va (VaSet
vasetType 3
)
xt "109750,24000,116000,24000"
pts [
"109750,24000"
"116000,24000"
]
)
start &122
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 773,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 774,0
va (VaSet
)
xt "111000,23000,114600,24000"
st "wiz_reset"
blo "111000,23800"
tm "WireNameMgr"
)
)
on &62
)
*197 (Wire
uid 777,0
shape (OrthoPolyLine
uid 778,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "109750,70000,116000,70000"
pts [
"109750,70000"
"116000,70000"
]
)
start &123
sat 32
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 781,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 782,0
va (VaSet
)
xt "111000,69000,115000,70000"
st "led : (7:0)"
blo "111000,69800"
tm "WireNameMgr"
)
)
on &63
)
*198 (Wire
uid 785,0
shape (OrthoPolyLine
uid 786,0
va (VaSet
vasetType 3
)
xt "109750,28000,122250,28000"
pts [
"109750,28000"
"122250,28000"
]
)
start &130
end &106
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 789,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 790,0
va (VaSet
)
xt "111000,27000,113700,28000"
st "wiz_cs"
blo "111000,27800"
tm "WireNameMgr"
)
)
on &64
)
*199 (Wire
uid 793,0
shape (OrthoPolyLine
uid 794,0
va (VaSet
vasetType 3
)
xt "109750,27000,122250,27000"
pts [
"122250,27000"
"109750,27000"
]
)
start &105
end &133
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 797,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 798,0
va (VaSet
)
xt "111000,26000,113700,27000"
st "wiz_int"
blo "111000,26800"
tm "WireNameMgr"
)
)
on &65
)
*200 (Wire
uid 801,0
shape (OrthoPolyLine
uid 802,0
va (VaSet
vasetType 3
)
xt "109750,40000,116000,40000"
pts [
"109750,40000"
"116000,40000"
]
)
start &149
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 805,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 806,0
va (VaSet
)
xt "111000,39000,113800,40000"
st "dac_cs"
blo "111000,39800"
tm "WireNameMgr"
)
)
on &66
)
*201 (Wire
uid 809,0
shape (OrthoPolyLine
uid 810,0
va (VaSet
vasetType 3
)
xt "109750,53000,116000,53000"
pts [
"109750,53000"
"116000,53000"
]
)
start &151
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 813,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 814,0
va (VaSet
)
xt "111000,52000,113000,53000"
st "mosi"
blo "111000,52800"
tm "WireNameMgr"
)
)
on &67
)
*202 (Wire
uid 817,0
shape (OrthoPolyLine
uid 818,0
va (VaSet
vasetType 3
)
xt "70000,66000,80250,66000"
pts [
"80250,66000"
"70000,66000"
]
)
start &152
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 821,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 822,0
va (VaSet
)
xt "71000,65000,74000,66000"
st "denable"
blo "71000,65800"
tm "WireNameMgr"
)
)
on &68
)
*203 (Wire
uid 825,0
shape (OrthoPolyLine
uid 826,0
va (VaSet
vasetType 3
)
xt "70000,23000,80250,23000"
pts [
"80250,23000"
"70000,23000"
]
)
start &134
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 829,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 830,0
va (VaSet
)
xt "71000,22000,75500,23000"
st "CLK_25_PS"
blo "71000,22800"
tm "WireNameMgr"
)
)
on &69
)
*204 (Wire
uid 833,0
shape (OrthoPolyLine
uid 834,0
va (VaSet
vasetType 3
)
xt "70000,22000,80250,22000"
pts [
"80250,22000"
"70000,22000"
]
)
start &135
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 837,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 838,0
va (VaSet
)
xt "71000,21000,74100,22000"
st "CLK_50"
blo "71000,21800"
tm "WireNameMgr"
)
)
on &70
)
*205 (Wire
uid 841,0
shape (OrthoPolyLine
uid 842,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "70000,62000,80250,62000"
pts [
"80250,62000"
"70000,62000"
]
)
start &139
sat 32
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 845,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 846,0
va (VaSet
)
xt "71000,61000,79500,62000"
st "drs_channel_id : (3:0)"
blo "71000,61800"
tm "WireNameMgr"
)
)
on &71
)
*206 (Wire
uid 849,0
shape (OrthoPolyLine
uid 850,0
va (VaSet
vasetType 3
)
xt "70000,67000,80250,67000"
pts [
"80250,67000"
"70000,67000"
]
)
start &140
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 853,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 854,0
va (VaSet
)
xt "71000,66000,75300,67000"
st "drs_dwrite"
blo "71000,66800"
tm "WireNameMgr"
)
)
on &72
)
*207 (Wire
uid 857,0
shape (OrthoPolyLine
uid 858,0
va (VaSet
vasetType 3
)
xt "70000,64000,80250,64000"
pts [
"80250,64000"
"70000,64000"
]
)
start &145
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 861,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 862,0
va (VaSet
)
xt "71000,63000,75200,64000"
st "RSRLOAD"
blo "71000,63800"
tm "WireNameMgr"
)
)
on &73
)
*208 (Wire
uid 865,0
shape (OrthoPolyLine
uid 866,0
va (VaSet
vasetType 3
)
xt "70000,65000,80250,65000"
pts [
"80250,65000"
"70000,65000"
]
)
start &146
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 869,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 870,0
va (VaSet
)
xt "71000,64000,74000,65000"
st "SRCLK"
blo "71000,64800"
tm "WireNameMgr"
)
)
on &74
)
*209 (Wire
uid 873,0
shape (OrthoPolyLine
uid 874,0
va (VaSet
vasetType 3
)
xt "70000,58000,80250,58000"
pts [
"70000,58000"
"80250,58000"
]
)
end &141
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 877,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 878,0
va (VaSet
)
xt "71000,57000,76400,58000"
st "SROUT_in_0"
blo "71000,57800"
tm "WireNameMgr"
)
)
on &75
)
*210 (Wire
uid 881,0
shape (OrthoPolyLine
uid 882,0
va (VaSet
vasetType 3
)
xt "70000,59000,80250,59000"
pts [
"70000,59000"
"80250,59000"
]
)
end &142
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 885,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 886,0
va (VaSet
)
xt "71000,58000,76400,59000"
st "SROUT_in_1"
blo "71000,58800"
tm "WireNameMgr"
)
)
on &76
)
*211 (Wire
uid 889,0
shape (OrthoPolyLine
uid 890,0
va (VaSet
vasetType 3
)
xt "70000,60000,80250,60000"
pts [
"70000,60000"
"80250,60000"
]
)
end &143
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 893,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 894,0
va (VaSet
)
xt "71000,59000,76400,60000"
st "SROUT_in_2"
blo "71000,59800"
tm "WireNameMgr"
)
)
on &77
)
*212 (Wire
uid 897,0
shape (OrthoPolyLine
uid 898,0
va (VaSet
vasetType 3
)
xt "70000,61000,80250,61000"
pts [
"70000,61000"
"80250,61000"
]
)
end &144
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 901,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 902,0
va (VaSet
)
xt "71000,60000,76400,61000"
st "SROUT_in_3"
blo "71000,60800"
tm "WireNameMgr"
)
)
on &78
)
*213 (Wire
uid 1437,0
shape (OrthoPolyLine
uid 1438,0
va (VaSet
vasetType 3
)
xt "73000,72000,80250,72000"
pts [
"80250,72000"
"73000,72000"
]
)
start &153
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 1441,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1442,0
va (VaSet
)
xt "76000,72000,79700,73000"
st "SRIN_out"
blo "76000,72800"
tm "WireNameMgr"
)
)
on &79
)
*214 (Wire
uid 1445,0
shape (OrthoPolyLine
uid 1446,0
va (VaSet
vasetType 3
)
xt "109750,80000,115000,80000"
pts [
"109750,80000"
"115000,80000"
]
)
start &155
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 1449,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1450,0
va (VaSet
)
xt "111000,79000,113500,80000"
st "amber"
blo "111000,79800"
tm "WireNameMgr"
)
)
on &80
)
*215 (Wire
uid 1453,0
shape (OrthoPolyLine
uid 1454,0
va (VaSet
vasetType 3
)
xt "109750,79000,114000,79000"
pts [
"109750,79000"
"114000,79000"
]
)
start &156
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 1457,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1458,0
va (VaSet
)
xt "111000,78000,112500,79000"
st "red"
blo "111000,78800"
tm "WireNameMgr"
)
)
on &81
)
*216 (Wire
uid 1461,0
shape (OrthoPolyLine
uid 1462,0
va (VaSet
vasetType 3
)
xt "109750,78000,114000,78000"
pts [
"109750,78000"
"114000,78000"
]
)
start &154
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 1465,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1466,0
va (VaSet
)
xt "111000,77000,113400,78000"
st "green"
blo "111000,77800"
tm "WireNameMgr"
)
)
on &82
)
*217 (Wire
uid 1469,0
shape (OrthoPolyLine
uid 1470,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "109750,77000,121000,77000"
pts [
"109750,77000"
"121000,77000"
]
)
start &160
sat 32
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 1473,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1474,0
va (VaSet
)
xt "111000,76000,119600,77000"
st "counter_result : (11:0)"
blo "111000,76800"
tm "WireNameMgr"
)
)
on &83
)
*218 (Wire
uid 1477,0
shape (OrthoPolyLine
uid 1478,0
va (VaSet
vasetType 3
)
xt "109750,75000,120000,75000"
pts [
"109750,75000"
"120000,75000"
]
)
start &162
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 1481,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1482,0
va (VaSet
)
xt "111000,74000,119200,75000"
st "alarm_refclk_too_low"
blo "111000,74800"
tm "WireNameMgr"
)
)
on &84
)
*219 (Wire
uid 1485,0
shape (OrthoPolyLine
uid 1486,0
va (VaSet
vasetType 3
)
xt "109750,74000,121000,74000"
pts [
"109750,74000"
"121000,74000"
]
)
start &161
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 1489,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1490,0
va (VaSet
)
xt "111000,73000,119600,74000"
st "alarm_refclk_too_high"
blo "111000,73800"
tm "WireNameMgr"
)
)
on &85
)
*220 (Wire
uid 1503,0
shape (OrthoPolyLine
uid 1504,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "73000,75000,80250,75000"
pts [
"73000,75000"
"80250,75000"
]
)
end &157
sat 16
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 1507,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1508,0
va (VaSet
)
xt "74000,74000,79500,75000"
st "D_T_in : (1:0)"
blo "74000,74800"
tm "WireNameMgr"
)
)
on &90
)
*221 (Wire
uid 1529,0
shape (OrthoPolyLine
uid 1530,0
va (VaSet
vasetType 3
)
xt "66750,76000,80250,79000"
pts [
"66750,79000"
"70000,79000"
"70000,76000"
"80250,76000"
]
)
start &92
end &158
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 1531,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1532,0
va (VaSet
)
xt "68750,78000,72650,79000"
st "REF_CLK"
blo "68750,78800"
tm "WireNameMgr"
)
)
on &99
)
*222 (Wire
uid 1533,0
shape (OrthoPolyLine
uid 1534,0
va (VaSet
vasetType 3
)
xt "35000,70000,45000,70000"
pts [
"35000,70000"
"45000,70000"
]
)
start &86
sat 2
eat 16
st 0
sf 1
si 0
tg (WTG
uid 1539,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1540,0
va (VaSet
)
xt "37000,69000,42500,70000"
st "D_T_in : (1:0)"
blo "37000,69800"
tm "WireNameMgr"
)
)
on &90
)
*223 (Wire
uid 1561,0
shape (OrthoPolyLine
uid 1562,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "72000,77000,80250,77000"
pts [
"72000,77000"
"80250,77000"
]
)
end &159
sat 16
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 1565,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1566,0
va (VaSet
)
xt "73000,76000,79100,77000"
st "plllock_in : (3:0)"
blo "73000,76800"
tm "WireNameMgr"
)
)
on &97
)
*224 (Wire
uid 1567,0
shape (OrthoPolyLine
uid 1568,0
va (VaSet
vasetType 3
)
xt "35000,71000,45000,71000"
pts [
"35000,71000"
"45000,71000"
]
)
start &86
sat 2
eat 16
st 0
sf 1
si 0
tg (WTG
uid 1573,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1574,0
va (VaSet
)
xt "37000,70000,43100,71000"
st "plllock_in : (3:0)"
blo "37000,70800"
tm "WireNameMgr"
)
)
on &97
)
*225 (Wire
uid 1684,0
shape (OrthoPolyLine
uid 1685,0
va (VaSet
vasetType 3
)
xt "70000,24000,80250,24000"
pts [
"80250,24000"
"70000,24000"
]
)
start &163
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 1688,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1689,0
va (VaSet
)
xt "71000,23000,75000,24000"
st "ADC_CLK"
blo "71000,23800"
tm "WireNameMgr"
)
)
on &98
)
*226 (Wire
uid 2707,0
shape (OrthoPolyLine
uid 2708,0
va (VaSet
vasetType 3
)
xt "109750,81000,122000,81000"
pts [
"109750,81000"
"122000,81000"
]
)
start &170
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 2711,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2712,0
va (VaSet
)
xt "111000,80000,121400,81000"
st "debug_data_ram_empty"
blo "111000,80800"
tm "WireNameMgr"
)
)
on &110
)
*227 (Wire
uid 2715,0
shape (OrthoPolyLine
uid 2716,0
va (VaSet
vasetType 3
)
xt "109750,82000,120000,82000"
pts [
"109750,82000"
"120000,82000"
]
)
start &171
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 2719,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2720,0
va (VaSet
)
xt "111000,81000,118500,82000"
st "debug_data_valid"
blo "111000,81800"
tm "WireNameMgr"
)
)
on &111
)
*228 (Wire
uid 2723,0
shape (OrthoPolyLine
uid 2724,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "109750,83000,119000,83000"
pts [
"109750,83000"
"119000,83000"
]
)
start &173
sat 32
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 2727,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2728,0
va (VaSet
)
xt "111000,82000,117900,83000"
st "DG_state : (7:0)"
blo "111000,82800"
tm "WireNameMgr"
)
)
on &112
)
*229 (Wire
uid 2731,0
shape (OrthoPolyLine
uid 2732,0
va (VaSet
vasetType 3
)
xt "109750,84000,120000,84000"
pts [
"109750,84000"
"120000,84000"
]
)
start &167
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 2735,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2736,0
va (VaSet
)
xt "111000,83000,119400,84000"
st "FTM_RS485_rx_en"
blo "111000,83800"
tm "WireNameMgr"
)
)
on &113
)
*230 (Wire
uid 2739,0
shape (OrthoPolyLine
uid 2740,0
va (VaSet
vasetType 3
)
xt "109750,85000,120000,85000"
pts [
"109750,85000"
"120000,85000"
]
)
start &166
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 2743,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2744,0
va (VaSet
)
xt "111000,84000,119100,85000"
st "FTM_RS485_tx_d"
blo "111000,84800"
tm "WireNameMgr"
)
)
on &114
)
*231 (Wire
uid 2747,0
shape (OrthoPolyLine
uid 2748,0
va (VaSet
vasetType 3
)
xt "109750,86000,120000,86000"
pts [
"109750,86000"
"120000,86000"
]
)
start &168
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 2751,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2752,0
va (VaSet
)
xt "111000,85000,119400,86000"
st "FTM_RS485_tx_en"
blo "111000,85800"
tm "WireNameMgr"
)
)
on &115
)
*232 (Wire
uid 2755,0
shape (OrthoPolyLine
uid 2756,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "109750,87000,123000,87000"
pts [
"109750,87000"
"123000,87000"
]
)
start &172
sat 32
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 2759,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2760,0
va (VaSet
)
xt "111000,86000,122400,87000"
st "mem_manager_state : (3:0)"
blo "111000,86800"
tm "WireNameMgr"
)
)
on &116
)
*233 (Wire
uid 2763,0
shape (OrthoPolyLine
uid 2764,0
va (VaSet
vasetType 3
)
xt "109750,88000,118000,88000"
pts [
"109750,88000"
"118000,88000"
]
)
start &164
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 2767,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2768,0
va (VaSet
)
xt "111000,87000,116600,88000"
st "trigger_veto"
blo "111000,87800"
tm "WireNameMgr"
)
)
on &117
)
*234 (Wire
uid 2771,0
shape (OrthoPolyLine
uid 2772,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "109750,89000,120000,89000"
pts [
"109750,89000"
"120000,89000"
]
)
start &169
sat 32
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 2775,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2776,0
va (VaSet
)
xt "111000,88000,119400,89000"
st "w5300_state : (7:0)"
blo "111000,88800"
tm "WireNameMgr"
)
)
on &118
)
*235 (Wire
uid 2779,0
shape (OrthoPolyLine
uid 2780,0
va (VaSet
vasetType 3
)
xt "74000,78000,80250,82000"
pts [
"74000,82000"
"80250,78000"
]
)
end &165
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 2783,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2784,0
va (VaSet
)
xt "73000,80000,81100,81000"
st "FTM_RS485_rx_d"
blo "73000,80800"
tm "WireNameMgr"
)
)
on &119
)
*236 (Wire
uid 2944,0
shape (OrthoPolyLine
uid 2945,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "109750,90000,124000,90000"
pts [
"109750,90000"
"124000,90000"
]
)
start &174
sat 32
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 2948,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2949,0
va (VaSet
)
xt "111000,89000,122900,90000"
st "socket_tx_free_out : (16:0)"
blo "111000,89800"
tm "WireNameMgr"
)
)
on &120
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 1
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *237 (PackageList
uid 41,0
stg "VerticalLayoutStrategy"
textVec [
*238 (Text
uid 42,0
va (VaSet
font "arial,8,1"
)
xt "-87000,0,-81600,1000"
st "Package List"
blo "-87000,800"
)
*239 (MLText
uid 43,0
va (VaSet
)
xt "-87000,1000,-72500,11000"
st "LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

LIBRARY FACT_FAD_lib;
USE FACT_FAD_lib.fad_definitions.all;
USE ieee.std_logic_textio.all;
LIBRARY std;
USE std.textio.all;"
tm "PackageList"
)
]
)
compDirBlock (MlTextGroup
uid 44,0
stg "VerticalLayoutStrategy"
textVec [
*240 (Text
uid 45,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,0,28100,1000"
st "Compiler Directives"
blo "20000,800"
)
*241 (Text
uid 46,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,1000,29600,2000"
st "Pre-module directives:"
blo "20000,1800"
)
*242 (MLText
uid 47,0
va (VaSet
isHidden 1
)
xt "20000,2000,27500,4000"
st "`resetall
`timescale 1ns/10ps"
tm "BdCompilerDirectivesTextMgr"
)
*243 (Text
uid 48,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,4000,30100,5000"
st "Post-module directives:"
blo "20000,4800"
)
*244 (MLText
uid 49,0
va (VaSet
isHidden 1
)
xt "20000,0,20000,0"
tm "BdCompilerDirectivesTextMgr"
)
*245 (Text
uid 50,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,5000,29900,6000"
st "End-module directives:"
blo "20000,5800"
)
*246 (MLText
uid 51,0
va (VaSet
isHidden 1
)
xt "20000,6000,20000,6000"
tm "BdCompilerDirectivesTextMgr"
)
]
associable 1
)
windowSize "0,0,1281,1024"
viewArea "53400,13900,168726,105965"
cachedDiagramExtent "-92000,0,146000,98000"
pageSetupInfo (PageSetupInfo
ptrCmd ""
toPrinter 1
exportedDirectories [
"$HDS_PROJECT_DIR/HTMLExport"
]
exportStdIncludeRefs 1
exportStdPackageRefs 1
)
hasePageBreakOrigin 1
pageBreakOrigin "-146000,0"
lastUid 3415,0
defaultCommentText (CommentText
shape (Rectangle
layer 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
lineColor "0,0,32768"
)
xt "0,0,15000,5000"
)
text (MLText
va (VaSet
fg "0,0,32768"
)
xt "200,200,2000,1200"
st "
Text
"
tm "CommentText"
wrapOption 3
visibleHeight 4600
visibleWidth 14600
)
)
defaultPanel (Panel
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "32768,0,0"
lineWidth 2
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (Text
va (VaSet
font "Arial,8,1"
)
xt "1000,1000,3800,2000"
st "Panel0"
blo "1000,1800"
tm "PanelText"
)
)
)
defaultBlk (Blk
shape (Rectangle
va (VaSet
vasetType 1
fg "39936,56832,65280"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*247 (Text
va (VaSet
font "Arial,8,1"
)
xt "2200,3500,5800,4500"
st "<library>"
blo "2200,4300"
tm "BdLibraryNameMgr"
)
*248 (Text
va (VaSet
font "Arial,8,1"
)
xt "2200,4500,5600,5500"
st "<block>"
blo "2200,5300"
tm "BlkNameMgr"
)
*249 (Text
va (VaSet
font "Arial,8,1"
)
xt "2200,5500,3200,6500"
st "I0"
blo "2200,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "2200,13500,2200,13500"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
)
defaultMWComponent (MWC
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*250 (Text
va (VaSet
font "Arial,8,1"
)
xt "550,3500,3450,4500"
st "Library"
blo "550,4300"
)
*251 (Text
va (VaSet
font "Arial,8,1"
)
xt "550,4500,7450,5500"
st "MWComponent"
blo "550,5300"
)
*252 (Text
va (VaSet
font "Arial,8,1"
)
xt "550,5500,1550,6500"
st "I0"
blo "550,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-6450,1500,-6450,1500"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
visOptions (mwParamsVisibilityOptions
)
)
defaultSaComponent (SaComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*253 (Text
va (VaSet
font "Arial,8,1"
)
xt "900,3500,3800,4500"
st "Library"
blo "900,4300"
tm "BdLibraryNameMgr"
)
*254 (Text
va (VaSet
font "Arial,8,1"
)
xt "900,4500,7100,5500"
st "SaComponent"
blo "900,5300"
tm "CptNameMgr"
)
*255 (Text
va (VaSet
font "Arial,8,1"
)
xt "900,5500,1900,6500"
st "I0"
blo "900,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-6100,1500,-6100,1500"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
defaultVhdlComponent (VhdlComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*256 (Text
va (VaSet
font "Arial,8,1"
)
xt "500,3500,3400,4500"
st "Library"
blo "500,4300"
)
*257 (Text
va (VaSet
font "Arial,8,1"
)
xt "500,4500,7500,5500"
st "VhdlComponent"
blo "500,5300"
)
*258 (Text
va (VaSet
font "Arial,8,1"
)
xt "500,5500,1500,6500"
st "I0"
blo "500,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-6500,1500,-6500,1500"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
)
entityPath ""
archName ""
archPath ""
)
defaultVerilogComponent (VerilogComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-450,0,8450,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*259 (Text
va (VaSet
font "Arial,8,1"
)
xt "50,3500,2950,4500"
st "Library"
blo "50,4300"
)
*260 (Text
va (VaSet
font "Arial,8,1"
)
xt "50,4500,7950,5500"
st "VerilogComponent"
blo "50,5300"
)
*261 (Text
va (VaSet
font "Arial,8,1"
)
xt "50,5500,1050,6500"
st "I0"
blo "50,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-6950,1500,-6950,1500"
)
header ""
)
elements [
]
)
entityPath ""
)
defaultHdlText (HdlText
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,37120"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*262 (Text
va (VaSet
font "Arial,8,1"
)
xt "3150,4000,4850,5000"
st "eb1"
blo "3150,4800"
tm "HdlTextNameMgr"
)
*263 (Text
va (VaSet
font "Arial,8,1"
)
xt "3150,5000,3950,6000"
st "1"
blo "3150,5800"
tm "HdlTextNumberMgr"
)
]
)
viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
)
defaultEmbeddedText (EmbeddedText
commentText (CommentText
ps "CenterOffsetStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,18000,5000"
)
text (MLText
va (VaSet
)
xt "200,200,2000,1200"
st "
Text
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 4600
visibleWidth 17600
)
)
)
defaultGlobalConnector (GlobalConnector
shape (Circle
va (VaSet
vasetType 1
fg "65535,65535,0"
)
xt "-1000,-1000,1000,1000"
radius 1000
)
name (Text
va (VaSet
font "Arial,8,1"
)
xt "-500,-500,500,500"
st "G"
blo "-500,300"
)
)
defaultRipper (Ripper
ps "OnConnectorStrategy"
shape (Line2D
pts [
"0,0"
"1000,1000"
]
va (VaSet
vasetType 1
)
xt "0,0,1000,1000"
)
)
defaultBdJunction (BdJunction
ps "OnConnectorStrategy"
shape (Circle
va (VaSet
vasetType 1
)
xt "-400,-400,400,400"
radius 400
)
)
defaultPortIoIn (PortIoIn
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "-2000,-375,-500,375"
)
(Line
sl 0
ro 270
xt "-500,0,0,0"
pts [
"-500,0"
"0,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "-1375,-1000,-1375,-1000"
ju 2
blo "-1375,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoOut (PortIoOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "500,-375,2000,375"
)
(Line
sl 0
ro 270
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "625,-1000,625,-1000"
blo "625,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoInOut (PortIoInOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultPortIoBuffer (PortIoBuffer
shape (CompositeShape
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultSignal (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,0,1900,1000"
st "sig0"
blo "0,800"
tm "WireNameMgr"
)
)
)
defaultBus (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineWidth 2
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,0,2400,1000"
st "dbus0"
blo "0,800"
tm "WireNameMgr"
)
)
)
defaultBundle (Bundle
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineColor "32768,0,0"
lineWidth 2
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
textGroup (BiTextGroup
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
first (Text
va (VaSet
)
xt "0,0,3000,1000"
st "bundle0"
blo "0,800"
tm "BundleNameMgr"
)
second (MLText
va (VaSet
)
xt "0,1000,1000,2000"
st "()"
tm "BundleContentsMgr"
)
)
bundleNet &0
)
defaultPortMapFrame (PortMapFrame
ps "PortMapFrameStrategy"
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,10000,12000"
)
portMapText (BiTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
first (MLText
va (VaSet
)
)
second (MLText
va (VaSet
)
tm "PortMapTextMgr"
)
)
)
defaultGenFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "26368,26368,26368"
lineStyle 2
lineWidth 2
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1100,12600,-100"
st "g0: FOR i IN 0 TO n GENERATE"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1250,1450"
)
num (Text
va (VaSet
)
xt "250,250,1050,1250"
st "1"
blo "250,1050"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*264 (Text
va (VaSet
font "Arial,8,1"
)
xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*265 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
)
]
)
)
defaultBlockFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "26368,26368,26368"
lineStyle 1
lineWidth 2
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1100,7400,-100"
st "b0: BLOCK (guard)"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1250,1450"
)
num (Text
va (VaSet
)
xt "250,250,1050,1250"
st "1"
blo "250,1050"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*266 (Text
va (VaSet
font "Arial,8,1"
)
xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*267 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
)
]
)
style 3
)
defaultSaCptPort (CptPort
ps "OnEdgeStrategy"
shape (Triangle
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1800,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultSaCptPortBuffer (CptPort
ps "OnEdgeStrategy"
shape (Diamond
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1800,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
m 3
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultDeclText (MLText
va (VaSet
font "Courier New,8,0"
)
)
archDeclarativeBlock (BdArchDeclBlock
uid 1,0
stg "BdArchDeclBlockLS"
declLabel (Text
uid 2,0
va (VaSet
font "Arial,8,1"
)
xt "-92000,21600,-86600,22600"
st "Declarations"
blo "-92000,22400"
)
portLabel (Text
uid 3,0
va (VaSet
font "Arial,8,1"
)
xt "-92000,22600,-89300,23600"
st "Ports:"
blo "-92000,23400"
)
preUserLabel (Text
uid 4,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "-92000,21600,-88200,22600"
st "Pre User:"
blo "-92000,22400"
)
preUserText (MLText
uid 5,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "-92000,21600,-92000,21600"
tm "BdDeclarativeTextMgr"
)
diagSignalLabel (Text
uid 6,0
va (VaSet
font "Arial,8,1"
)
xt "-92000,23600,-84900,24600"
st "Diagram Signals:"
blo "-92000,24400"
)
postUserLabel (Text
uid 7,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "-92000,21600,-87300,22600"
st "Post User:"
blo "-92000,22400"
)
postUserText (MLText
uid 8,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "-92000,21600,-92000,21600"
tm "BdDeclarativeTextMgr"
)
)
commonDM (CommonDM
ldm (LogicalDM
suid 64,0
usingSuid 1
emptyRow *268 (LEmptyRow
)
uid 54,0
optionalChildren [
*269 (RefLabelRowHdr
)
*270 (TitleRowHdr
)
*271 (FilterRowHdr
)
*272 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*273 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*274 (GroupColHdr
tm "GroupColHdrMgr"
)
*275 (NameColHdr
tm "BlockDiagramNameColHdrMgr"
)
*276 (ModeColHdr
tm "BlockDiagramModeColHdrMgr"
)
*277 (TypeColHdr
tm "BlockDiagramTypeColHdrMgr"
)
*278 (BoundsColHdr
tm "BlockDiagramBoundsColHdrMgr"
)
*279 (InitColHdr
tm "BlockDiagramInitColHdrMgr"
)
*280 (EolColHdr
tm "BlockDiagramEolColHdrMgr"
)
*281 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "clk"
t "STD_LOGIC"
preAdd 0
posAdd 0
o 1
suid 1,0
)
)
uid 340,0
)
*282 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "wiz_addr"
t "std_logic_vector"
b "(9 DOWNTO 0)"
o 2
suid 2,0
)
)
uid 342,0
)
*283 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "wiz_data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 3
suid 3,0
)
)
uid 344,0
)
*284 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "wiz_rd"
t "std_logic"
o 4
suid 4,0
i "'1'"
)
)
uid 346,0
)
*285 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "wiz_wr"
t "std_logic"
o 5
suid 5,0
i "'1'"
)
)
uid 348,0
)
*286 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "sensor_cs"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 6
suid 6,0
)
)
uid 404,0
)
*287 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "sclk"
t "std_logic"
o 7
suid 7,0
)
)
uid 406,0
)
*288 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "sio"
t "std_logic"
preAdd 0
posAdd 0
o 8
suid 8,0
)
)
uid 408,0
)
*289 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "trigger"
t "std_logic"
preAdd 0
posAdd 0
o 9
suid 9,0
)
)
uid 456,0
)
*290 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "board_id"
t "std_logic_vector"
b "(3 downto 0)"
preAdd 0
posAdd 0
o 10
suid 10,0
)
)
uid 458,0
)
*291 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "crate_id"
t "std_logic_vector"
b "(1 downto 0)"
o 11
suid 11,0
)
)
uid 460,0
)
*292 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "adc_otr_array"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 12
suid 12,0
)
)
uid 584,0
)
*293 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "adc_data_array"
t "adc_data_array_type"
o 13
suid 13,0
)
)
uid 586,0
)
*294 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "adc_oeb"
t "std_logic"
preAdd 0
posAdd 0
o 14
suid 14,0
)
)
uid 588,0
)
*295 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "adc_otr"
t "STD_LOGIC"
preAdd 0
posAdd 0
o 16
suid 16,0
)
)
uid 590,0
)
*296 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "adc_data"
t "std_logic_vector"
b "(11 DOWNTO 0)"
preAdd 0
posAdd 0
o 17
suid 17,0
)
)
uid 592,0
)
*297 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "wiz_reset"
t "std_logic"
o 21
suid 23,0
i "'1'"
)
)
uid 903,0
)
*298 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "led"
t "std_logic_vector"
b "(7 DOWNTO 0)"
posAdd 0
o 22
suid 24,0
i "(OTHERS => '0')"
)
)
uid 905,0
)
*299 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "wiz_cs"
t "std_logic"
o 23
suid 25,0
i "'1'"
)
)
uid 907,0
)
*300 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "wiz_int"
t "std_logic"
o 24
suid 26,0
)
)
uid 909,0
)
*301 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "dac_cs"
t "std_logic"
o 25
suid 27,0
)
)
uid 911,0
)
*302 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "mosi"
t "std_logic"
o 26
suid 28,0
i "'0'"
)
)
uid 913,0
)
*303 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "denable"
t "std_logic"
eolc "-- default domino wave off"
posAdd 0
o 27
suid 29,0
i "'0'"
)
)
uid 915,0
)
*304 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "CLK_25_PS"
t "std_logic"
o 28
suid 30,0
)
)
uid 917,0
)
*305 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "CLK_50"
t "std_logic"
o 29
suid 31,0
)
)
uid 919,0
)
*306 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "drs_channel_id"
t "std_logic_vector"
b "(3 downto 0)"
o 30
suid 32,0
i "(others => '0')"
)
)
uid 921,0
)
*307 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "drs_dwrite"
t "std_logic"
o 31
suid 33,0
i "'1'"
)
)
uid 923,0
)
*308 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "RSRLOAD"
t "std_logic"
o 32
suid 34,0
i "'0'"
)
)
uid 925,0
)
*309 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "SRCLK"
t "std_logic"
o 33
suid 35,0
i "'0'"
)
)
uid 927,0
)
*310 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "SROUT_in_0"
t "std_logic"
o 30
suid 36,0
)
)
uid 929,0
)
*311 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "SROUT_in_1"
t "std_logic"
o 31
suid 37,0
)
)
uid 931,0
)
*312 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "SROUT_in_2"
t "std_logic"
o 32
suid 38,0
)
)
uid 933,0
)
*313 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "SROUT_in_3"
t "std_logic"
o 33
suid 39,0
)
)
uid 935,0
)
*314 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "SRIN_out"
t "std_logic"
o 34
suid 40,0
i "'0'"
)
)
uid 1541,0
)
*315 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "amber"
t "std_logic"
o 35
suid 41,0
)
)
uid 1543,0
)
*316 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "red"
t "std_logic"
o 36
suid 42,0
)
)
uid 1545,0
)
*317 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "green"
t "std_logic"
o 37
suid 43,0
)
)
uid 1547,0
)
*318 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "counter_result"
t "std_logic_vector"
b "(11 DOWNTO 0)"
o 38
suid 44,0
)
)
uid 1549,0
)
*319 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "alarm_refclk_too_low"
t "std_logic"
posAdd 0
o 39
suid 45,0
)
)
uid 1551,0
)
*320 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "alarm_refclk_too_high"
t "std_logic"
o 40
suid 46,0
)
)
uid 1553,0
)
*321 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "D_T_in"
t "std_logic_vector"
b "(1 DOWNTO 0)"
o 41
suid 47,0
)
)
uid 1555,0
)
*322 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "plllock_in"
t "std_logic_vector"
b "(3 DOWNTO 0)"
eolc "-- high level, if dominowave is running and DRS PLL locked"
o 43
suid 49,0
)
)
uid 1575,0
)
*323 (LeafLogPort
port (LogicalPort
lang 2
m 4
decl (Decl
n "ADC_CLK"
t "std_logic"
o 44
suid 50,0
)
)
uid 1690,0
)
*324 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "REF_CLK"
t "STD_LOGIC"
o 42
suid 51,0
i "'0'"
)
)
uid 2003,0
)
*325 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "debug_data_ram_empty"
t "std_logic"
o 45
suid 53,0
)
)
uid 2785,0
)
*326 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "debug_data_valid"
t "std_logic"
o 46
suid 54,0
)
)
uid 2787,0
)
*327 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "DG_state"
t "std_logic_vector"
b "(7 downto 0)"
prec "-- for debugging"
preAdd 0
o 47
suid 55,0
)
)
uid 2789,0
)
*328 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "FTM_RS485_rx_en"
t "std_logic"
o 48
suid 56,0
)
)
uid 2791,0
)
*329 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "FTM_RS485_tx_d"
t "std_logic"
o 49
suid 57,0
)
)
uid 2793,0
)
*330 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "FTM_RS485_tx_en"
t "std_logic"
o 50
suid 58,0
)
)
uid 2795,0
)
*331 (LeafLogPort
port (LogicalPort
lang 2
m 4
decl (Decl
n "mem_manager_state"
t "std_logic_vector"
b "(3 DOWNTO 0)"
eolc "-- state is encoded here ... useful for debugging."
posAdd 0
o 51
suid 59,0
)
)
uid 2797,0
)
*332 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "trigger_veto"
t "std_logic"
o 52
suid 60,0
i "'1'"
)
)
uid 2799,0
)
*333 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "w5300_state"
t "std_logic_vector"
b "(7 DOWNTO 0)"
eolc "-- state is encoded here ... useful for debugging."
posAdd 0
o 53
suid 61,0
)
)
uid 2801,0
)
*334 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "FTM_RS485_rx_d"
t "std_logic"
o 54
suid 62,0
)
)
uid 2803,0
)
*335 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "socket_tx_free_out"
t "std_logic_vector"
b "(16 DOWNTO 0)"
eolc "-- 17bit value .. that's true"
posAdd 0
o 55
suid 64,0
)
)
uid 2950,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 67,0
optionalChildren [
*336 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *337 (MRCItem
litem &268
pos 55
dimension 20
)
uid 69,0
optionalChildren [
*338 (MRCItem
litem &269
pos 0
dimension 20
uid 70,0
)
*339 (MRCItem
litem &270
pos 1
dimension 23
uid 71,0
)
*340 (MRCItem
litem &271
pos 2
hidden 1
dimension 20
uid 72,0
)
*341 (MRCItem
litem &281
pos 0
dimension 20
uid 341,0
)
*342 (MRCItem
litem &282
pos 1
dimension 20
uid 343,0
)
*343 (MRCItem
litem &283
pos 2
dimension 20
uid 345,0
)
*344 (MRCItem
litem &284
pos 3
dimension 20
uid 347,0
)
*345 (MRCItem
litem &285
pos 4
dimension 20
uid 349,0
)
*346 (MRCItem
litem &286
pos 5
dimension 20
uid 405,0
)
*347 (MRCItem
litem &287
pos 6
dimension 20
uid 407,0
)
*348 (MRCItem
litem &288
pos 7
dimension 20
uid 409,0
)
*349 (MRCItem
litem &289
pos 8
dimension 20
uid 457,0
)
*350 (MRCItem
litem &290
pos 9
dimension 20
uid 459,0
)
*351 (MRCItem
litem &291
pos 10
dimension 20
uid 461,0
)
*352 (MRCItem
litem &292
pos 11
dimension 20
uid 585,0
)
*353 (MRCItem
litem &293
pos 12
dimension 20
uid 587,0
)
*354 (MRCItem
litem &294
pos 13
dimension 20
uid 589,0
)
*355 (MRCItem
litem &295
pos 14
dimension 20
uid 591,0
)
*356 (MRCItem
litem &296
pos 15
dimension 20
uid 593,0
)
*357 (MRCItem
litem &297
pos 16
dimension 20
uid 904,0
)
*358 (MRCItem
litem &298
pos 17
dimension 20
uid 906,0
)
*359 (MRCItem
litem &299
pos 18
dimension 20
uid 908,0
)
*360 (MRCItem
litem &300
pos 19
dimension 20
uid 910,0
)
*361 (MRCItem
litem &301
pos 20
dimension 20
uid 912,0
)
*362 (MRCItem
litem &302
pos 21
dimension 20
uid 914,0
)
*363 (MRCItem
litem &303
pos 22
dimension 20
uid 916,0
)
*364 (MRCItem
litem &304
pos 23
dimension 20
uid 918,0
)
*365 (MRCItem
litem &305
pos 24
dimension 20
uid 920,0
)
*366 (MRCItem
litem &306
pos 25
dimension 20
uid 922,0
)
*367 (MRCItem
litem &307
pos 26
dimension 20
uid 924,0
)
*368 (MRCItem
litem &308
pos 27
dimension 20
uid 926,0
)
*369 (MRCItem
litem &309
pos 28
dimension 20
uid 928,0
)
*370 (MRCItem
litem &310
pos 29
dimension 20
uid 930,0
)
*371 (MRCItem
litem &311
pos 30
dimension 20
uid 932,0
)
*372 (MRCItem
litem &312
pos 31
dimension 20
uid 934,0
)
*373 (MRCItem
litem &313
pos 32
dimension 20
uid 936,0
)
*374 (MRCItem
litem &314
pos 33
dimension 20
uid 1542,0
)
*375 (MRCItem
litem &315
pos 34
dimension 20
uid 1544,0
)
*376 (MRCItem
litem &316
pos 35
dimension 20
uid 1546,0
)
*377 (MRCItem
litem &317
pos 36
dimension 20
uid 1548,0
)
*378 (MRCItem
litem &318
pos 37
dimension 20
uid 1550,0
)
*379 (MRCItem
litem &319
pos 38
dimension 20
uid 1552,0
)
*380 (MRCItem
litem &320
pos 39
dimension 20
uid 1554,0
)
*381 (MRCItem
litem &321
pos 40
dimension 20
uid 1556,0
)
*382 (MRCItem
litem &322
pos 41
dimension 20
uid 1576,0
)
*383 (MRCItem
litem &323
pos 42
dimension 20
uid 1691,0
)
*384 (MRCItem
litem &324
pos 43
dimension 20
uid 2004,0
)
*385 (MRCItem
litem &325
pos 44
dimension 20
uid 2786,0
)
*386 (MRCItem
litem &326
pos 45
dimension 20
uid 2788,0
)
*387 (MRCItem
litem &327
pos 46
dimension 20
uid 2790,0
)
*388 (MRCItem
litem &328
pos 47
dimension 20
uid 2792,0
)
*389 (MRCItem
litem &329
pos 48
dimension 20
uid 2794,0
)
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