source: firmware/FAD/FACT_FAD_TB_lib/hds/led_controller_tb/struct.bd.bak@ 14207

DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
dmPackageRefs [
(DmPackageRef
library "ieee"
unitName "std_logic_1164"
itemName "ALL"
)
(DmPackageRef
library "ieee"
unitName "std_logic_arith"
itemName "ALL"
)
(DmPackageRef
library "ieee"
unitName "STD_LOGIC_UNSIGNED"
itemName "ALL"
)
(DmPackageRef
library "FACT_FAD_lib"
unitName "fad_definitions"
itemName "ALL"
)
]
instances [
(Instance
name "U_0"
duLibraryName "FACT_FAD_lib"
duName "led_controller"
elements [
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name "HEARTBEAT_PWM_DIVIDER"
type "integer"
value "500"
)
(GiElement
name "WAITING_DIVIDER"
type "integer"
value "500000000"
)
]
mwi 0
uid 53,0
)
(Instance
name "U_1"
duLibraryName "FACT_FAD_TB_lib"
duName "led_controller_tester"
elements [
]
mwi 0
uid 143,0
)
(Instance
name "U_2"
duLibraryName "FACT_FAD_TB_lib"
duName "clock_generator"
elements [
(GiElement
name "clock_period"
type "time"
value "20 ns"
)
(GiElement
name "reset_time"
type "time"
value "50 ns"
)
]
mwi 0
uid 424,0
)
]
libraryRefs [
"ieee"
"FACT_FAD_lib"
]
)
version "29.1"
appVersion "2009.1 (Build 12)"
noEmbeddedEditors 1
model (BlockDiag
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vvMap [
(vvPair
variable "HDLDir"
value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hdl"
)
(vvPair
variable "HDSDir"
value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\led_controller_tb\\struct.bd.info"
)
(vvPair
variable "SideDataUserDir"
value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\led_controller_tb\\struct.bd.user"
)
(vvPair
variable "SourceDir"
value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "struct"
)
(vvPair
variable "config"
value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\led_controller_tb"
)
(vvPair
variable "d_logical"
value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\led_controller_tb"
)
(vvPair
variable "date"
value "02.03.2011"
)
(vvPair
variable "day"
value "Mi"
)
(vvPair
variable "day_long"
value "Mittwoch"
)
(vvPair
variable "dd"
value "02"
)
(vvPair
variable "entity_name"
value "led_controller_tb"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "struct.bd"
)
(vvPair
variable "f_logical"
value "struct.bd"
)
(vvPair
variable "f_noext"
value "struct"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "IHP110"
)
(vvPair
variable "language"
value "VHDL"
)
(vvPair
variable "library"
value "FACT_FAD_TB_lib"
)
(vvPair
variable "library_downstream_HdsLintPlugin"
value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/designcheck"
)
(vvPair
variable "library_downstream_ISEPARInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
)
(vvPair
variable "library_downstream_ImpactInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/work"
)
(vvPair
variable "library_downstream_XSTDataPrep"
value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
)
(vvPair
variable "mm"
value "03"
)
(vvPair
variable "module_name"
value "led_controller_tb"
)
(vvPair
variable "month"
value "Mrz"
)
(vvPair
variable "month_long"
value "März"
)
(vvPair
variable "p"
value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\led_controller_tb\\struct.bd"
)
(vvPair
variable "p_logical"
value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\led_controller_tb\\struct.bd"
)
(vvPair
variable "package_name"
value "<Undefined Variable>"
)
(vvPair
variable "project_name"
value "FACT_FAD"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "D:\\modeltech_6.5e\\win32"
)
(vvPair
variable "task_NC-SimPath"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
)
(vvPair
variable "task_QuestaSimPath"
value "<TBD>"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "this_ext"
value "bd"
)
(vvPair
variable "this_file"
value "struct"
)
(vvPair
variable "this_file_logical"
value "struct"
)
(vvPair
variable "time"
value "09:54:46"
)
(vvPair
variable "unit"
value "led_controller_tb"
)
(vvPair
variable "user"
value "daqct3"
)
(vvPair
variable "version"
value "2009.1 (Build 12)"
)
(vvPair
variable "view"
value "struct"
)
(vvPair
variable "year"
value "2011"
)
(vvPair
variable "yy"
value "11"
)
]
)
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visibleWidth 20000
)
ignorePrefs 1
titleBlock 1
)
*35 (CommentText
uid 250,0
shape (Rectangle
uid 251,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "41000,46000,57000,47000"
)
oxt "39000,66000,55000,67000"
text (MLText
uid 252,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "41200,46000,45700,47000"
st "
%project_name
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 16000
)
position 1
ignorePrefs 1
titleBlock 1
)
*36 (CommentText
uid 253,0
shape (Rectangle
uid 254,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "16000,46000,37000,48000"
)
oxt "14000,66000,35000,68000"
text (MLText
uid 255,0
va (VaSet
fg "32768,0,0"
)
xt "23150,46500,29850,47500"
st "
<company name>
"
ju 0
tm "CommentText"
wrapOption 3
visibleHeight 2000
visibleWidth 21000
)
position 1
ignorePrefs 1
titleBlock 1
)
*37 (CommentText
uid 256,0
shape (Rectangle
uid 257,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "16000,49000,20000,50000"
)
oxt "14000,69000,18000,70000"
text (MLText
uid 258,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "16200,49000,18300,50000"
st "
Path:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*38 (CommentText
uid 259,0
shape (Rectangle
uid 260,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "16000,50000,20000,51000"
)
oxt "14000,70000,18000,71000"
text (MLText
uid 261,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "16200,50000,18900,51000"
st "
Edited:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*39 (CommentText
uid 262,0
shape (Rectangle
uid 263,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "20000,49000,37000,50000"
)
oxt "18000,69000,35000,70000"
text (MLText
uid 264,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "20200,49000,36400,50000"
st "
%library/%unit/%view
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
titleBlock 1
)
]
shape (GroupingShape
uid 234,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
lineWidth 2
)
xt "16000,46000,57000,51000"
)
oxt "14000,66000,55000,71000"
)
*40 (SaComponent
uid 424,0
optionalChildren [
*41 (CptPort
uid 413,0
ps "OnEdgeStrategy"
shape (Triangle
uid 414,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "7000,31625,7750,32375"
)
tg (CPTG
uid 415,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 416,0
va (VaSet
)
xt "4700,31500,6000,32500"
st "clk"
ju 2
blo "6000,32300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "clk"
t "std_logic"
preAdd 0
posAdd 0
o 1
suid 1,0
i "'0'"
)
)
)
*42 (CptPort
uid 417,0
ps "OnEdgeStrategy"
shape (Triangle
uid 418,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "7000,32625,7750,33375"
)
tg (CPTG
uid 419,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 420,0
va (VaSet
)
xt "4700,32500,6000,33500"
st "rst"
ju 2
blo "6000,33300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "rst"
t "std_logic"
preAdd 0
posAdd 0
o 2
suid 2,0
i "'0'"
)
)
)
]
shape (Rectangle
uid 425,0
va (VaSet
vasetType 1
fg "0,49152,49152"
lineColor "0,0,50000"
lineWidth 2
)
xt "-1000,31000,7000,35000"
)
oxt "22000,15000,30000,19000"
ttg (MlTextGroup
uid 426,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*43 (Text
uid 427,0
va (VaSet
font "Arial,8,1"
)
xt "-850,35000,6850,36000"
st "FACT_FAD_TB_lib"
blo "-850,35800"
tm "BdLibraryNameMgr"
)
*44 (Text
uid 428,0
va (VaSet
font "Arial,8,1"
)
xt "-850,36000,5850,37000"
st "clock_generator"
blo "-850,36800"
tm "CptNameMgr"
)
*45 (Text
uid 429,0
va (VaSet
font "Arial,8,1"
)
xt "-850,37000,950,38000"
st "U_2"
blo "-850,37800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 430,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 431,0
text (MLText
uid 432,0
va (VaSet
font "Courier New,8,0"
)
xt "-5000,29400,13500,31000"
st "clock_period = 20 ns    ( time )  
reset_time   = 50 ns    ( time )  "
)
header ""
)
elements [
(GiElement
name "clock_period"
type "time"
value "20 ns"
)
(GiElement
name "reset_time"
type "time"
value "50 ns"
)
]
)
viewicon (ZoomableIcon
uid 433,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "-750,33250,750,34750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*46 (Wire
uid 65,0
shape (OrthoPolyLine
uid 66,0
va (VaSet
vasetType 3
)
xt "18750,16000,30000,16000"
pts [
"18750,16000"
"30000,16000"
]
)
start &3
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 69,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 70,0
va (VaSet
)
xt "20000,15000,22400,16000"
st "green"
blo "20000,15800"
tm "WireNameMgr"
)
)
on &15
)
*47 (Wire
uid 73,0
shape (OrthoPolyLine
uid 74,0
va (VaSet
vasetType 3
)
xt "18750,17000,30000,17000"
pts [
"18750,17000"
"30000,17000"
]
)
start &4
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 77,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 78,0
va (VaSet
)
xt "20000,16000,22500,17000"
st "amber"
blo "20000,16800"
tm "WireNameMgr"
)
)
on &16
)
*48 (Wire
uid 81,0
shape (OrthoPolyLine
uid 82,0
va (VaSet
vasetType 3
)
xt "18750,18000,30000,18000"
pts [
"18750,18000"
"30000,18000"
]
)
start &5
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 85,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 86,0
va (VaSet
)
xt "20000,17000,21500,18000"
st "red"
blo "20000,17800"
tm "WireNameMgr"
)
)
on &17
)
*49 (Wire
uid 89,0
shape (OrthoPolyLine
uid 90,0
va (VaSet
vasetType 3
)
xt "18750,19000,30000,19000"
pts [
"18750,19000"
"30000,19000"
]
)
start &6
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 93,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 94,0
va (VaSet
)
xt "20000,18000,28500,19000"
st "additional_flasher_out"
blo "20000,18800"
tm "WireNameMgr"
)
)
on &18
)
*50 (Wire
uid 97,0
shape (OrthoPolyLine
uid 98,0
va (VaSet
vasetType 3
)
xt "-10000,16000,-750,16000"
pts [
"-10000,16000"
"-750,16000"
]
)
end &2
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 101,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 102,0
va (VaSet
)
xt "-9000,15000,-7100,16000"
st "CLK"
blo "-9000,15800"
tm "WireNameMgr"
)
)
on &19
)
*51 (Wire
uid 105,0
shape (OrthoPolyLine
uid 106,0
va (VaSet
vasetType 3
)
xt "-10000,17000,-750,17000"
pts [
"-10000,17000"
"-750,17000"
]
)
end &7
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 109,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 110,0
va (VaSet
)
xt "-9000,16000,-6200,17000"
st "trigger"
blo "-9000,16800"
tm "WireNameMgr"
)
)
on &20
)
*52 (Wire
uid 113,0
shape (OrthoPolyLine
uid 114,0
va (VaSet
vasetType 3
)
xt "-10000,18000,-750,18000"
pts [
"-10000,18000"
"-750,18000"
]
)
end &8
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 117,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 118,0
va (VaSet
)
xt "-9000,17000,-3100,18000"
st "refclk_too_high"
blo "-9000,17800"
tm "WireNameMgr"
)
)
on &21
)
*53 (Wire
uid 121,0
shape (OrthoPolyLine
uid 122,0
va (VaSet
vasetType 3
)
xt "-10000,19000,-750,19000"
pts [
"-10000,19000"
"-750,19000"
]
)
end &9
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 125,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 126,0
va (VaSet
)
xt "-9000,18000,-3500,19000"
st "refclk_too_low"
blo "-9000,18800"
tm "WireNameMgr"
)
)
on &22
)
*54 (Wire
uid 129,0
shape (OrthoPolyLine
uid 130,0
va (VaSet
vasetType 3
)
xt "-10000,20000,-750,20000"
pts [
"-10000,20000"
"-750,20000"
]
)
end &10
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 133,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 134,0
va (VaSet
)
xt "-9000,19000,-3500,20000"
st "socks_waiting"
blo "-9000,19800"
tm "WireNameMgr"
)
)
on &23
)
*55 (Wire
uid 137,0
shape (OrthoPolyLine
uid 138,0
va (VaSet
vasetType 3
)
xt "-10000,21000,-750,21000"
pts [
"-10000,21000"
"-750,21000"
]
)
end &11
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 141,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 142,0
va (VaSet
)
xt "-9000,20000,-2500,21000"
st "socks_connected"
blo "-9000,20800"
tm "WireNameMgr"
)
)
on &24
)
*56 (Wire
uid 153,0
shape (OrthoPolyLine
uid 154,0
va (VaSet
vasetType 3
)
xt "62000,16000,74000,16000"
pts [
"62000,16000"
"74000,16000"
]
)
start &25
sat 1
eat 16
st 0
sf 1
si 0
tg (WTG
uid 159,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 160,0
va (VaSet
)
xt "63000,15000,64500,16000"
st "red"
blo "63000,15800"
tm "WireNameMgr"
)
)
on &17
)
*57 (Wire
uid 161,0
shape (OrthoPolyLine
uid 162,0
va (VaSet
vasetType 3
)
xt "62000,14000,74000,14000"
pts [
"62000,14000"
"74000,14000"
]
)
start &25
sat 1
eat 16
st 0
sf 1
si 0
tg (WTG
uid 167,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 168,0
va (VaSet
)
xt "63000,13000,65400,14000"
st "green"
blo "63000,13800"
tm "WireNameMgr"
)
)
on &15
)
*58 (Wire
uid 169,0
shape (OrthoPolyLine
uid 170,0
va (VaSet
vasetType 3
)
xt "34000,15000,44000,15000"
pts [
"34000,15000"
"44000,15000"
]
)
end &25
sat 16
eat 2
st 0
sf 1
si 0
tg (WTG
uid 175,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 176,0
va (VaSet
)
xt "35000,14000,37800,15000"
st "trigger"
blo "35000,14800"
tm "WireNameMgr"
)
)
on &20
)
*59 (Wire
uid 177,0
shape (OrthoPolyLine
uid 178,0
va (VaSet
vasetType 3
)
xt "62000,17000,74000,17000"
pts [
"62000,17000"
"74000,17000"
]
)
start &25
sat 1
eat 16
st 0
sf 1
si 0
tg (WTG
uid 183,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 184,0
va (VaSet
)
xt "63000,16000,71500,17000"
st "additional_flasher_out"
blo "63000,16800"
tm "WireNameMgr"
)
)
on &18
)
*60 (Wire
uid 185,0
shape (OrthoPolyLine
uid 186,0
va (VaSet
vasetType 3
)
xt "34000,18000,44000,18000"
pts [
"34000,18000"
"44000,18000"
]
)
end &25
sat 16
eat 2
st 0
sf 1
si 0
tg (WTG
uid 191,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 192,0
va (VaSet
)
xt "35000,17000,40500,18000"
st "socks_waiting"
blo "35000,17800"
tm "WireNameMgr"
)
)
on &23
)
*61 (Wire
uid 193,0
shape (OrthoPolyLine
uid 194,0
va (VaSet
vasetType 3
)
xt "34000,16000,44000,16000"
pts [
"34000,16000"
"44000,16000"
]
)
end &25
sat 16
eat 2
st 0
sf 1
si 0
tg (WTG
uid 199,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 200,0
va (VaSet
)
xt "35000,15000,40900,16000"
st "refclk_too_high"
blo "35000,15800"
tm "WireNameMgr"
)
)
on &21
)
*62 (Wire
uid 201,0
shape (OrthoPolyLine
uid 202,0
va (VaSet
vasetType 3
)
xt "34000,17000,44000,17000"
pts [
"34000,17000"
"44000,17000"
]
)
end &25
sat 16
eat 2
st 0
sf 1
si 0
tg (WTG
uid 207,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 208,0
va (VaSet
)
xt "35000,16000,40500,17000"
st "refclk_too_low"
blo "35000,16800"
tm "WireNameMgr"
)
)
on &22
)
*63 (Wire
uid 217,0
shape (OrthoPolyLine
uid 218,0
va (VaSet
vasetType 3
)
xt "62000,15000,74000,15000"
pts [
"62000,15000"
"74000,15000"
]
)
start &25
sat 1
eat 16
st 0
sf 1
si 0
tg (WTG
uid 223,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 224,0
va (VaSet
)
xt "63000,14000,65500,15000"
st "amber"
blo "63000,14800"
tm "WireNameMgr"
)
)
on &16
)
*64 (Wire
uid 225,0
shape (OrthoPolyLine
uid 226,0
va (VaSet
vasetType 3
)
xt "34000,19000,44000,19000"
pts [
"34000,19000"
"44000,19000"
]
)
end &25
sat 16
eat 2
st 0
sf 1
si 0
tg (WTG
uid 231,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 232,0
va (VaSet
)
xt "35000,18000,41500,19000"
st "socks_connected"
blo "35000,18800"
tm "WireNameMgr"
)
)
on &24
)
*65 (Wire
uid 434,0
shape (OrthoPolyLine
uid 435,0
va (VaSet
vasetType 3
)
xt "7750,32000,12000,32000"
pts [
"7750,32000"
"12000,32000"
]
)
start &41
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 438,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 439,0
va (VaSet
)
xt "9000,31000,10900,32000"
st "CLK"
blo "9000,31800"
tm "WireNameMgr"
)
)
on &19
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 1
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *66 (PackageList
uid 285,0
stg "VerticalLayoutStrategy"
textVec [
*67 (Text
uid 286,0
va (VaSet
font "arial,8,1"
)
xt "0,0,5400,1000"
st "Package List"
blo "0,800"
)
*68 (MLText
uid 287,0
va (VaSet
)
xt "0,1000,15300,7000"
st "LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.STD_LOGIC_UNSIGNED.ALL;
LIBRARY FACT_FAD_lib;
USE FACT_FAD_lib.fad_definitions.ALL;"
tm "PackageList"
)
]
)
compDirBlock (MlTextGroup
uid 288,0
stg "VerticalLayoutStrategy"
textVec [
*69 (Text
uid 289,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,0,28100,1000"
st "Compiler Directives"
blo "20000,800"
)
*70 (Text
uid 290,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,1000,29600,2000"
st "Pre-module directives:"
blo "20000,1800"
)
*71 (MLText
uid 291,0
va (VaSet
isHidden 1
)
xt "20000,2000,27500,4000"
st "`resetall
`timescale 1ns/10ps"
tm "BdCompilerDirectivesTextMgr"
)
*72 (Text
uid 292,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,4000,30100,5000"
st "Post-module directives:"
blo "20000,4800"
)
*73 (MLText
uid 293,0
va (VaSet
isHidden 1
)
xt "20000,0,20000,0"
tm "BdCompilerDirectivesTextMgr"
)
*74 (Text
uid 294,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,5000,29900,6000"
st "End-module directives:"
blo "20000,5800"
)
*75 (MLText
uid 295,0
va (VaSet
isHidden 1
)
xt "20000,6000,20000,6000"
tm "BdCompilerDirectivesTextMgr"
)
]
associable 1
)
windowSize "0,0,1016,690"
viewArea "-7610,-500,64120,49000"
cachedDiagramExtent "-10400,0,74400,51000"
hasePageBreakOrigin 1
pageBreakOrigin "-11000,0"
lastUid 439,0
defaultCommentText (CommentText
shape (Rectangle
layer 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
lineColor "0,0,32768"
)
xt "0,0,15000,5000"
)
text (MLText
va (VaSet
fg "0,0,32768"
)
xt "200,200,2000,1200"
st "
Text
"
tm "CommentText"
wrapOption 3
visibleHeight 4600
visibleWidth 14600
)
)
defaultPanel (Panel
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "32768,0,0"
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (Text
va (VaSet
font "Arial,8,1"
)
xt "1000,1000,3800,2000"
st "Panel0"
blo "1000,1800"
tm "PanelText"
)
)
)
defaultBlk (Blk
shape (Rectangle
va (VaSet
vasetType 1
fg "39936,56832,65280"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*76 (Text
va (VaSet
font "Arial,8,1"
)
xt "2200,3500,5800,4500"
st "<library>"
blo "2200,4300"
tm "BdLibraryNameMgr"
)
*77 (Text
va (VaSet
font "Arial,8,1"
)
xt "2200,4500,5600,5500"
st "<block>"
blo "2200,5300"
tm "BlkNameMgr"
)
*78 (Text
va (VaSet
font "Arial,8,1"
)
xt "2200,5500,4000,6500"
st "U_0"
blo "2200,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "2200,13500,2200,13500"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
)
defaultMWComponent (MWC
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
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va (VaSet
font "Arial,8,1"
)
xt "550,3500,3450,4500"
st "Library"
blo "550,4300"
)
*80 (Text
va (VaSet
font "Arial,8,1"
)
xt "550,4500,7450,5500"
st "MWComponent"
blo "550,5300"
)
*81 (Text
va (VaSet
font "Arial,8,1"
)
xt "550,5500,2350,6500"
st "U_0"
blo "550,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-6450,1500,-6450,1500"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
visOptions (mwParamsVisibilityOptions
)
)
defaultSaComponent (SaComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*82 (Text
va (VaSet
font "Arial,8,1"
)
xt "900,3500,3800,4500"
st "Library"
blo "900,4300"
tm "BdLibraryNameMgr"
)
*83 (Text
va (VaSet
font "Arial,8,1"
)
xt "900,4500,7100,5500"
st "SaComponent"
blo "900,5300"
tm "CptNameMgr"
)
*84 (Text
va (VaSet
font "Arial,8,1"
)
xt "900,5500,2700,6500"
st "U_0"
blo "900,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-6100,1500,-6100,1500"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
defaultVhdlComponent (VhdlComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*85 (Text
va (VaSet
font "Arial,8,1"
)
xt "500,3500,3400,4500"
st "Library"
blo "500,4300"
)
*86 (Text
va (VaSet
font "Arial,8,1"
)
xt "500,4500,7500,5500"
st "VhdlComponent"
blo "500,5300"
)
*87 (Text
va (VaSet
font "Arial,8,1"
)
xt "500,5500,2300,6500"
st "U_0"
blo "500,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-6500,1500,-6500,1500"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
)
entityPath ""
archName ""
archPath ""
)
defaultVerilogComponent (VerilogComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-450,0,8450,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*88 (Text
va (VaSet
font "Arial,8,1"
)
xt "50,3500,2950,4500"
st "Library"
blo "50,4300"
)
*89 (Text
va (VaSet
font "Arial,8,1"
)
xt "50,4500,7950,5500"
st "VerilogComponent"
blo "50,5300"
)
*90 (Text
va (VaSet
font "Arial,8,1"
)
xt "50,5500,1850,6500"
st "U_0"
blo "50,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-6950,1500,-6950,1500"
)
header ""
)
elements [
]
)
entityPath ""
)
defaultHdlText (HdlText
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,37120"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*91 (Text
va (VaSet
font "Arial,8,1"
)
xt "3150,4000,4850,5000"
st "eb1"
blo "3150,4800"
tm "HdlTextNameMgr"
)
*92 (Text
va (VaSet
font "Arial,8,1"
)
xt "3150,5000,3950,6000"
st "1"
blo "3150,5800"
tm "HdlTextNumberMgr"
)
]
)
viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
)
defaultEmbeddedText (EmbeddedText
commentText (CommentText
ps "CenterOffsetStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,18000,5000"
)
text (MLText
va (VaSet
)
xt "200,200,2000,1200"
st "
Text
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 4600
visibleWidth 17600
)
)
)
defaultGlobalConnector (GlobalConnector
shape (Circle
va (VaSet
vasetType 1
fg "65535,65535,0"
)
xt "-1000,-1000,1000,1000"
radius 1000
)
name (Text
va (VaSet
font "Arial,8,1"
)
xt "-500,-500,500,500"
st "G"
blo "-500,300"
)
)
defaultRipper (Ripper
ps "OnConnectorStrategy"
shape (Line2D
pts [
"0,0"
"1000,1000"
]
va (VaSet
vasetType 1
)
xt "0,0,1000,1000"
)
)
defaultBdJunction (BdJunction
ps "OnConnectorStrategy"
shape (Circle
va (VaSet
vasetType 1
)
xt "-400,-400,400,400"
radius 400
)
)
defaultPortIoIn (PortIoIn
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "-2000,-375,-500,375"
)
(Line
sl 0
ro 270
xt "-500,0,0,0"
pts [
"-500,0"
"0,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "-1375,-1000,-1375,-1000"
ju 2
blo "-1375,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoOut (PortIoOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "500,-375,2000,375"
)
(Line
sl 0
ro 270
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "625,-1000,625,-1000"
blo "625,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoInOut (PortIoInOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultPortIoBuffer (PortIoBuffer
shape (CompositeShape
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultSignal (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,0,1900,1000"
st "sig0"
blo "0,800"
tm "WireNameMgr"
)
)
)
defaultBus (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineWidth 2
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,0,2400,1000"
st "dbus0"
blo "0,800"
tm "WireNameMgr"
)
)
)
defaultBundle (Bundle
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineColor "32768,0,0"
lineWidth 2
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
textGroup (BiTextGroup
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
first (Text
va (VaSet
)
xt "0,0,3000,1000"
st "bundle0"
blo "0,800"
tm "BundleNameMgr"
)
second (MLText
va (VaSet
)
xt "0,1000,1000,2000"
st "()"
tm "BundleContentsMgr"
)
)
bundleNet &0
)
defaultPortMapFrame (PortMapFrame
ps "PortMapFrameStrategy"
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,10000,12000"
)
portMapText (BiTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
first (MLText
va (VaSet
)
)
second (MLText
va (VaSet
)
tm "PortMapTextMgr"
)
)
)
defaultGenFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "26368,26368,26368"
lineStyle 2
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1100,12600,-100"
st "g0: FOR i IN 0 TO n GENERATE"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1250,1450"
)
num (Text
va (VaSet
)
xt "250,250,1050,1250"
st "1"
blo "250,1050"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*93 (Text
va (VaSet
font "Arial,8,1"
)
xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*94 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
)
]
)
)
defaultBlockFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "26368,26368,26368"
lineStyle 1
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1100,7400,-100"
st "b0: BLOCK (guard)"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1250,1450"
)
num (Text
va (VaSet
)
xt "250,250,1050,1250"
st "1"
blo "250,1050"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*95 (Text
va (VaSet
font "Arial,8,1"
)
xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*96 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
)
]
)
style 3
)
defaultSaCptPort (CptPort
ps "OnEdgeStrategy"
shape (Triangle
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1800,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultSaCptPortBuffer (CptPort
ps "OnEdgeStrategy"
shape (Diamond
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1800,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
m 3
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultDeclText (MLText
va (VaSet
font "Courier New,8,0"
)
)
archDeclarativeBlock (BdArchDeclBlock
uid 1,0
stg "BdArchDeclBlockLS"
declLabel (Text
uid 2,0
va (VaSet
font "Arial,8,1"
)
xt "20000,0,25400,1000"
st "Declarations"
blo "20000,800"
)
portLabel (Text
uid 3,0
va (VaSet
font "Arial,8,1"
)
xt "20000,1000,22700,2000"
st "Ports:"
blo "20000,1800"
)
preUserLabel (Text
uid 4,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,0,23800,1000"
st "Pre User:"
blo "20000,800"
)
preUserText (MLText
uid 5,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "20000,0,20000,0"
tm "BdDeclarativeTextMgr"
)
diagSignalLabel (Text
uid 6,0
va (VaSet
font "Arial,8,1"
)
xt "20000,2000,27100,3000"
st "Diagram Signals:"
blo "20000,2800"
)
postUserLabel (Text
uid 7,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,0,24700,1000"
st "Post User:"
blo "20000,800"
)
postUserText (MLText
uid 8,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "20000,0,20000,0"
tm "BdDeclarativeTextMgr"
)
)
commonDM (CommonDM
ldm (LogicalDM
suid 10,0
usingSuid 1
emptyRow *97 (LEmptyRow
)
uid 298,0
optionalChildren [
*98 (RefLabelRowHdr
)
*99 (TitleRowHdr
)
*100 (FilterRowHdr
)
*101 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*102 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*103 (GroupColHdr
tm "GroupColHdrMgr"
)
*104 (NameColHdr
tm "BlockDiagramNameColHdrMgr"
)
*105 (ModeColHdr
tm "BlockDiagramModeColHdrMgr"
)
*106 (TypeColHdr
tm "BlockDiagramTypeColHdrMgr"
)
*107 (BoundsColHdr
tm "BlockDiagramBoundsColHdrMgr"
)
*108 (InitColHdr
tm "BlockDiagramInitColHdrMgr"
)
*109 (EolColHdr
tm "BlockDiagramEolColHdrMgr"
)
*110 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "green"
t "std_logic"
o 1
suid 1,0
)
)
uid 265,0
)
*111 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "amber"
t "std_logic"
o 2
suid 2,0
)
)
uid 267,0
)
*112 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "red"
t "std_logic"
o 3
suid 3,0
)
)
uid 269,0
)
*113 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "additional_flasher_out"
t "std_logic"
o 4
suid 4,0
)
)
uid 271,0
)
*114 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "CLK"
t "std_logic"
o 5
suid 5,0
)
)
uid 273,0
)
*115 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "trigger"
t "std_logic"
o 6
suid 6,0
)
)
uid 275,0
)
*116 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "refclk_too_high"
t "std_logic"
o 7
suid 7,0
)
)
uid 277,0
)
*117 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "refclk_too_low"
t "std_logic"
o 8
suid 8,0
)
)
uid 279,0
)
*118 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "socks_waiting"
t "std_logic"
o 9
suid 9,0
)
)
uid 281,0
)
*119 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "socks_connected"
t "std_logic"
o 10
suid 10,0
)
)
uid 283,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 311,0
optionalChildren [
*120 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *121 (MRCItem
litem &97
pos 10
dimension 20
)
uid 313,0
optionalChildren [
*122 (MRCItem
litem &98
pos 0
dimension 20
uid 314,0
)
*123 (MRCItem
litem &99
pos 1
dimension 23
uid 315,0
)
*124 (MRCItem
litem &100
pos 2
hidden 1
dimension 20
uid 316,0
)
*125 (MRCItem
litem &110
pos 0
dimension 20
uid 266,0
)
*126 (MRCItem
litem &111
pos 1
dimension 20
uid 268,0
)
*127 (MRCItem
litem &112
pos 2
dimension 20
uid 270,0
)
*128 (MRCItem
litem &113
pos 3
dimension 20
uid 272,0
)
*129 (MRCItem
litem &114
pos 4
dimension 20
uid 274,0
)
*130 (MRCItem
litem &115
pos 5
dimension 20
uid 276,0
)
*131 (MRCItem
litem &116
pos 6
dimension 20
uid 278,0
)
*132 (MRCItem
litem &117
pos 7
dimension 20
uid 280,0
)
*133 (MRCItem
litem &118
pos 8
dimension 20
uid 282,0
)
*134 (MRCItem
litem &119
pos 9
dimension 20
uid 284,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 317,0
optionalChildren [
*135 (MRCItem
litem &101
pos 0
dimension 20
uid 318,0
)
*136 (MRCItem
litem &103
pos 1
dimension 50
uid 319,0
)
*137 (MRCItem
litem &104
pos 2
dimension 100
uid 320,0
)
*138 (MRCItem
litem &105
pos 3
dimension 50
uid 321,0
)
*139 (MRCItem
litem &106
pos 4
dimension 100
uid 322,0
)
*140 (MRCItem
litem &107
pos 5
dimension 100
uid 323,0
)
*141 (MRCItem
litem &108
pos 6
dimension 50
uid 324,0
)
*142 (MRCItem
litem &109
pos 7
dimension 80
uid 325,0
)
]
)
fixedCol 4
fixedRow 2
name "Ports"
uid 312,0
vaOverrides [
]
)
]
)
uid 297,0
)
genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *143 (LEmptyRow
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uid 327,0
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