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"GroupColHdrMgr" ) *52 (NameColHdr tm "GenericNameColHdrMgr" ) *53 (TypeColHdr tm "GenericTypeColHdrMgr" ) *54 (InitColHdr tm "GenericValueColHdrMgr" ) *55 (PragmaColHdr tm "GenericPragmaColHdrMgr" ) *56 (EolColHdr tm "GenericEolColHdrMgr" ) ] ) pdm (PhysicalDM displayShortBounds 1 editShortBounds 1 uid 164,0 optionalChildren [ *57 (Sheet sheetRow (SheetRow headerVa (MVa cellColor "49152,49152,49152" fontColor "0,0,0" font "Tahoma,10,0" ) cellVa (MVa cellColor "65535,65535,65535" fontColor "0,0,0" font "Tahoma,10,0" ) groupVa (MVa cellColor "39936,56832,65280" fontColor "0,0,0" font "Tahoma,10,0" ) emptyMRCItem *58 (MRCItem litem &45 pos 3 dimension 20 ) uid 166,0 optionalChildren [ *59 (MRCItem litem &46 pos 0 dimension 20 uid 167,0 ) *60 (MRCItem litem &47 pos 1 dimension 23 uid 168,0 ) *61 (MRCItem litem &48 pos 2 hidden 1 dimension 20 uid 169,0 ) ] ) sheetCol (SheetCol propVa (MVa cellColor "0,49152,49152" fontColor "0,0,0" font "Tahoma,10,0" textAngle 90 ) uid 170,0 optionalChildren [ *62 (MRCItem litem &49 pos 0 dimension 20 uid 171,0 ) *63 (MRCItem litem &51 pos 1 dimension 50 uid 172,0 ) *64 (MRCItem litem &52 pos 2 dimension 100 uid 173,0 ) *65 (MRCItem litem &53 pos 3 dimension 100 uid 174,0 ) *66 (MRCItem litem &54 pos 4 dimension 50 uid 175,0 ) *67 (MRCItem litem &55 pos 5 dimension 50 uid 176,0 ) *68 (MRCItem litem &56 pos 6 dimension 80 uid 177,0 ) ] ) fixedCol 3 fixedRow 2 name "Ports" uid 165,0 vaOverrides [ ] ) ] ) uid 151,0 type 1 ) VExpander (VariableExpander vvMap [ (vvPair variable "HDLDir" value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hdl" ) (vvPair variable "HDSDir" value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds" ) (vvPair variable "SideDataDesignDir" value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\led_controller_tester\\interface.info" ) (vvPair variable "SideDataUserDir" value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\led_controller_tester\\interface.user" ) (vvPair variable "SourceDir" value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds" ) (vvPair variable "appl" value "HDL Designer" ) (vvPair variable "arch_name" value "interface" ) (vvPair variable "config" value "%(unit)_%(view)_config" ) (vvPair variable "d" value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\led_controller_tester" ) (vvPair variable "d_logical" value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\led_controller_tester" ) (vvPair variable "date" value "02.03.2011" ) (vvPair variable "day" value "Mi" ) (vvPair variable "day_long" value "Mittwoch" ) (vvPair variable "dd" value "02" ) (vvPair variable "entity_name" value "led_controller_tester" ) (vvPair variable "ext" value "" ) (vvPair variable "f" value "interface" ) (vvPair variable "f_logical" value "interface" ) (vvPair variable "f_noext" value "interface" ) (vvPair variable "group" value "UNKNOWN" ) (vvPair variable "host" value "IHP110" ) (vvPair variable "language" value "VHDL" ) (vvPair variable "library" value "FACT_FAD_TB_lib" ) (vvPair variable "library_downstream_HdsLintPlugin" value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/designcheck" ) (vvPair variable "library_downstream_ISEPARInvoke" value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise" ) (vvPair variable "library_downstream_ImpactInvoke" value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise" ) (vvPair variable "library_downstream_ModelSimCompiler" value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/work" ) (vvPair variable "library_downstream_XSTDataPrep" value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise" ) (vvPair variable "mm" value "03" ) (vvPair variable "module_name" value "led_controller_tester" ) (vvPair variable "month" value "Mrz" ) (vvPair variable "month_long" value "März" ) (vvPair variable "p" value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\led_controller_tester\\interface" ) (vvPair variable "p_logical" value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\led_controller_tester\\interface" ) (vvPair variable "package_name" value "" ) (vvPair variable "project_name" value "FACT_FAD" ) (vvPair variable "series" value "HDL Designer Series" ) (vvPair variable "task_DesignCompilerPath" value "" ) (vvPair variable "task_LeonardoPath" value "" ) (vvPair variable "task_ModelSimPath" value "D:\\modeltech_6.5e\\win32" ) (vvPair variable "task_NC-SimPath" value "" ) (vvPair variable "task_PrecisionRTLPath" value "" ) (vvPair variable "task_QuestaSimPath" value "" ) (vvPair variable "task_VCSPath" value "" ) (vvPair variable "this_ext" value "" ) (vvPair variable "this_file" value "interface" ) (vvPair variable "this_file_logical" value "interface" ) (vvPair variable "time" value "09:51:45" ) (vvPair variable "unit" value "led_controller_tester" ) (vvPair variable "user" value "daqct3" ) (vvPair variable "version" value "2009.1 (Build 12)" ) (vvPair variable "view" value "interface" ) (vvPair variable "year" value "2011" ) (vvPair variable "yy" value "11" ) ] ) LanguageMgr "VhdlLangMgr" uid 121,0 optionalChildren [ *69 (SymbolBody uid 8,0 optionalChildren [ *70 (CptPort uid 201,0 ps "OnEdgeStrategy" shape (Triangle uid 202,0 ro 270 va (VaSet vasetType 1 fg "0,65535,0" ) xt "33000,9625,33750,10375" ) tg (CPTG uid 203,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 204,0 va (VaSet ) xt "23500,9500,32000,10500" st "additional_flasher_out" ju 2 blo "32000,10300" tm "CptPortNameMgr" ) ) dt (MLText uid 205,0 va (VaSet font "Courier New,8,0" ) ) thePort (LogicalPort decl (Decl n "additional_flasher_out" t "std_logic" o 1 suid 11,0 ) ) ) *71 (CptPort uid 206,0 ps "OnEdgeStrategy" shape (Triangle uid 207,0 ro 270 va (VaSet vasetType 1 fg "0,65535,0" ) xt "33000,7625,33750,8375" ) tg (CPTG uid 208,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 209,0 va (VaSet ) xt "29500,7500,32000,8500" st "amber" ju 2 blo "32000,8300" tm "CptPortNameMgr" ) ) dt (MLText uid 210,0 va (VaSet font "Courier New,8,0" ) ) thePort (LogicalPort decl (Decl n "amber" t "std_logic" o 2 suid 12,0 ) ) ) *72 (CptPort uid 211,0 ps "OnEdgeStrategy" shape (Triangle uid 212,0 ro 270 va (VaSet vasetType 1 fg "0,65535,0" ) xt "33000,6625,33750,7375" ) tg (CPTG uid 213,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 214,0 va (VaSet ) xt "29600,6500,32000,7500" st "green" ju 2 blo "32000,7300" tm "CptPortNameMgr" ) ) dt (MLText uid 215,0 va (VaSet font "Courier New,8,0" ) ) thePort (LogicalPort decl (Decl n "green" t "std_logic" o 3 suid 13,0 ) ) ) *73 (CptPort uid 216,0 ps "OnEdgeStrategy" shape (Triangle uid 217,0 ro 270 va (VaSet vasetType 1 fg "0,65535,0" ) xt "33000,8625,33750,9375" ) tg (CPTG uid 218,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 219,0 va (VaSet ) xt "30500,8500,32000,9500" st "red" ju 2 blo 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