source: firmware/FAD/FACT_FAD_TB_lib/hds/phase_shifter_tb/struct.bd.bak@ 20115

Last change on this file since 20115 was 11755, checked in by neise, 13 years ago
reinit of this svn repos .... it was all too messy deleted the old folders and restarted with FACT_FAD_lib only. (well and the testbenches)
File size: 55.7 KB
Line 
1DocumentHdrVersion "1.1"
2Header (DocumentHdr
3version 2
4dmPackageRefs [
5(DmPackageRef
6library "ieee"
7unitName "std_logic_1164"
8itemName "ALL"
9)
10(DmPackageRef
11library "IEEE"
12unitName "NUMERIC_STD"
13itemName "ALL"
14)
15(DmPackageRef
16library "FACT_FAD_lib"
17unitName "fad_definitions"
18itemName "ALL"
19)
20(DmPackageRef
21library "ieee"
22unitName "std_logic_unsigned"
23)
24(DmPackageRef
25library "ieee"
26unitName "std_logic_arith"
27)
28]
29instances [
30(Instance
31name "U_0"
32duLibraryName "FACT_FAD_lib"
33duName "phase_shifter"
34elements [
35]
36mwi 0
37uid 64,0
38)
39(Instance
40name "U_1"
41duLibraryName "FACT_FAD_TB_lib"
42duName "phase_shifter_tester"
43elements [
44]
45mwi 0
46uid 190,0
47)
48(Instance
49name "U_2"
50duLibraryName "FACT_FAD_TB_lib"
51duName "clock_generator"
52elements [
53(GiElement
54name "clock_period"
55type "time"
56value "20 ns"
57)
58(GiElement
59name "reset_time"
60type "time"
61value "50 ns"
62)
63]
64mwi 0
65uid 525,0
66)
67]
68libraryRefs [
69"ieee"
70"FACT_FAD_lib"
71]
72)
73version "29.1"
74appVersion "2009.2 (Build 10)"
75noEmbeddedEditors 1
76model (BlockDiag
77VExpander (VariableExpander
78vvMap [
79(vvPair
80variable "HDLDir"
81value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hdl"
82)
83(vvPair
84variable "HDSDir"
85value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
86)
87(vvPair
88variable "SideDataDesignDir"
89value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\phase_shifter_tb\\struct.bd.info"
90)
91(vvPair
92variable "SideDataUserDir"
93value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\phase_shifter_tb\\struct.bd.user"
94)
95(vvPair
96variable "SourceDir"
97value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
98)
99(vvPair
100variable "appl"
101value "HDL Designer"
102)
103(vvPair
104variable "arch_name"
105value "struct"
106)
107(vvPair
108variable "config"
109value "%(unit)_%(view)_config"
110)
111(vvPair
112variable "d"
113value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\phase_shifter_tb"
114)
115(vvPair
116variable "d_logical"
117value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\phase_shifter_tb"
118)
119(vvPair
120variable "date"
121value "14.02.2011"
122)
123(vvPair
124variable "day"
125value "Mo"
126)
127(vvPair
128variable "day_long"
129value "Montag"
130)
131(vvPair
132variable "dd"
133value "14"
134)
135(vvPair
136variable "entity_name"
137value "phase_shifter_tb"
138)
139(vvPair
140variable "ext"
141value "<TBD>"
142)
143(vvPair
144variable "f"
145value "struct.bd"
146)
147(vvPair
148variable "f_logical"
149value "struct.bd"
150)
151(vvPair
152variable "f_noext"
153value "struct"
154)
155(vvPair
156variable "group"
157value "UNKNOWN"
158)
159(vvPair
160variable "host"
161value "E5B-LABOR6"
162)
163(vvPair
164variable "language"
165value "VHDL"
166)
167(vvPair
168variable "library"
169value "FACT_FAD_TB_lib"
170)
171(vvPair
172variable "library_downstream_ISEPARInvoke"
173value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
174)
175(vvPair
176variable "library_downstream_ImpactInvoke"
177value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
178)
179(vvPair
180variable "library_downstream_ModelSimCompiler"
181value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/work"
182)
183(vvPair
184variable "library_downstream_XSTDataPrep"
185value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
186)
187(vvPair
188variable "mm"
189value "02"
190)
191(vvPair
192variable "module_name"
193value "phase_shifter_tb"
194)
195(vvPair
196variable "month"
197value "Feb"
198)
199(vvPair
200variable "month_long"
201value "Februar"
202)
203(vvPair
204variable "p"
205value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\phase_shifter_tb\\struct.bd"
206)
207(vvPair
208variable "p_logical"
209value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\phase_shifter_tb\\struct.bd"
210)
211(vvPair
212variable "package_name"
213value "<Undefined Variable>"
214)
215(vvPair
216variable "project_name"
217value "FACT_FAD"
218)
219(vvPair
220variable "series"
221value "HDL Designer Series"
222)
223(vvPair
224variable "task_DesignCompilerPath"
225value "<TBD>"
226)
227(vvPair
228variable "task_LeonardoPath"
229value "<TBD>"
230)
231(vvPair
232variable "task_ModelSimPath"
233value "C:\\modeltech_6.6a\\win32"
234)
235(vvPair
236variable "task_NC-SimPath"
237value "<TBD>"
238)
239(vvPair
240variable "task_PrecisionRTLPath"
241value "<TBD>"
242)
243(vvPair
244variable "task_QuestaSimPath"
245value "<TBD>"
246)
247(vvPair
248variable "task_VCSPath"
249value "<TBD>"
250)
251(vvPair
252variable "this_ext"
253value "bd"
254)
255(vvPair
256variable "this_file"
257value "struct"
258)
259(vvPair
260variable "this_file_logical"
261value "struct"
262)
263(vvPair
264variable "time"
265value "13:16:32"
266)
267(vvPair
268variable "unit"
269value "phase_shifter_tb"
270)
271(vvPair
272variable "user"
273value "dneise"
274)
275(vvPair
276variable "version"
277value "2009.2 (Build 10)"
278)
279(vvPair
280variable "view"
281value "struct"
282)
283(vvPair
284variable "year"
285value "2011"
286)
287(vvPair
288variable "yy"
289value "11"
290)
291]
292)
293LanguageMgr "VhdlLangMgr"
294uid 379,0
295optionalChildren [
296*1 (SaComponent
297uid 64,0
298optionalChildren [
299*2 (CptPort
300uid 9,0
301ps "OnEdgeStrategy"
302shape (Triangle
303uid 10,0
304ro 90
305va (VaSet
306vasetType 1
307fg "0,65535,0"
308)
309xt "10250,8625,11000,9375"
310)
311tg (CPTG
312uid 11,0
313ps "CptPortTextPlaceStrategy"
314stg "VerticalLayoutStrategy"
315f (Text
316uid 12,0
317va (VaSet
318)
319xt "12000,8500,13900,9500"
320st "CLK"
321blo "12000,9300"
322)
323)
324thePort (LogicalPort
325decl (Decl
326n "CLK"
327t "std_logic"
328preAdd 0
329posAdd 0
330o 1
331suid 1,0
332)
333)
334)
335*3 (CptPort
336uid 13,0
337ps "OnEdgeStrategy"
338shape (Triangle
339uid 14,0
340ro 90
341va (VaSet
342vasetType 1
343fg "0,65535,0"
344)
345xt "26000,8625,26750,9375"
346)
347tg (CPTG
348uid 15,0
349ps "CptPortTextPlaceStrategy"
350stg "RightVerticalLayoutStrategy"
351f (Text
352uid 16,0
353va (VaSet
354)
355xt "22100,8500,25000,9500"
356st "PSCLK"
357ju 2
358blo "25000,9300"
359)
360)
361thePort (LogicalPort
362m 1
363decl (Decl
364n "PSCLK"
365t "std_logic"
366prec "-- interface to: clock_generator_variable_PS_struct.vhd"
367preAdd 0
368posAdd 0
369o 3
370suid 2,0
371)
372)
373)
374*4 (CptPort
375uid 17,0
376ps "OnEdgeStrategy"
377shape (Triangle
378uid 18,0
379ro 90
380va (VaSet
381vasetType 1
382fg "0,65535,0"
383)
384xt "26000,10625,26750,11375"
385)
386tg (CPTG
387uid 19,0
388ps "CptPortTextPlaceStrategy"
389stg "RightVerticalLayoutStrategy"
390f (Text
391uid 20,0
392va (VaSet
393)
394xt "22500,10500,25000,11500"
395st "PSEN"
396ju 2
397blo "25000,11300"
398)
399t (Text
400uid 74,0
401va (VaSet
402)
403xt "23800,11500,25000,12500"
404st "'0'"
405ju 2
406blo "25000,12300"
407)
408)
409thePort (LogicalPort
410m 1
411decl (Decl
412n "PSEN"
413t "std_logic"
414preAdd 0
415posAdd 0
416o 4
417suid 3,0
418i "'0'"
419)
420)
421)
422*5 (CptPort
423uid 21,0
424ps "OnEdgeStrategy"
425shape (Triangle
426uid 22,0
427ro 90
428va (VaSet
429vasetType 1
430fg "0,65535,0"
431)
432xt "26000,12625,26750,13375"
433)
434tg (CPTG
435uid 23,0
436ps "CptPortTextPlaceStrategy"
437stg "RightVerticalLayoutStrategy"
438f (Text
439uid 24,0
440va (VaSet
441)
442xt "20500,12500,25000,13500"
443st "PSINCDEC"
444ju 2
445blo "25000,13300"
446)
447t (Text
448uid 75,0
449va (VaSet
450)
451xt "23800,13500,25000,14500"
452st "'1'"
453ju 2
454blo "25000,14300"
455)
456)
457thePort (LogicalPort
458m 1
459decl (Decl
460n "PSINCDEC"
461t "std_logic"
462eolc "-- default is 'incrementing'"
463preAdd 0
464posAdd 0
465o 5
466suid 4,0
467i "'1'"
468)
469)
470)
471*6 (CptPort
472uid 25,0
473ps "OnEdgeStrategy"
474shape (Triangle
475uid 26,0
476ro 90
477va (VaSet
478vasetType 1
479fg "0,65535,0"
480)
481xt "10250,10625,11000,11375"
482)
483tg (CPTG
484uid 27,0
485ps "CptPortTextPlaceStrategy"
486stg "VerticalLayoutStrategy"
487f (Text
488uid 28,0
489va (VaSet
490)
491xt "12000,10500,15700,11500"
492st "PSDONE"
493blo "12000,11300"
494)
495)
496thePort (LogicalPort
497decl (Decl
498n "PSDONE"
499t "std_logic"
500eolc "-- will pulse once, if phase shifting was done."
501preAdd 0
502posAdd 0
503o 6
504suid 5,0
505)
506)
507)
508*7 (CptPort
509uid 29,0
510ps "OnEdgeStrategy"
511shape (Triangle
512uid 30,0
513ro 90
514va (VaSet
515vasetType 1
516fg "0,65535,0"
517)
518xt "10250,12625,11000,13375"
519)
520tg (CPTG
521uid 31,0
522ps "CptPortTextPlaceStrategy"
523stg "VerticalLayoutStrategy"
524f (Text
525uid 32,0
526va (VaSet
527)
528xt "12000,12500,15600,13500"
529st "LOCKED"
530blo "12000,13300"
531)
532)
533thePort (LogicalPort
534decl (Decl
535n "LOCKED"
536t "std_logic"
537eolc "-- when is this going high?"
538preAdd 0
539posAdd 0
540o 7
541suid 6,0
542)
543)
544)
545*8 (CptPort
546uid 33,0
547ps "OnEdgeStrategy"
548shape (Triangle
549uid 34,0
550ro 90
551va (VaSet
552vasetType 1
553fg "0,65535,0"
554)
555xt "10250,16625,11000,17375"
556)
557tg (CPTG
558uid 35,0
559ps "CptPortTextPlaceStrategy"
560stg "VerticalLayoutStrategy"
561f (Text
562uid 36,0
563va (VaSet
564)
565xt "12000,16500,16600,17500"
566st "shift_phase"
567blo "12000,17300"
568)
569)
570thePort (LogicalPort
571decl (Decl
572n "shift_phase"
573t "std_logic"
574prec "-- interface to: w5300_modul.vhd"
575preAdd 0
576posAdd 0
577o 8
578suid 8,0
579)
580)
581)
582*9 (CptPort
583uid 37,0
584ps "OnEdgeStrategy"
585shape (Triangle
586uid 38,0
587ro 90
588va (VaSet
589vasetType 1
590fg "0,65535,0"
591)
592xt "10250,18625,11000,19375"
593)
594tg (CPTG
595uid 39,0
596ps "CptPortTextPlaceStrategy"
597stg "VerticalLayoutStrategy"
598f (Text
599uid 40,0
600va (VaSet
601)
602xt "12000,18500,15300,19500"
603st "direction"
604blo "12000,19300"
605)
606)
607thePort (LogicalPort
608decl (Decl
609n "direction"
610t "std_logic"
611eolc "-- corresponds to 'PSINCDEC'"
612preAdd 0
613posAdd 0
614o 9
615suid 9,0
616)
617)
618)
619*10 (CptPort
620uid 41,0
621ps "OnEdgeStrategy"
622shape (Triangle
623uid 42,0
624ro 90
625va (VaSet
626vasetType 1
627fg "0,65535,0"
628)
629xt "26000,14625,26750,15375"
630)
631tg (CPTG
632uid 43,0
633ps "CptPortTextPlaceStrategy"
634stg "RightVerticalLayoutStrategy"
635f (Text
636uid 44,0
637va (VaSet
638)
639xt "22100,14500,25000,15500"
640st "shifting"
641ju 2
642blo "25000,15300"
643)
644t (Text
645uid 76,0
646va (VaSet
647)
648xt "23800,15500,25000,16500"
649st "'0'"
650ju 2
651blo "25000,16300"
652)
653)
654thePort (LogicalPort
655m 1
656decl (Decl
657n "shifting"
658t "std_logic"
659prec "-- status:"
660preAdd 0
661posAdd 0
662o 11
663suid 10,0
664i "'0'"
665)
666)
667)
668*11 (CptPort
669uid 45,0
670ps "OnEdgeStrategy"
671shape (Triangle
672uid 46,0
673ro 90
674va (VaSet
675vasetType 1
676fg "0,65535,0"
677)
678xt "26000,16625,26750,17375"
679)
680tg (CPTG
681uid 47,0
682ps "CptPortTextPlaceStrategy"
683stg "RightVerticalLayoutStrategy"
684f (Text
685uid 48,0
686va (VaSet
687)
688xt "22800,16500,25000,17500"
689st "ready"
690ju 2
691blo "25000,17300"
692)
693t (Text
694uid 77,0
695va (VaSet
696)
697xt "23800,17500,25000,18500"
698st "'0'"
699ju 2
700blo "25000,18300"
701)
702)
703thePort (LogicalPort
704m 1
705decl (Decl
706n "ready"
707t "std_logic"
708preAdd 0
709posAdd 0
710o 12
711suid 11,0
712i "'0'"
713)
714)
715)
716*12 (CptPort
717uid 49,0
718ps "OnEdgeStrategy"
719shape (Triangle
720uid 50,0
721ro 90
722va (VaSet
723vasetType 1
724fg "0,65535,0"
725)
726xt "26000,18625,26750,19375"
727)
728tg (CPTG
729uid 51,0
730ps "CptPortTextPlaceStrategy"
731stg "RightVerticalLayoutStrategy"
732f (Text
733uid 52,0
734va (VaSet
735)
736xt "20200,18500,25000,19500"
737st "offset : (7:0)"
738ju 2
739blo "25000,19300"
740)
741t (Text
742uid 78,0
743va (VaSet
744)
745xt "18100,19500,25000,20500"
746st "(OTHERS => '0')"
747ju 2
748blo "25000,20300"
749)
750)
751thePort (LogicalPort
752m 1
753decl (Decl
754n "offset"
755t "std_logic_vector"
756b "(7 DOWNTO 0)"
757preAdd 0
758posAdd 0
759o 13
760suid 12,0
761i "(OTHERS => '0')"
762)
763)
764)
765*13 (CptPort
766uid 53,0
767ps "OnEdgeStrategy"
768shape (Triangle
769uid 54,0
770ro 270
771va (VaSet
772vasetType 1
773fg "0,65535,0"
774)
775xt "10250,19625,11000,20375"
776)
777tg (CPTG
778uid 55,0
779ps "CptPortTextPlaceStrategy"
780stg "VerticalLayoutStrategy"
781f (Text
782uid 56,0
783va (VaSet
784)
785xt "12000,19500,13300,20500"
786st "rst"
787blo "12000,20300"
788)
789t (Text
790uid 79,0
791va (VaSet
792)
793xt "12000,20500,13200,21500"
794st "'0'"
795blo "12000,21300"
796)
797)
798thePort (LogicalPort
799m 1
800decl (Decl
801n "rst"
802t "std_logic"
803eolc "--asynch in of DCM"
804posAdd 0
805o 2
806suid 15,0
807i "'0'"
808)
809)
810)
811*14 (CptPort
812uid 57,0
813ps "OnEdgeStrategy"
814shape (Triangle
815uid 58,0
816ro 90
817va (VaSet
818vasetType 1
819fg "0,65535,0"
820)
821xt "10250,21625,11000,22375"
822)
823tg (CPTG
824uid 59,0
825ps "CptPortTextPlaceStrategy"
826stg "VerticalLayoutStrategy"
827f (Text
828uid 60,0
829va (VaSet
830)
831xt "12000,21500,16400,22500"
832st "reset_DCM"
833blo "12000,22300"
834)
835)
836thePort (LogicalPort
837decl (Decl
838n "reset_DCM"
839t "std_logic"
840eolc "-- asynch in: orders us, to reset the DCM"
841posAdd 0
842o 10
843suid 17,0
844)
845)
846)
847]
848shape (Rectangle
849uid 65,0
850va (VaSet
851vasetType 1
852fg "0,65535,0"
853lineColor "0,32896,0"
854lineWidth 2
855)
856xt "11000,7000,26000,25000"
857)
858oxt "50000,7000,65000,25000"
859ttg (MlTextGroup
860uid 66,0
861ps "CenterOffsetStrategy"
862stg "VerticalLayoutStrategy"
863textVec [
864*15 (Text
865uid 67,0
866va (VaSet
867font "Arial,8,1"
868)
869xt "15700,15000,21900,16000"
870st "FACT_FAD_lib"
871blo "15700,15800"
872tm "BdLibraryNameMgr"
873)
874*16 (Text
875uid 68,0
876va (VaSet
877font "Arial,8,1"
878)
879xt "15700,16000,21500,17000"
880st "phase_shifter"
881blo "15700,16800"
882tm "CptNameMgr"
883)
884*17 (Text
885uid 69,0
886va (VaSet
887font "Arial,8,1"
888)
889xt "15700,17000,17500,18000"
890st "U_0"
891blo "15700,17800"
892tm "InstanceNameMgr"
893)
894]
895)
896ga (GenericAssociation
897uid 70,0
898ps "EdgeToEdgeStrategy"
899matrix (Matrix
900uid 71,0
901text (MLText
902uid 72,0
903va (VaSet
904font "Courier New,8,0"
905)
906xt "11000,6000,11000,6000"
907)
908header ""
909)
910elements [
911]
912)
913viewicon (ZoomableIcon
914uid 73,0
915sl 0
916va (VaSet
917vasetType 1
918fg "49152,49152,49152"
919)
920xt "11250,23250,12750,24750"
921iconName "VhdlFileViewIcon.png"
922iconMaskName "VhdlFileViewIcon.msk"
923ftype 10
924)
925ordering 1
926viewiconposition 0
927portVis (PortSigDisplay
928sIVOD 1
929)
930archType 1
931archFileType "UNKNOWN"
932)
933*18 (Net
934uid 80,0
935lang 10
936decl (Decl
937n "PSCLK"
938t "std_logic"
939o 1
940suid 1,0
941)
942declText (MLText
943uid 81,0
944va (VaSet
945font "Courier New,8,0"
946)
947xt "13000,-12200,29500,-11400"
948st "SIGNAL PSCLK : std_logic"
949)
950)
951*19 (Net
952uid 88,0
953lang 10
954decl (Decl
955n "PSEN"
956t "std_logic"
957o 2
958suid 2,0
959)
960declText (MLText
961uid 89,0
962va (VaSet
963font "Courier New,8,0"
964)
965xt "13000,-10600,29500,-9800"
966st "SIGNAL PSEN : std_logic"
967)
968)
969*20 (Net
970uid 97,0
971lang 10
972decl (Decl
973n "PSINCDEC"
974t "std_logic"
975o 3
976suid 3,0
977)
978declText (MLText
979uid 98,0
980va (VaSet
981font "Courier New,8,0"
982)
983xt "13000,-9800,29500,-9000"
984st "SIGNAL PSINCDEC : std_logic"
985)
986)
987*21 (Net
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1003)
1004)
1005*22 (Net
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1007lang 10
1008decl (Decl
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1010t "std_logic"
1011o 5
1012suid 5,0
1013)
1014declText (MLText
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1016va (VaSet
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1021)
1022)
1023*23 (Net
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1025lang 10
1026decl (Decl
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1028t "std_logic_vector"
1029b "(7 DOWNTO 0)"
1030o 6
1031suid 6,0
1032)
1033declText (MLText
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1035va (VaSet
1036font "Courier New,8,0"
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1040)
1041)
1042*24 (Net
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1044lang 10
1045decl (Decl
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1047t "std_logic"
1048o 7
1049suid 7,0
1050)
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1053va (VaSet
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1059)
1060*25 (Net
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1062lang 10
1063decl (Decl
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1065t "std_logic"
1066o 8
1067suid 8,0
1068)
1069declText (MLText
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1071va (VaSet
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1076)
1077)
1078*26 (Net
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1080lang 10
1081decl (Decl
1082n "LOCKED"
1083t "std_logic"
1084o 9
1085suid 9,0
1086)
1087declText (MLText
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1089va (VaSet
1090font "Courier New,8,0"
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1093st "SIGNAL LOCKED : std_logic"
1094)
1095)
1096*27 (Net
1097uid 157,0
1098lang 10
1099decl (Decl
1100n "shift_phase"
1101t "std_logic"
1102o 10
1103suid 10,0
1104)
1105declText (MLText
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1107va (VaSet
1108font "Courier New,8,0"
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1111st "SIGNAL shift_phase : std_logic"
1112)
1113)
1114*28 (Net
1115uid 165,0
1116lang 10
1117decl (Decl
1118n "direction"
1119t "std_logic"
1120o 11
1121suid 11,0
1122)
1123declText (MLText
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1125va (VaSet
1126font "Courier New,8,0"
1127)
1128xt "13000,-8200,29500,-7400"
1129st "SIGNAL direction : std_logic"
1130)
1131)
1132*29 (Net
1133uid 173,0
1134lang 10
1135decl (Decl
1136n "rst"
1137t "std_logic"
1138o 12
1139suid 12,0
1140)
1141declText (MLText
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1143va (VaSet
1144font "Courier New,8,0"
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1146xt "13000,-5000,29500,-4200"
1147st "SIGNAL rst : std_logic"
1148)
1149)
1150*30 (Net
1151uid 182,0
1152lang 10
1153decl (Decl
1154n "reset_DCM"
1155t "std_logic"
1156o 13
1157suid 13,0
1158)
1159declText (MLText
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1161va (VaSet
1162font "Courier New,8,0"
1163)
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1167)
1168*31 (Blk
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1170shape (Rectangle
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1173vasetType 1
1174fg "39936,56832,65280"
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1178xt "54000,9000,69000,27000"
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1180oxt "87000,18000,102000,36000"
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1188va (VaSet
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1191xt "57650,16500,65350,17500"
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1193blo "57650,17300"
1194tm "BdLibraryNameMgr"
1195)
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1198va (VaSet
1199font "Arial,8,1"
1200)
1201xt "57650,17500,66350,18500"
1202st "phase_shifter_tester"
1203blo "57650,18300"
1204tm "BlkNameMgr"
1205)
1206*34 (Text
1207uid 195,0
1208va (VaSet
1209font "Arial,8,1"
1210)
1211xt "57650,18500,59450,19500"
1212st "U_1"
1213blo "57650,19300"
1214tm "InstanceNameMgr"
1215)
1216]
1217)
1218ga (GenericAssociation
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1220ps "EdgeToEdgeStrategy"
1221matrix (Matrix
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1223text (MLText
1224uid 198,0
1225va (VaSet
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1228xt "57650,26500,57650,26500"
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1230header ""
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1232elements [
1233]
1234)
1235viewicon (ZoomableIcon
1236uid 199,0
1237sl 0
1238va (VaSet
1239vasetType 1
1240fg "49152,49152,49152"
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1242xt "54250,25250,55750,26750"
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1247ordering 1
1248viewiconposition 0
1249blkPorts [
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1251"PSCLK"
1252"PSEN"
1253"PSINCDEC"
1254"offset"
1255"ready"
1256"rst"
1257"shifting"
1258"LOCKED"
1259"PSDONE"
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1262"shift_phase"
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1272sl 0
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1274vasetType 1
1275fg "65280,65280,46080"
1276)
1277xt "36000,59000,53000,60000"
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1279oxt "18000,70000,35000,71000"
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1282va (VaSet
1283fg "0,0,32768"
1284bg "0,0,32768"
1285)
1286xt "36200,59000,45800,60000"
1287st "
1288by %user on %dd %month %year
1289"
1290tm "CommentText"
1291wrapOption 3
1292visibleHeight 1000
1293visibleWidth 17000
1294)
1295position 1
1296ignorePrefs 1
1297titleBlock 1
1298)
1299*37 (CommentText
1300uid 315,0
1301shape (Rectangle
1302uid 316,0
1303sl 0
1304va (VaSet
1305vasetType 1
1306fg "65280,65280,46080"
1307)
1308xt "53000,55000,57000,56000"
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1310oxt "35000,66000,39000,67000"
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1313va (VaSet
1314fg "0,0,32768"
1315bg "0,0,32768"
1316)
1317xt "53200,55000,56200,56000"
1318st "
1319Project:
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1321tm "CommentText"
1322wrapOption 3
1323visibleHeight 1000
1324visibleWidth 4000
1325)
1326position 1
1327ignorePrefs 1
1328titleBlock 1
1329)
1330*38 (CommentText
1331uid 318,0
1332shape (Rectangle
1333uid 319,0
1334sl 0
1335va (VaSet
1336vasetType 1
1337fg "65280,65280,46080"
1338)
1339xt "36000,57000,53000,58000"
1340)
1341oxt "18000,68000,35000,69000"
1342text (MLText
1343uid 320,0
1344va (VaSet
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1346bg "0,0,32768"
1347)
1348xt "36200,57000,46200,58000"
1349st "
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1352tm "CommentText"
1353wrapOption 3
1354visibleHeight 1000
1355visibleWidth 17000
1356)
1357position 1
1358ignorePrefs 1
1359titleBlock 1
1360)
1361*39 (CommentText
1362uid 321,0
1363shape (Rectangle
1364uid 322,0
1365sl 0
1366va (VaSet
1367vasetType 1
1368fg "65280,65280,46080"
1369)
1370xt "32000,57000,36000,58000"
1371)
1372oxt "14000,68000,18000,69000"
1373text (MLText
1374uid 323,0
1375va (VaSet
1376fg "0,0,32768"
1377bg "0,0,32768"
1378)
1379xt "32200,57000,34300,58000"
1380st "
1381Title:
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1383tm "CommentText"
1384wrapOption 3
1385visibleHeight 1000
1386visibleWidth 4000
1387)
1388position 1
1389ignorePrefs 1
1390titleBlock 1
1391)
1392*40 (CommentText
1393uid 324,0
1394shape (Rectangle
1395uid 325,0
1396sl 0
1397va (VaSet
1398vasetType 1
1399fg "65280,65280,46080"
1400)
1401xt "53000,56000,73000,60000"
1402)
1403oxt "35000,67000,55000,71000"
1404text (MLText
1405uid 326,0
1406va (VaSet
1407fg "0,0,32768"
1408bg "0,0,32768"
1409)
1410xt "53200,56200,62400,57200"
1411st "
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1414tm "CommentText"
1415wrapOption 3
1416visibleHeight 4000
1417visibleWidth 20000
1418)
1419ignorePrefs 1
1420titleBlock 1
1421)
1422*41 (CommentText
1423uid 327,0
1424shape (Rectangle
1425uid 328,0
1426sl 0
1427va (VaSet
1428vasetType 1
1429fg "65280,65280,46080"
1430)
1431xt "57000,55000,73000,56000"
1432)
1433oxt "39000,66000,55000,67000"
1434text (MLText
1435uid 329,0
1436va (VaSet
1437fg "0,0,32768"
1438bg "0,0,32768"
1439)
1440xt "57200,55000,61700,56000"
1441st "
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1444tm "CommentText"
1445wrapOption 3
1446visibleHeight 1000
1447visibleWidth 16000
1448)
1449position 1
1450ignorePrefs 1
1451titleBlock 1
1452)
1453*42 (CommentText
1454uid 330,0
1455shape (Rectangle
1456uid 331,0
1457sl 0
1458va (VaSet
1459vasetType 1
1460fg "65280,65280,46080"
1461)
1462xt "32000,55000,53000,57000"
1463)
1464oxt "14000,66000,35000,68000"
1465text (MLText
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1467va (VaSet
1468fg "32768,0,0"
1469)
1470xt "39150,55500,45850,56500"
1471st "
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1473"
1474ju 0
1475tm "CommentText"
1476wrapOption 3
1477visibleHeight 2000
1478visibleWidth 21000
1479)
1480position 1
1481ignorePrefs 1
1482titleBlock 1
1483)
1484*43 (CommentText
1485uid 333,0
1486shape (Rectangle
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1488sl 0
1489va (VaSet
1490vasetType 1
1491fg "65280,65280,46080"
1492)
1493xt "32000,58000,36000,59000"
1494)
1495oxt "14000,69000,18000,70000"
1496text (MLText
1497uid 335,0
1498va (VaSet
1499fg "0,0,32768"
1500bg "0,0,32768"
1501)
1502xt "32200,58000,34300,59000"
1503st "
1504Path:
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1506tm "CommentText"
1507wrapOption 3
1508visibleHeight 1000
1509visibleWidth 4000
1510)
1511position 1
1512ignorePrefs 1
1513titleBlock 1
1514)
1515*44 (CommentText
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1519sl 0
1520va (VaSet
1521vasetType 1
1522fg "65280,65280,46080"
1523)
1524xt "32000,59000,36000,60000"
1525)
1526oxt "14000,70000,18000,71000"
1527text (MLText
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1529va (VaSet
1530fg "0,0,32768"
1531bg "0,0,32768"
1532)
1533xt "32200,59000,34900,60000"
1534st "
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1537tm "CommentText"
1538wrapOption 3
1539visibleHeight 1000
1540visibleWidth 4000
1541)
1542position 1
1543ignorePrefs 1
1544titleBlock 1
1545)
1546*45 (CommentText
1547uid 339,0
1548shape (Rectangle
1549uid 340,0
1550sl 0
1551va (VaSet
1552vasetType 1
1553fg "65280,65280,46080"
1554)
1555xt "36000,58000,53000,59000"
1556)
1557oxt "18000,69000,35000,70000"
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1560va (VaSet
1561fg "0,0,32768"
1562bg "0,0,32768"
1563)
1564xt "36200,58000,51900,59000"
1565st "
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1568tm "CommentText"
1569wrapOption 3
1570visibleHeight 1000
1571visibleWidth 17000
1572)
1573position 1
1574ignorePrefs 1
1575titleBlock 1
1576)
1577]
1578shape (GroupingShape
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1581vasetType 1
1582fg "65535,65535,65535"
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1584lineWidth 2
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1586xt "32000,55000,73000,60000"
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1588oxt "14000,66000,55000,71000"
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1590*46 (SaComponent
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1596shape (Triangle
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1598ro 90
1599va (VaSet
1600vasetType 1
1601fg "0,65535,0"
1602)
1603xt "12000,38625,12750,39375"
1604)
1605tg (CPTG
1606uid 516,0
1607ps "CptPortTextPlaceStrategy"
1608stg "RightVerticalLayoutStrategy"
1609f (Text
1610uid 517,0
1611va (VaSet
1612)
1613xt "9700,38500,11000,39500"
1614st "clk"
1615ju 2
1616blo "11000,39300"
1617)
1618)
1619thePort (LogicalPort
1620m 1
1621decl (Decl
1622n "clk"
1623t "std_logic"
1624preAdd 0
1625posAdd 0
1626o 1
1627suid 1,0
1628i "'0'"
1629)
1630)
1631)
1632*48 (CptPort
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1634ps "OnEdgeStrategy"
1635shape (Triangle
1636uid 519,0
1637ro 90
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1639vasetType 1
1640fg "0,65535,0"
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1642xt "12000,39625,12750,40375"
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1644tg (CPTG
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1647stg "RightVerticalLayoutStrategy"
1648f (Text
1649uid 521,0
1650va (VaSet
1651)
1652xt "9700,39500,11000,40500"
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1654ju 2
1655blo "11000,40300"
1656)
1657)
1658thePort (LogicalPort
1659m 1
1660decl (Decl
1661n "rst"
1662t "std_logic"
1663preAdd 0
1664posAdd 0
1665o 2
1666suid 2,0
1667i "'0'"
1668)
1669)
1670)
1671]
1672shape (Rectangle
1673uid 526,0
1674va (VaSet
1675vasetType 1
1676fg "0,49152,49152"
1677lineColor "0,0,50000"
1678lineWidth 2
1679)
1680xt "4000,38000,12000,42000"
1681)
1682oxt "22000,15000,30000,19000"
1683ttg (MlTextGroup
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1686stg "VerticalLayoutStrategy"
1687textVec [
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1689uid 528,0
1690va (VaSet
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1693xt "4150,42000,11850,43000"
1694st "FACT_FAD_TB_lib"
1695blo "4150,42800"
1696tm "BdLibraryNameMgr"
1697)
1698*50 (Text
1699uid 529,0
1700va (VaSet
1701font "Arial,8,1"
1702)
1703xt "4150,43000,10850,44000"
1704st "clock_generator"
1705blo "4150,43800"
1706tm "CptNameMgr"
1707)
1708*51 (Text
1709uid 530,0
1710va (VaSet
1711font "Arial,8,1"
1712)
1713xt "4150,44000,5950,45000"
1714st "U_2"
1715blo "4150,44800"
1716tm "InstanceNameMgr"
1717)
1718]
1719)
1720ga (GenericAssociation
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1722ps "EdgeToEdgeStrategy"
1723matrix (Matrix
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1725text (MLText
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1734header ""
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1736elements [
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1739type "time"
1740value "20 ns"
1741)
1742(GiElement
1743name "reset_time"
1744type "time"
1745value "50 ns"
1746)
1747]
1748)
1749viewicon (ZoomableIcon
1750uid 534,0
1751sl 0
1752va (VaSet
1753vasetType 1
1754fg "49152,49152,49152"
1755)
1756xt "4250,40250,5750,41750"
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1758iconMaskName "VhdlFileViewIcon.msk"
1759ftype 10
1760)
1761ordering 1
1762viewiconposition 0
1763portVis (PortSigDisplay
1764)
1765archFileType "UNKNOWN"
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1767*52 (Wire
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1769shape (OrthoPolyLine
1770uid 83,0
1771va (VaSet
1772vasetType 3
1773)
1774xt "26750,9000,36000,9000"
1775pts [
1776"26750,9000"
1777"36000,9000"
1778]
1779)
1780start &3
1781sat 32
1782eat 16
1783st 0
1784sf 1
1785tg (WTG
1786uid 86,0
1787ps "ConnStartEndStrategy"
1788stg "STSignalDisplayStrategy"
1789f (Text
1790uid 87,0
1791va (VaSet
1792)
1793xt "28000,8000,30900,9000"
1794st "PSCLK"
1795blo "28000,8800"
1796tm "WireNameMgr"
1797)
1798)
1799on &18
1800)
1801*53 (Wire
1802uid 90,0
1803shape (OrthoPolyLine
1804uid 91,0
1805va (VaSet
1806vasetType 3
1807)
1808xt "26750,11000,36000,11000"
1809pts [
1810"26750,11000"
1811"36000,11000"
1812]
1813)
1814start &4
1815sat 32
1816eat 16
1817st 0
1818sf 1
1819tg (WTG
1820uid 94,0
1821ps "ConnStartEndStrategy"
1822stg "STSignalDisplayStrategy"
1823f (Text
1824uid 95,0
1825va (VaSet
1826)
1827xt "28000,10000,30500,11000"
1828st "PSEN"
1829blo "28000,10800"
1830tm "WireNameMgr"
1831)
1832)
1833on &19
1834)
1835*54 (Wire
1836uid 99,0
1837shape (OrthoPolyLine
1838uid 100,0
1839va (VaSet
1840vasetType 3
1841)
1842xt "26750,13000,36000,13000"
1843pts [
1844"26750,13000"
1845"36000,13000"
1846]
1847)
1848start &5
1849sat 32
1850eat 16
1851st 0
1852sf 1
1853tg (WTG
1854uid 103,0
1855ps "ConnStartEndStrategy"
1856stg "STSignalDisplayStrategy"
1857f (Text
1858uid 104,0
1859va (VaSet
1860)
1861xt "28000,12000,32500,13000"
1862st "PSINCDEC"
1863blo "28000,12800"
1864tm "WireNameMgr"
1865)
1866)
1867on &20
1868)
1869*55 (Wire
1870uid 108,0
1871shape (OrthoPolyLine
1872uid 109,0
1873va (VaSet
1874vasetType 3
1875)
1876xt "26750,15000,36000,15000"
1877pts [
1878"26750,15000"
1879"36000,15000"
1880]
1881)
1882start &10
1883sat 32
1884eat 16
1885st 0
1886sf 1
1887tg (WTG
1888uid 112,0
1889ps "ConnStartEndStrategy"
1890stg "STSignalDisplayStrategy"
1891f (Text
1892uid 113,0
1893va (VaSet
1894)
1895xt "28000,14000,30900,15000"
1896st "shifting"
1897blo "28000,14800"
1898tm "WireNameMgr"
1899)
1900)
1901on &21
1902)
1903*56 (Wire
1904uid 117,0
1905shape (OrthoPolyLine
1906uid 118,0
1907va (VaSet
1908vasetType 3
1909)
1910xt "26750,17000,36000,17000"
1911pts [
1912"26750,17000"
1913"36000,17000"
1914]
1915)
1916start &11
1917sat 32
1918eat 16
1919st 0
1920sf 1
1921tg (WTG
1922uid 121,0
1923ps "ConnStartEndStrategy"
1924stg "STSignalDisplayStrategy"
1925f (Text
1926uid 122,0
1927va (VaSet
1928)
1929xt "28000,16000,30200,17000"
1930st "ready"
1931blo "28000,16800"
1932tm "WireNameMgr"
1933)
1934)
1935on &22
1936)
1937*57 (Wire
1938uid 126,0
1939shape (OrthoPolyLine
1940uid 127,0
1941va (VaSet
1942vasetType 3
1943lineWidth 2
1944)
1945xt "26750,19000,36000,19000"
1946pts [
1947"26750,19000"
1948"36000,19000"
1949]
1950)
1951start &12
1952sat 32
1953eat 16
1954sty 1
1955st 0
1956sf 1
1957tg (WTG
1958uid 130,0
1959ps "ConnStartEndStrategy"
1960stg "STSignalDisplayStrategy"
1961f (Text
1962uid 131,0
1963va (VaSet
1964)
1965xt "28000,18000,32800,19000"
1966st "offset : (7:0)"
1967blo "28000,18800"
1968tm "WireNameMgr"
1969)
1970)
1971on &23
1972)
1973*58 (Wire
1974uid 135,0
1975shape (OrthoPolyLine
1976uid 136,0
1977va (VaSet
1978vasetType 3
1979)
1980xt "1000,9000,19000,39000"
1981pts [
1982"12750,39000"
1983"19000,39000"
1984"19000,33000"
1985"1000,33000"
1986"1000,9000"
1987"10250,9000"
1988]
1989)
1990start &47
1991end &2
1992sat 32
1993eat 32
1994st 0
1995sf 1
1996tg (WTG
1997uid 139,0
1998ps "ConnStartEndStrategy"
1999stg "STSignalDisplayStrategy"
2000f (Text
2001uid 140,0
2002va (VaSet
2003)
2004xt "14750,38000,16050,39000"
2005st "clk"
2006blo "14750,38800"
2007tm "WireNameMgr"
2008)
2009)
2010on &24
2011)
2012*59 (Wire
2013uid 143,0
2014shape (OrthoPolyLine
2015uid 144,0
2016va (VaSet
2017vasetType 3
2018)
2019xt "3000,11000,10250,11000"
2020pts [
2021"3000,11000"
2022"10250,11000"
2023]
2024)
2025end &6
2026sat 16
2027eat 32
2028st 0
2029sf 1
2030tg (WTG
2031uid 147,0
2032ps "ConnStartEndStrategy"
2033stg "STSignalDisplayStrategy"
2034f (Text
2035uid 148,0
2036va (VaSet
2037)
2038xt "4000,10000,7700,11000"
2039st "PSDONE"
2040blo "4000,10800"
2041tm "WireNameMgr"
2042)
2043)
2044on &25
2045)
2046*60 (Wire
2047uid 151,0
2048shape (OrthoPolyLine
2049uid 152,0
2050va (VaSet
2051vasetType 3
2052)
2053xt "3000,13000,10250,13000"
2054pts [
2055"3000,13000"
2056"10250,13000"
2057]
2058)
2059end &7
2060sat 16
2061eat 32
2062st 0
2063sf 1
2064tg (WTG
2065uid 155,0
2066ps "ConnStartEndStrategy"
2067stg "STSignalDisplayStrategy"
2068f (Text
2069uid 156,0
2070va (VaSet
2071)
2072xt "4000,12000,7600,13000"
2073st "LOCKED"
2074blo "4000,12800"
2075tm "WireNameMgr"
2076)
2077)
2078on &26
2079)
2080*61 (Wire
2081uid 159,0
2082shape (OrthoPolyLine
2083uid 160,0
2084va (VaSet
2085vasetType 3
2086)
2087xt "3000,17000,10250,17000"
2088pts [
2089"3000,17000"
2090"10250,17000"
2091]
2092)
2093end &8
2094sat 16
2095eat 32
2096st 0
2097sf 1
2098tg (WTG
2099uid 163,0
2100ps "ConnStartEndStrategy"
2101stg "STSignalDisplayStrategy"
2102f (Text
2103uid 164,0
2104va (VaSet
2105)
2106xt "4000,16000,8600,17000"
2107st "shift_phase"
2108blo "4000,16800"
2109tm "WireNameMgr"
2110)
2111)
2112on &27
2113)
2114*62 (Wire
2115uid 167,0
2116shape (OrthoPolyLine
2117uid 168,0
2118va (VaSet
2119vasetType 3
2120)
2121xt "3000,19000,10250,19000"
2122pts [
2123"3000,19000"
2124"10250,19000"
2125]
2126)
2127end &9
2128sat 16
2129eat 32
2130st 0
2131sf 1
2132tg (WTG
2133uid 171,0
2134ps "ConnStartEndStrategy"
2135stg "STSignalDisplayStrategy"
2136f (Text
2137uid 172,0
2138va (VaSet
2139)
2140xt "4000,18000,7300,19000"
2141st "direction"
2142blo "4000,18800"
2143tm "WireNameMgr"
2144)
2145)
2146on &28
2147)
2148*63 (Wire
2149uid 175,0
2150shape (OrthoPolyLine
2151uid 176,0
2152va (VaSet
2153vasetType 3
2154)
2155xt "3000,20000,10250,20000"
2156pts [
2157"10250,20000"
2158"3000,20000"
2159]
2160)
2161start &13
2162sat 32
2163eat 16
2164st 0
2165sf 1
2166tg (WTG
2167uid 179,0
2168ps "ConnStartEndStrategy"
2169stg "STSignalDisplayStrategy"
2170f (Text
2171uid 180,0
2172va (VaSet
2173)
2174xt "4000,19000,5300,20000"
2175st "rst"
2176blo "4000,19800"
2177tm "WireNameMgr"
2178)
2179)
2180on &29
2181)
2182*64 (Wire
2183uid 184,0
2184shape (OrthoPolyLine
2185uid 185,0
2186va (VaSet
2187vasetType 3
2188)
2189xt "3000,22000,10250,22000"
2190pts [
2191"3000,22000"
2192"10250,22000"
2193]
2194)
2195end &14
2196sat 16
2197eat 32
2198st 0
2199sf 1
2200tg (WTG
2201uid 188,0
2202ps "ConnStartEndStrategy"
2203stg "STSignalDisplayStrategy"
2204f (Text
2205uid 189,0
2206va (VaSet
2207)
2208xt "4000,21000,8400,22000"
2209st "reset_DCM"
2210blo "4000,21800"
2211tm "WireNameMgr"
2212)
2213)
2214on &30
2215)
2216*65 (Wire
2217uid 200,0
2218shape (OrthoPolyLine
2219uid 201,0
2220va (VaSet
2221vasetType 3
2222)
2223xt "46000,19000,54000,19000"
2224pts [
2225"46000,19000"
2226"54000,19000"
2227]
2228)
2229end &31
2230sat 16
2231eat 2
2232st 0
2233sf 1
2234tg (WTG
2235uid 206,0
2236ps "ConnStartEndStrategy"
2237stg "STSignalDisplayStrategy"
2238f (Text
2239uid 207,0
2240va (VaSet
2241)
2242xt "47000,18000,51600,19000"
2243st "shift_phase"
2244blo "47000,18800"
2245tm "WireNameMgr"
2246)
2247)
2248on &27
2249)
2250*66 (Wire
2251uid 208,0
2252shape (OrthoPolyLine
2253uid 209,0
2254va (VaSet
2255vasetType 3
2256)
2257xt "46000,21000,54000,21000"
2258pts [
2259"46000,21000"
2260"54000,21000"
2261]
2262)
2263end &31
2264sat 16
2265eat 2
2266st 0
2267sf 1
2268tg (WTG
2269uid 214,0
2270ps "ConnStartEndStrategy"
2271stg "STSignalDisplayStrategy"
2272f (Text
2273uid 215,0
2274va (VaSet
2275)
2276xt "47000,20000,50300,21000"
2277st "direction"
2278blo "47000,20800"
2279tm "WireNameMgr"
2280)
2281)
2282on &28
2283)
2284*67 (Wire
2285uid 216,0
2286shape (OrthoPolyLine
2287uid 217,0
2288va (VaSet
2289vasetType 3
2290)
2291xt "46000,22000,54000,22000"
2292pts [
2293"54000,22000"
2294"46000,22000"
2295]
2296)
2297start &31
2298sat 1
2299eat 16
2300st 0
2301sf 1
2302tg (WTG
2303uid 222,0
2304ps "ConnStartEndStrategy"
2305stg "STSignalDisplayStrategy"
2306f (Text
2307uid 223,0
2308va (VaSet
2309)
2310xt "47000,21000,48300,22000"
2311st "rst"
2312blo "47000,21800"
2313tm "WireNameMgr"
2314)
2315)
2316on &29
2317)
2318*68 (Wire
2319uid 225,0
2320shape (OrthoPolyLine
2321uid 226,0
2322va (VaSet
2323vasetType 3
2324)
2325xt "46000,13000,54000,13000"
2326pts [
2327"46000,13000"
2328"54000,13000"
2329]
2330)
2331end &31
2332sat 16
2333eat 2
2334st 0
2335sf 1
2336tg (WTG
2337uid 231,0
2338ps "ConnStartEndStrategy"
2339stg "STSignalDisplayStrategy"
2340f (Text
2341uid 232,0
2342va (VaSet
2343)
2344xt "47000,12000,50700,13000"
2345st "PSDONE"
2346blo "47000,12800"
2347tm "WireNameMgr"
2348)
2349)
2350on &25
2351)
2352*69 (Wire
2353uid 233,0
2354shape (OrthoPolyLine
2355uid 234,0
2356va (VaSet
2357vasetType 3
2358)
2359xt "46000,24000,54000,24000"
2360pts [
2361"46000,24000"
2362"54000,24000"
2363]
2364)
2365end &31
2366sat 16
2367eat 2
2368st 0
2369sf 1
2370tg (WTG
2371uid 239,0
2372ps "ConnStartEndStrategy"
2373stg "STSignalDisplayStrategy"
2374f (Text
2375uid 240,0
2376va (VaSet
2377)
2378xt "47000,23000,51400,24000"
2379st "reset_DCM"
2380blo "47000,23800"
2381tm "WireNameMgr"
2382)
2383)
2384on &30
2385)
2386*70 (Wire
2387uid 241,0
2388shape (OrthoPolyLine
2389uid 242,0
2390va (VaSet
2391vasetType 3
2392)
2393xt "69000,17000,79000,17000"
2394pts [
2395"69000,17000"
2396"79000,17000"
2397]
2398)
2399start &31
2400sat 1
2401eat 16
2402st 0
2403sf 1
2404tg (WTG
2405uid 247,0
2406ps "ConnStartEndStrategy"
2407stg "STSignalDisplayStrategy"
2408f (Text
2409uid 248,0
2410va (VaSet
2411)
2412xt "70000,16000,72900,17000"
2413st "shifting"
2414blo "70000,16800"
2415tm "WireNameMgr"
2416)
2417)
2418on &21
2419)
2420*71 (Wire
2421uid 250,0
2422shape (OrthoPolyLine
2423uid 251,0
2424va (VaSet
2425vasetType 3
2426)
2427xt "69000,19000,79000,19000"
2428pts [
2429"69000,19000"
2430"79000,19000"
2431]
2432)
2433start &31
2434sat 1
2435eat 16
2436st 0
2437sf 1
2438tg (WTG
2439uid 256,0
2440ps "ConnStartEndStrategy"
2441stg "STSignalDisplayStrategy"
2442f (Text
2443uid 257,0
2444va (VaSet
2445)
2446xt "70000,18000,72200,19000"
2447st "ready"
2448blo "70000,18800"
2449tm "WireNameMgr"
2450)
2451)
2452on &22
2453)
2454*72 (Wire
2455uid 259,0
2456shape (OrthoPolyLine
2457uid 260,0
2458va (VaSet
2459vasetType 3
2460lineWidth 2
2461)
2462xt "69000,21000,79000,21000"
2463pts [
2464"69000,21000"
2465"79000,21000"
2466]
2467)
2468start &31
2469sat 1
2470eat 16
2471sty 1
2472st 0
2473sf 1
2474tg (WTG
2475uid 265,0
2476ps "ConnStartEndStrategy"
2477stg "STSignalDisplayStrategy"
2478f (Text
2479uid 266,0
2480va (VaSet
2481)
2482xt "71000,20000,75800,21000"
2483st "offset : (7:0)"
2484blo "71000,20800"
2485tm "WireNameMgr"
2486)
2487)
2488on &23
2489)
2490*73 (Wire
2491uid 268,0
2492shape (OrthoPolyLine
2493uid 269,0
2494va (VaSet
2495vasetType 3
2496)
2497xt "46000,11000,54000,11000"
2498pts [
2499"46000,11000"
2500"54000,11000"
2501]
2502)
2503sat 16
2504eat 16
2505st 0
2506sf 1
2507tg (WTG
2508uid 274,0
2509ps "ConnStartEndStrategy"
2510stg "STSignalDisplayStrategy"
2511f (Text
2512uid 275,0
2513va (VaSet
2514)
2515xt "47000,10000,48300,11000"
2516st "clk"
2517blo "47000,10800"
2518tm "WireNameMgr"
2519)
2520)
2521on &24
2522)
2523*74 (Wire
2524uid 276,0
2525shape (OrthoPolyLine
2526uid 277,0
2527va (VaSet
2528vasetType 3
2529)
2530xt "46000,15000,54000,15000"
2531pts [
2532"46000,15000"
2533"54000,15000"
2534]
2535)
2536end &31
2537sat 16
2538eat 2
2539st 0
2540sf 1
2541tg (WTG
2542uid 282,0
2543ps "ConnStartEndStrategy"
2544stg "STSignalDisplayStrategy"
2545f (Text
2546uid 283,0
2547va (VaSet
2548)
2549xt "47000,14000,50600,15000"
2550st "LOCKED"
2551blo "47000,14800"
2552tm "WireNameMgr"
2553)
2554)
2555on &26
2556)
2557*75 (Wire
2558uid 284,0
2559shape (OrthoPolyLine
2560uid 285,0
2561va (VaSet
2562vasetType 3
2563)
2564xt "69000,11000,79000,11000"
2565pts [
2566"69000,11000"
2567"79000,11000"
2568]
2569)
2570start &31
2571sat 1
2572eat 16
2573st 0
2574sf 1
2575tg (WTG
2576uid 290,0
2577ps "ConnStartEndStrategy"
2578stg "STSignalDisplayStrategy"
2579f (Text
2580uid 291,0
2581va (VaSet
2582)
2583xt "70000,10000,72900,11000"
2584st "PSCLK"
2585blo "70000,10800"
2586tm "WireNameMgr"
2587)
2588)
2589on &18
2590)
2591*76 (Wire
2592uid 292,0
2593shape (OrthoPolyLine
2594uid 293,0
2595va (VaSet
2596vasetType 3
2597)
2598xt "69000,13000,79000,13000"
2599pts [
2600"69000,13000"
2601"79000,13000"
2602]
2603)
2604start &31
2605sat 1
2606eat 16
2607st 0
2608sf 1
2609tg (WTG
2610uid 298,0
2611ps "ConnStartEndStrategy"
2612stg "STSignalDisplayStrategy"
2613f (Text
2614uid 299,0
2615va (VaSet
2616)
2617xt "70000,12000,72500,13000"
2618st "PSEN"
2619blo "70000,12800"
2620tm "WireNameMgr"
2621)
2622)
2623on &19
2624)
2625*77 (Wire
2626uid 301,0
2627shape (OrthoPolyLine
2628uid 302,0
2629va (VaSet
2630vasetType 3
2631)
2632xt "69000,15000,79000,15000"
2633pts [
2634"69000,15000"
2635"79000,15000"
2636]
2637)
2638start &31
2639sat 1
2640eat 16
2641st 0
2642sf 1
2643tg (WTG
2644uid 307,0
2645ps "ConnStartEndStrategy"
2646stg "STSignalDisplayStrategy"
2647f (Text
2648uid 308,0
2649va (VaSet
2650)
2651xt "70000,14000,74500,15000"
2652st "PSINCDEC"
2653blo "70000,14800"
2654tm "WireNameMgr"
2655)
2656)
2657on &20
2658)
2659*78 (Wire
2660uid 535,0
2661shape (OrthoPolyLine
2662uid 536,0
2663va (VaSet
2664vasetType 3
2665)
2666xt "44000,25000,54000,25000"
2667pts [
2668"44000,25000"
2669"54000,25000"
2670]
2671)
2672end &31
2673sat 16
2674eat 1
2675st 0
2676sf 1
2677si 0
2678tg (WTG
2679uid 541,0
2680ps "ConnStartEndStrategy"
2681stg "STSignalDisplayStrategy"
2682f (Text
2683uid 542,0
2684va (VaSet
2685)
2686xt "46000,24000,47300,25000"
2687st "clk"
2688blo "46000,24800"
2689tm "WireNameMgr"
2690)
2691)
2692on &24
2693)
2694]
2695bg "65535,65535,65535"
2696grid (Grid
2697origin "0,0"
2698isVisible 1
2699isActive 1
2700xSpacing 1000
2701xySpacing 1000
2702xShown 1
2703yShown 1
2704color "26368,26368,26368"
2705)
2706packageList *79 (PackageList
2707uid 368,0
2708stg "VerticalLayoutStrategy"
2709textVec [
2710*80 (Text
2711uid 369,0
2712va (VaSet
2713font "arial,8,1"
2714)
2715xt "0,0,5400,1000"
2716st "Package List"
2717blo "0,800"
2718)
2719*81 (MLText
2720uid 370,0
2721va (VaSet
2722)
2723xt "0,1000,15000,8000"
2724st "LIBRARY ieee;
2725USE ieee.std_logic_1164.ALL;
2726USE IEEE.NUMERIC_STD.ALL;
2727LIBRARY FACT_FAD_lib;
2728USE FACT_FAD_lib.fad_definitions.ALL;
2729USE ieee.std_logic_unsigned.all;
2730USE ieee.std_logic_arith.all;"
2731tm "PackageList"
2732)
2733]
2734)
2735compDirBlock (MlTextGroup
2736uid 371,0
2737stg "VerticalLayoutStrategy"
2738textVec [
2739*82 (Text
2740uid 372,0
2741va (VaSet
2742isHidden 1
2743font "Arial,8,1"
2744)
2745xt "20000,0,28100,1000"
2746st "Compiler Directives"
2747blo "20000,800"
2748)
2749*83 (Text
2750uid 373,0
2751va (VaSet
2752isHidden 1
2753font "Arial,8,1"
2754)
2755xt "20000,1000,29600,2000"
2756st "Pre-module directives:"
2757blo "20000,1800"
2758)
2759*84 (MLText
2760uid 374,0
2761va (VaSet
2762isHidden 1
2763)
2764xt "20000,2000,27500,4000"
2765st "`resetall
2766`timescale 1ns/10ps"
2767tm "BdCompilerDirectivesTextMgr"
2768)
2769*85 (Text
2770uid 375,0
2771va (VaSet
2772isHidden 1
2773font "Arial,8,1"
2774)
2775xt "20000,4000,30100,5000"
2776st "Post-module directives:"
2777blo "20000,4800"
2778)
2779*86 (MLText
2780uid 376,0
2781va (VaSet
2782isHidden 1
2783)
2784xt "20000,0,20000,0"
2785tm "BdCompilerDirectivesTextMgr"
2786)
2787*87 (Text
2788uid 377,0
2789va (VaSet
2790isHidden 1
2791font "Arial,8,1"
2792)
2793xt "20000,5000,29900,6000"
2794st "End-module directives:"
2795blo "20000,5800"
2796)
2797*88 (MLText
2798uid 378,0
2799va (VaSet
2800isHidden 1
2801)
2802xt "20000,6000,20000,6000"
2803tm "BdCompilerDirectivesTextMgr"
2804)
2805]
2806associable 1
2807)
2808windowSize "-4,-4,1284,998"
2809viewArea "22779,-12050,84296,35470"
2810cachedDiagramExtent "0,-16000,79400,60000"
2811hasePageBreakOrigin 1
2812pageBreakOrigin "0,0"
2813lastUid 576,0
2814defaultCommentText (CommentText
2815shape (Rectangle
2816layer 0
2817va (VaSet
2818vasetType 1
2819fg "65280,65280,46080"
2820lineColor "0,0,32768"
2821)
2822xt "0,0,15000,5000"
2823)
2824text (MLText
2825va (VaSet
2826fg "0,0,32768"
2827)
2828xt "200,200,2000,1200"
2829st "
2830Text
2831"
2832tm "CommentText"
2833wrapOption 3
2834visibleHeight 4600
2835visibleWidth 14600
2836)
2837)
2838defaultPanel (Panel
2839shape (RectFrame
2840va (VaSet
2841vasetType 1
2842fg "65535,65535,65535"
2843lineColor "32768,0,0"
2844lineWidth 3
2845)
2846xt "0,0,20000,20000"
2847)
2848title (TextAssociate
2849ps "TopLeftStrategy"
2850text (Text
2851va (VaSet
2852font "Arial,8,1"
2853)
2854xt "1000,1000,3800,2000"
2855st "Panel0"
2856blo "1000,1800"
2857tm "PanelText"
2858)
2859)
2860)
2861defaultBlk (Blk
2862shape (Rectangle
2863va (VaSet
2864vasetType 1
2865fg "39936,56832,65280"
2866lineColor "0,0,32768"
2867lineWidth 2
2868)
2869xt "0,0,8000,10000"
2870)
2871ttg (MlTextGroup
2872ps "CenterOffsetStrategy"
2873stg "VerticalLayoutStrategy"
2874textVec [
2875*89 (Text
2876va (VaSet
2877font "Arial,8,1"
2878)
2879xt "2200,3500,5800,4500"
2880st "<library>"
2881blo "2200,4300"
2882tm "BdLibraryNameMgr"
2883)
2884*90 (Text
2885va (VaSet
2886font "Arial,8,1"
2887)
2888xt "2200,4500,5600,5500"
2889st "<block>"
2890blo "2200,5300"
2891tm "BlkNameMgr"
2892)
2893*91 (Text
2894va (VaSet
2895font "Arial,8,1"
2896)
2897xt "2200,5500,4000,6500"
2898st "U_0"
2899blo "2200,6300"
2900tm "InstanceNameMgr"
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2907text (MLText
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2983]
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2985portVis (PortSigDisplay
2986)
2987prms (Property
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2989pname "params"
2990ptn "String"
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3035)
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3037)
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3041text (MLText
3042va (VaSet
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3052viewicon (ZoomableIcon
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3056fg "49152,49152,49152"
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3058xt "0,0,1500,1500"
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3060iconMaskName "UnknownFile.msk"
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3062viewiconposition 0
3063portVis (PortSigDisplay
3064)
3065archFileType "UNKNOWN"
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3067defaultVhdlComponent (VhdlComponent
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3073lineWidth 2
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3104tm "InstanceNameMgr"
3105)
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3108ga (GenericAssociation
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3111text (MLText
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3123)
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3132fg "0,65535,0"
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3140stg "VerticalLayoutStrategy"
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3165tm "InstanceNameMgr"
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3169ga (GenericAssociation
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3181]
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3200va (VaSet
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3208*105 (Text
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3216)
3217]
3218)
3219viewicon (ZoomableIcon
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3223fg "49152,49152,49152"
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3225xt "0,0,1500,1500"
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3227iconMaskName "UnknownFile.msk"
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3229viewiconposition 0
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3231defaultEmbeddedText (EmbeddedText
3232commentText (CommentText
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3234shape (Rectangle
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3241xt "0,0,18000,5000"
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3243text (MLText
3244va (VaSet
3245)
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3248Text
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3250tm "HdlTextMgr"
3251wrapOption 3
3252visibleHeight 4600
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3255)
3256)
3257defaultGlobalConnector (GlobalConnector
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3261fg "65535,65535,0"
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3263xt "-1000,-1000,1000,1000"
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3266name (Text
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3270xt "-500,-500,500,500"
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3275defaultRipper (Ripper
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3282va (VaSet
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3284)
3285xt "0,0,1000,1000"
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3287)
3288defaultBdJunction (BdJunction
3289ps "OnConnectorStrategy"
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3291va (VaSet
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3294xt "-400,-400,400,400"
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3298defaultPortIoIn (PortIoIn
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3302fg "0,0,32768"
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3310(Line
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3316"0,0"
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3318)
3319]
3320)
3321stc 0
3322sf 1
3323tg (WTG
3324ps "PortIoTextPlaceStrategy"
3325stg "STSignalDisplayStrategy"
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3327va (VaSet
3328)
3329xt "-1375,-1000,-1375,-1000"
3330ju 2
3331blo "-1375,-1000"
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3334)
3335)
3336defaultPortIoOut (PortIoOut
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3342optionalChildren [
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3348(Line
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3356)
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3358)
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3360sf 1
3361tg (WTG
3362ps "PortIoTextPlaceStrategy"
3363stg "STSignalDisplayStrategy"
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3365va (VaSet
3366)
3367xt "625,-1000,625,-1000"
3368blo "625,-1000"
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3370)
3371)
3372)
3373defaultPortIoInOut (PortIoInOut
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3379optionalChildren [
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3384(Line
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3391)
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3393)
3394stc 0
3395sf 1
3396tg (WTG
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3398stg "STSignalDisplayStrategy"
3399f (Text
3400va (VaSet
3401)
3402xt "0,-375,0,-375"
3403blo "0,-375"
3404tm "WireNameMgr"
3405)
3406)
3407)
3408defaultPortIoBuffer (PortIoBuffer
3409shape (CompositeShape
3410va (VaSet
3411vasetType 1
3412fg "65535,65535,65535"
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3415optionalChildren [
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3420(Line
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3424"0,0"
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3427)
3428]
3429)
3430stc 0
3431sf 1
3432tg (WTG
3433ps "PortIoTextPlaceStrategy"
3434stg "STSignalDisplayStrategy"
3435f (Text
3436va (VaSet
3437)
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3440tm "WireNameMgr"
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3442)
3443)
3444defaultSignal (Wire
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3447vasetType 3
3448)
3449pts [
3450"0,0"
3451"0,0"
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3453)
3454ss 0
3455es 0
3456sat 32
3457eat 32
3458st 0
3459sf 1
3460si 0
3461tg (WTG
3462ps "ConnStartEndStrategy"
3463stg "STSignalDisplayStrategy"
3464f (Text
3465va (VaSet
3466)
3467xt "0,0,1900,1000"
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3470tm "WireNameMgr"
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3472)
3473)
3474defaultBus (Wire
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3477vasetType 3
3478lineWidth 2
3479)
3480pts [
3481"0,0"
3482"0,0"
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3484)
3485ss 0
3486es 0
3487sat 32
3488eat 32
3489sty 1
3490st 0
3491sf 1
3492si 0
3493tg (WTG
3494ps "ConnStartEndStrategy"
3495stg "STSignalDisplayStrategy"
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3498)
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3501blo "0,800"
3502tm "WireNameMgr"
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3504)
3505)
3506defaultBundle (Bundle
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3511lineWidth 2
3512)
3513pts [
3514"0,0"
3515"0,0"
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3518ss 0
3519es 0
3520sat 32
3521eat 32
3522textGroup (BiTextGroup
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3524stg "VerticalLayoutStrategy"
3525first (Text
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3531tm "BundleNameMgr"
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3533second (MLText
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3538tm "BundleContentsMgr"
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3541bundleNet &0
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3543defaultPortMapFrame (PortMapFrame
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3550lineWidth 2
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3552xt "0,0,10000,12000"
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3554portMapText (BiTextGroup
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3556stg "VerticalLayoutStrategy"
3557first (MLText
3558va (VaSet
3559)
3560)
3561second (MLText
3562va (VaSet
3563)
3564tm "PortMapTextMgr"
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3566)
3567)
3568defaultGenFrame (Frame
3569shape (RectFrame
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3571vasetType 1
3572fg "65535,65535,65535"
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3574lineStyle 2
3575lineWidth 3
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3577xt "0,0,20000,20000"
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3579title (TextAssociate
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3581text (MLText
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3583)
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3585st "g0: FOR i IN 0 TO n GENERATE"
3586tm "FrameTitleTextMgr"
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3588)
3589seqNum (FrameSequenceNumber
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3591shape (Rectangle
3592va (VaSet
3593vasetType 1
3594fg "65535,65535,65535"
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3596xt "50,50,1250,1450"
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3598num (Text
3599va (VaSet
3600)
3601xt "250,250,1050,1250"
3602st "1"
3603blo "250,1050"
3604tm "FrameSeqNumMgr"
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3607decls (MlTextGroup
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3609stg "VerticalLayoutStrategy"
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3611*106 (Text
3612va (VaSet
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3617blo "14100,20800"
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3619*107 (MLText
3620va (VaSet
3621)
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3624)
3625]
3626)
3627)
3628defaultBlockFrame (Frame
3629shape (RectFrame
3630va (VaSet
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3632fg "65535,65535,65535"
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3634lineStyle 1
3635lineWidth 3
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3637xt "0,0,20000,20000"
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3639title (TextAssociate
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3641text (MLText
3642va (VaSet
3643)
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3645st "b0: BLOCK (guard)"
3646tm "FrameTitleTextMgr"
3647)
3648)
3649seqNum (FrameSequenceNumber
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3652va (VaSet
3653vasetType 1
3654fg "65535,65535,65535"
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3656xt "50,50,1250,1450"
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3658num (Text
3659va (VaSet
3660)
3661xt "250,250,1050,1250"
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3663blo "250,1050"
3664tm "FrameSeqNumMgr"
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3669stg "VerticalLayoutStrategy"
3670textVec [
3671*108 (Text
3672va (VaSet
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3679*109 (MLText
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3681)
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3683tm "BdFrameDeclTextMgr"
3684)
3685]
3686)
3687style 3
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3689defaultSaCptPort (CptPort
3690ps "OnEdgeStrategy"
3691shape (Triangle
3692ro 90
3693va (VaSet
3694vasetType 1
3695fg "0,65535,0"
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3697xt "0,0,750,750"
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3699tg (CPTG
3700ps "CptPortTextPlaceStrategy"
3701stg "VerticalLayoutStrategy"
3702f (Text
3703va (VaSet
3704)
3705xt "0,750,1800,1750"
3706st "Port"
3707blo "0,1550"
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3709)
3710thePort (LogicalPort
3711decl (Decl
3712n "Port"
3713t ""
3714o 0
3715)
3716)
3717)
3718defaultSaCptPortBuffer (CptPort
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3723fg "65535,65535,65535"
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3725xt "0,0,750,750"
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3727tg (CPTG
3728ps "CptPortTextPlaceStrategy"
3729stg "VerticalLayoutStrategy"
3730f (Text
3731va (VaSet
3732)
3733xt "0,750,1800,1750"
3734st "Port"
3735blo "0,1550"
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3737)
3738thePort (LogicalPort
3739m 3
3740decl (Decl
3741n "Port"
3742t ""
3743o 0
3744)
3745)
3746)
3747defaultDeclText (MLText
3748va (VaSet
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3751)
3752archDeclarativeBlock (BdArchDeclBlock
3753uid 1,0
3754stg "BdArchDeclBlockLS"
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3756uid 2,0
3757va (VaSet
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3761st "Declarations"
3762blo "11000,-15200"
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3764portLabel (Text
3765uid 3,0
3766va (VaSet
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3769xt "11000,-15000,13700,-14000"
3770st "Ports:"
3771blo "11000,-14200"
3772)
3773preUserLabel (Text
3774uid 4,0
3775va (VaSet
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3777font "Arial,8,1"
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3779xt "11000,-16000,14800,-15000"
3780st "Pre User:"
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3782)
3783preUserText (MLText
3784uid 5,0
3785va (VaSet
3786isHidden 1
3787font "Courier New,8,0"
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3789xt "11000,-16000,11000,-16000"
3790tm "BdDeclarativeTextMgr"
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3792diagSignalLabel (Text
3793uid 6,0
3794va (VaSet
3795font "Arial,8,1"
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3797xt "11000,-14000,18100,-13000"
3798st "Diagram Signals:"
3799blo "11000,-13200"
3800)
3801postUserLabel (Text
3802uid 7,0
3803va (VaSet
3804isHidden 1
3805font "Arial,8,1"
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3807xt "11000,-16000,15700,-15000"
3808st "Post User:"
3809blo "11000,-15200"
3810)
3811postUserText (MLText
3812uid 8,0
3813va (VaSet
3814isHidden 1
3815font "Courier New,8,0"
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3817xt "11000,-16000,11000,-16000"
3818tm "BdDeclarativeTextMgr"
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3821commonDM (CommonDM
3822ldm (LogicalDM
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3824usingSuid 1
3825emptyRow *110 (LEmptyRow
3826)
3827uid 381,0
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3830)
3831*112 (TitleRowHdr
3832)
3833*113 (FilterRowHdr
3834)
3835*114 (RefLabelColHdr
3836tm "RefLabelColHdrMgr"
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3838*115 (RowExpandColHdr
3839tm "RowExpandColHdrMgr"
3840)
3841*116 (GroupColHdr
3842tm "GroupColHdrMgr"
3843)
3844*117 (NameColHdr
3845tm "BlockDiagramNameColHdrMgr"
3846)
3847*118 (ModeColHdr
3848tm "BlockDiagramModeColHdrMgr"
3849)
3850*119 (TypeColHdr
3851tm "BlockDiagramTypeColHdrMgr"
3852)
3853*120 (BoundsColHdr
3854tm "BlockDiagramBoundsColHdrMgr"
3855)
3856*121 (InitColHdr
3857tm "BlockDiagramInitColHdrMgr"
3858)
3859*122 (EolColHdr
3860tm "BlockDiagramEolColHdrMgr"
3861)
3862*123 (LeafLogPort
3863port (LogicalPort
3864lang 10
3865m 4
3866decl (Decl
3867n "PSCLK"
3868t "std_logic"
3869o 1
3870suid 1,0
3871)
3872)
3873uid 342,0
3874)
3875*124 (LeafLogPort
3876port (LogicalPort
3877lang 10
3878m 4
3879decl (Decl
3880n "PSEN"
3881t "std_logic"
3882o 2
3883suid 2,0
3884)
3885)
3886uid 344,0
3887)
3888*125 (LeafLogPort
3889port (LogicalPort
3890lang 10
3891m 4
3892decl (Decl
3893n "PSINCDEC"
3894t "std_logic"
3895o 3
3896suid 3,0
3897)
3898)
3899uid 346,0
3900)
3901*126 (LeafLogPort
3902port (LogicalPort
3903lang 10
3904m 4
3905decl (Decl
3906n "shifting"
3907t "std_logic"
3908o 4
3909suid 4,0
3910)
3911)
3912uid 348,0
3913)
3914*127 (LeafLogPort
3915port (LogicalPort
3916lang 10
3917m 4
3918decl (Decl
3919n "ready"
3920t "std_logic"
3921o 5
3922suid 5,0
3923)
3924)
3925uid 350,0
3926)
3927*128 (LeafLogPort
3928port (LogicalPort
3929lang 10
3930m 4
3931decl (Decl
3932n "offset"
3933t "std_logic_vector"
3934b "(7 DOWNTO 0)"
3935o 6
3936suid 6,0
3937)
3938)
3939uid 352,0
3940)
3941*129 (LeafLogPort
3942port (LogicalPort
3943lang 10
3944m 4
3945decl (Decl
3946n "clk"
3947t "std_logic"
3948o 7
3949suid 7,0
3950)
3951)
3952uid 354,0
3953)
3954*130 (LeafLogPort
3955port (LogicalPort
3956lang 10
3957m 4
3958decl (Decl
3959n "PSDONE"
3960t "std_logic"
3961o 8
3962suid 8,0
3963)
3964)
3965uid 356,0
3966)
3967*131 (LeafLogPort
3968port (LogicalPort
3969lang 10
3970m 4
3971decl (Decl
3972n "LOCKED"
3973t "std_logic"
3974o 9
3975suid 9,0
3976)
3977)
3978uid 358,0
3979)
3980*132 (LeafLogPort
3981port (LogicalPort
3982lang 10
3983m 4
3984decl (Decl
3985n "shift_phase"
3986t "std_logic"
3987o 10
3988suid 10,0
3989)
3990)
3991uid 360,0
3992)
3993*133 (LeafLogPort
3994port (LogicalPort
3995lang 10
3996m 4
3997decl (Decl
3998n "direction"
3999t "std_logic"
4000o 11
4001suid 11,0
4002)
4003)
4004uid 362,0
4005)
4006*134 (LeafLogPort
4007port (LogicalPort
4008lang 10
4009m 4
4010decl (Decl
4011n "rst"
4012t "std_logic"
4013o 12
4014suid 12,0
4015)
4016)
4017uid 364,0
4018)
4019*135 (LeafLogPort
4020port (LogicalPort
4021lang 10
4022m 4
4023decl (Decl
4024n "reset_DCM"
4025t "std_logic"
4026o 13
4027suid 13,0
4028)
4029)
4030uid 366,0
4031)
4032]
4033)
4034pdm (PhysicalDM
4035displayShortBounds 1
4036editShortBounds 1
4037uid 394,0
4038optionalChildren [
4039*136 (Sheet
4040sheetRow (SheetRow
4041headerVa (MVa
4042cellColor "49152,49152,49152"
4043fontColor "0,0,0"
4044font "Tahoma,10,0"
4045)
4046cellVa (MVa
4047cellColor "65535,65535,65535"
4048fontColor "0,0,0"
4049font "Tahoma,10,0"
4050)
4051groupVa (MVa
4052cellColor "39936,56832,65280"
4053fontColor "0,0,0"
4054font "Tahoma,10,0"
4055)
4056emptyMRCItem *137 (MRCItem
4057litem &110
4058pos 13
4059dimension 20
4060)
4061uid 396,0
4062optionalChildren [
4063*138 (MRCItem
4064litem &111
4065pos 0
4066dimension 20
4067uid 397,0
4068)
4069*139 (MRCItem
4070litem &112
4071pos 1
4072dimension 23
4073uid 398,0
4074)
4075*140 (MRCItem
4076litem &113
4077pos 2
4078hidden 1
4079dimension 20
4080uid 399,0
4081)
4082*141 (MRCItem
4083litem &123
4084pos 0
4085dimension 20
4086uid 343,0
4087)
4088*142 (MRCItem
4089litem &124
4090pos 1
4091dimension 20
4092uid 345,0
4093)
4094*143 (MRCItem
4095litem &125
4096pos 2
4097dimension 20
4098uid 347,0
4099)
4100*144 (MRCItem
4101litem &126
4102pos 3
4103dimension 20
4104uid 349,0
4105)
4106*145 (MRCItem
4107litem &127
4108pos 4
4109dimension 20
4110uid 351,0
4111)
4112*146 (MRCItem
4113litem &128
4114pos 5
4115dimension 20
4116uid 353,0
4117)
4118*147 (MRCItem
4119litem &129
4120pos 6
4121dimension 20
4122uid 355,0
4123)
4124*148 (MRCItem
4125litem &130
4126pos 7
4127dimension 20
4128uid 357,0
4129)
4130*149 (MRCItem
4131litem &131
4132pos 8
4133dimension 20
4134uid 359,0
4135)
4136*150 (MRCItem
4137litem &132
4138pos 9
4139dimension 20
4140uid 361,0
4141)
4142*151 (MRCItem
4143litem &133
4144pos 10
4145dimension 20
4146uid 363,0
4147)
4148*152 (MRCItem
4149litem &134
4150pos 11
4151dimension 20
4152uid 365,0
4153)
4154*153 (MRCItem
4155litem &135
4156pos 12
4157dimension 20
4158uid 367,0
4159)
4160]
4161)
4162sheetCol (SheetCol
4163propVa (MVa
4164cellColor "0,49152,49152"
4165fontColor "0,0,0"
4166font "Tahoma,10,0"
4167textAngle 90
4168)
4169uid 400,0
4170optionalChildren [
4171*154 (MRCItem
4172litem &114
4173pos 0
4174dimension 20
4175uid 401,0
4176)
4177*155 (MRCItem
4178litem &116
4179pos 1
4180dimension 50
4181uid 402,0
4182)
4183*156 (MRCItem
4184litem &117
4185pos 2
4186dimension 100
4187uid 403,0
4188)
4189*157 (MRCItem
4190litem &118
4191pos 3
4192dimension 50
4193uid 404,0
4194)
4195*158 (MRCItem
4196litem &119
4197pos 4
4198dimension 100
4199uid 405,0
4200)
4201*159 (MRCItem
4202litem &120
4203pos 5
4204dimension 100
4205uid 406,0
4206)
4207*160 (MRCItem
4208litem &121
4209pos 6
4210dimension 50
4211uid 407,0
4212)
4213*161 (MRCItem
4214litem &122
4215pos 7
4216dimension 80
4217uid 408,0
4218)
4219]
4220)
4221fixedCol 4
4222fixedRow 2
4223name "Ports"
4224uid 395,0
4225vaOverrides [
4226]
4227)
4228]
4229)
4230uid 380,0
4231)
4232genericsCommonDM (CommonDM
4233ldm (LogicalDM
4234emptyRow *162 (LEmptyRow
4235)
4236uid 410,0
4237optionalChildren [
4238*163 (RefLabelRowHdr
4239)
4240*164 (TitleRowHdr
4241)
4242*165 (FilterRowHdr
4243)
4244*166 (RefLabelColHdr
4245tm "RefLabelColHdrMgr"
4246)
4247*167 (RowExpandColHdr
4248tm "RowExpandColHdrMgr"
4249)
4250*168 (GroupColHdr
4251tm "GroupColHdrMgr"
4252)
4253*169 (NameColHdr
4254tm "GenericNameColHdrMgr"
4255)
4256*170 (TypeColHdr
4257tm "GenericTypeColHdrMgr"
4258)
4259*171 (InitColHdr
4260tm "GenericValueColHdrMgr"
4261)
4262*172 (PragmaColHdr
4263tm "GenericPragmaColHdrMgr"
4264)
4265*173 (EolColHdr
4266tm "GenericEolColHdrMgr"
4267)
4268]
4269)
4270pdm (PhysicalDM
4271displayShortBounds 1
4272editShortBounds 1
4273uid 422,0
4274optionalChildren [
4275*174 (Sheet
4276sheetRow (SheetRow
4277headerVa (MVa
4278cellColor "49152,49152,49152"
4279fontColor "0,0,0"
4280font "Tahoma,10,0"
4281)
4282cellVa (MVa
4283cellColor "65535,65535,65535"
4284fontColor "0,0,0"
4285font "Tahoma,10,0"
4286)
4287groupVa (MVa
4288cellColor "39936,56832,65280"
4289fontColor "0,0,0"
4290font "Tahoma,10,0"
4291)
4292emptyMRCItem *175 (MRCItem
4293litem &162
4294pos 0
4295dimension 20
4296)
4297uid 424,0
4298optionalChildren [
4299*176 (MRCItem
4300litem &163
4301pos 0
4302dimension 20
4303uid 425,0
4304)
4305*177 (MRCItem
4306litem &164
4307pos 1
4308dimension 23
4309uid 426,0
4310)
4311*178 (MRCItem
4312litem &165
4313pos 2
4314hidden 1
4315dimension 20
4316uid 427,0
4317)
4318]
4319)
4320sheetCol (SheetCol
4321propVa (MVa
4322cellColor "0,49152,49152"
4323fontColor "0,0,0"
4324font "Tahoma,10,0"
4325textAngle 90
4326)
4327uid 428,0
4328optionalChildren [
4329*179 (MRCItem
4330litem &166
4331pos 0
4332dimension 20
4333uid 429,0
4334)
4335*180 (MRCItem
4336litem &168
4337pos 1
4338dimension 50
4339uid 430,0
4340)
4341*181 (MRCItem
4342litem &169
4343pos 2
4344dimension 100
4345uid 431,0
4346)
4347*182 (MRCItem
4348litem &170
4349pos 3
4350dimension 100
4351uid 432,0
4352)
4353*183 (MRCItem
4354litem &171
4355pos 4
4356dimension 50
4357uid 433,0
4358)
4359*184 (MRCItem
4360litem &172
4361pos 5
4362dimension 50
4363uid 434,0
4364)
4365*185 (MRCItem
4366litem &173
4367pos 6
4368dimension 80
4369uid 435,0
4370)
4371]
4372)
4373fixedCol 3
4374fixedRow 2
4375name "Ports"
4376uid 423,0
4377vaOverrides [
4378]
4379)
4380]
4381)
4382uid 409,0
4383type 1
4384)
4385activeModelName "BlockDiag"
4386)
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