DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
dmPackageRefs [
(DmPackageRef
library "ieee"
unitName "std_logic_1164"
itemName "ALL"
)
(DmPackageRef
library "IEEE"
unitName "NUMERIC_STD"
itemName "ALL"
)
(DmPackageRef
library "FACT_FAD_lib"
unitName "fad_definitions"
itemName "ALL"
)
(DmPackageRef
library "ieee"
unitName "std_logic_unsigned"
)
(DmPackageRef
library "ieee"
unitName "std_logic_arith"
)
]
instances [
(Instance
name "U_0"
duLibraryName "FACT_FAD_lib"
duName "phase_shifter"
elements [
]
mwi 0
uid 64,0
)
(Instance
name "U_1"
duLibraryName "FACT_FAD_TB_lib"
duName "phase_shifter_tester"
elements [
]
mwi 0
uid 190,0
)
(Instance
name "U_2"
duLibraryName "FACT_FAD_TB_lib"
duName "clock_generator"
elements [
(GiElement
name "clock_period"
type "time"
value "20 ns"
)
(GiElement
name "reset_time"
type "time"
value "50 ns"
)
]
mwi 0
uid 525,0
)
]
libraryRefs [
"ieee"
"FACT_FAD_lib"
]
)
version "29.1"
appVersion "2009.2 (Build 10)"
noEmbeddedEditors 1
model (BlockDiag
VExpander (VariableExpander
vvMap [
(vvPair
variable "HDLDir"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hdl"
)
(vvPair
variable "HDSDir"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\phase_shifter_tb\\struct.bd.info"
)
(vvPair
variable "SideDataUserDir"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\phase_shifter_tb\\struct.bd.user"
)
(vvPair
variable "SourceDir"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "struct"
)
(vvPair
variable "config"
value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\phase_shifter_tb"
)
(vvPair
variable "d_logical"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\phase_shifter_tb"
)
(vvPair
variable "date"
value "14.02.2011"
)
(vvPair
variable "day"
value "Mo"
)
(vvPair
variable "day_long"
value "Montag"
)
(vvPair
variable "dd"
value "14"
)
(vvPair
variable "entity_name"
value "phase_shifter_tb"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "struct.bd"
)
(vvPair
variable "f_logical"
value "struct.bd"
)
(vvPair
variable "f_noext"
value "struct"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "E5B-LABOR6"
)
(vvPair
variable "language"
value "VHDL"
)
(vvPair
variable "library"
value "FACT_FAD_TB_lib"
)
(vvPair
variable "library_downstream_ISEPARInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
)
(vvPair
variable "library_downstream_ImpactInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/work"
)
(vvPair
variable "library_downstream_XSTDataPrep"
value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
)
(vvPair
variable "mm"
value "02"
)
(vvPair
variable "module_name"
value "phase_shifter_tb"
)
(vvPair
variable "month"
value "Feb"
)
(vvPair
variable "month_long"
value "Februar"
)
(vvPair
variable "p"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\phase_shifter_tb\\struct.bd"
)
(vvPair
variable "p_logical"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\phase_shifter_tb\\struct.bd"
)
(vvPair
variable "package_name"
value "<Undefined Variable>"
)
(vvPair
variable "project_name"
value "FACT_FAD"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "C:\\modeltech_6.6a\\win32"
)
(vvPair
variable "task_NC-SimPath"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
)
(vvPair
variable "task_QuestaSimPath"
value "<TBD>"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "this_ext"
value "bd"
)
(vvPair
variable "this_file"
value "struct"
)
(vvPair
variable "this_file_logical"
value "struct"
)
(vvPair
variable "time"
value "13:39:02"
)
(vvPair
variable "unit"
value "phase_shifter_tb"
)
(vvPair
variable "user"
value "dneise"
)
(vvPair
variable "version"
value "2009.2 (Build 10)"
)
(vvPair
variable "view"
value "struct"
)
(vvPair
variable "year"
value "2011"
)
(vvPair
variable "yy"
value "11"
)
]
)
LanguageMgr "VhdlLangMgr"
uid 379,0
optionalChildren [
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uid 64,0
optionalChildren [
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uid 9,0
ps "OnEdgeStrategy"
shape (Triangle
uid 10,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "10250,8625,11000,9375"
)
tg (CPTG
uid 11,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 12,0
va (VaSet
)
xt "12000,8500,13900,9500"
st "CLK"
blo "12000,9300"
)
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_logic"
preAdd 0
posAdd 0
o 1
suid 1,0
)
)
)
*3 (CptPort
uid 13,0
ps "OnEdgeStrategy"
shape (Triangle
uid 14,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "26000,8625,26750,9375"
)
tg (CPTG
uid 15,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 16,0
va (VaSet
)
xt "22100,8500,25000,9500"
st "PSCLK"
ju 2
blo "25000,9300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "PSCLK"
t "std_logic"
prec "-- interface to: clock_generator_variable_PS_struct.vhd"
preAdd 0
posAdd 0
o 3
suid 2,0
)
)
)
*4 (CptPort
uid 17,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "26000,10625,26750,11375"
)
tg (CPTG
uid 19,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 20,0
va (VaSet
)
xt "22500,10500,25000,11500"
st "PSEN"
ju 2
blo "25000,11300"
)
t (Text
uid 74,0
va (VaSet
)
xt "23800,11500,25000,12500"
st "'0'"
ju 2
blo "25000,12300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "PSEN"
t "std_logic"
preAdd 0
posAdd 0
o 4
suid 3,0
i "'0'"
)
)
)
*5 (CptPort
uid 21,0
ps "OnEdgeStrategy"
shape (Triangle
uid 22,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "26000,12625,26750,13375"
)
tg (CPTG
uid 23,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 24,0
va (VaSet
)
xt "20500,12500,25000,13500"
st "PSINCDEC"
ju 2
blo "25000,13300"
)
t (Text
uid 75,0
va (VaSet
)
xt "23800,13500,25000,14500"
st "'1'"
ju 2
blo "25000,14300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "PSINCDEC"
t "std_logic"
eolc "-- default is 'incrementing'"
preAdd 0
posAdd 0
o 5
suid 4,0
i "'1'"
)
)
)
*6 (CptPort
uid 25,0
ps "OnEdgeStrategy"
shape (Triangle
uid 26,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "10250,10625,11000,11375"
)
tg (CPTG
uid 27,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 28,0
va (VaSet
)
xt "12000,10500,15700,11500"
st "PSDONE"
blo "12000,11300"
)
)
thePort (LogicalPort
decl (Decl
n "PSDONE"
t "std_logic"
eolc "-- will pulse once, if phase shifting was done."
preAdd 0
posAdd 0
o 6
suid 5,0
)
)
)
*7 (CptPort
uid 29,0
ps "OnEdgeStrategy"
shape (Triangle
uid 30,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "10250,12625,11000,13375"
)
tg (CPTG
uid 31,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 32,0
va (VaSet
)
xt "12000,12500,15600,13500"
st "LOCKED"
blo "12000,13300"
)
)
thePort (LogicalPort
decl (Decl
n "LOCKED"
t "std_logic"
eolc "-- when is this going high?"
preAdd 0
posAdd 0
o 7
suid 6,0
)
)
)
*8 (CptPort
uid 33,0
ps "OnEdgeStrategy"
shape (Triangle
uid 34,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "10250,16625,11000,17375"
)
tg (CPTG
uid 35,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 36,0
va (VaSet
)
xt "12000,16500,16600,17500"
st "shift_phase"
blo "12000,17300"
)
)
thePort (LogicalPort
decl (Decl
n "shift_phase"
t "std_logic"
prec "-- interface to: w5300_modul.vhd"
preAdd 0
posAdd 0
o 8
suid 8,0
)
)
)
*9 (CptPort
uid 37,0
ps "OnEdgeStrategy"
shape (Triangle
uid 38,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "10250,18625,11000,19375"
)
tg (CPTG
uid 39,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 40,0
va (VaSet
)
xt "12000,18500,15300,19500"
st "direction"
blo "12000,19300"
)
)
thePort (LogicalPort
decl (Decl
n "direction"
t "std_logic"
eolc "-- corresponds to 'PSINCDEC'"
preAdd 0
posAdd 0
o 9
suid 9,0
)
)
)
*10 (CptPort
uid 41,0
ps "OnEdgeStrategy"
shape (Triangle
uid 42,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "26000,14625,26750,15375"
)
tg (CPTG
uid 43,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 44,0
va (VaSet
)
xt "22100,14500,25000,15500"
st "shifting"
ju 2
blo "25000,15300"
)
t (Text
uid 76,0
va (VaSet
)
xt "23800,15500,25000,16500"
st "'0'"
ju 2
blo "25000,16300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "shifting"
t "std_logic"
prec "-- status:"
preAdd 0
posAdd 0
o 11
suid 10,0
i "'0'"
)
)
)
*11 (CptPort
uid 45,0
ps "OnEdgeStrategy"
shape (Triangle
uid 46,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "26000,16625,26750,17375"
)
tg (CPTG
uid 47,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 48,0
va (VaSet
)
xt "22800,16500,25000,17500"
st "ready"
ju 2
blo "25000,17300"
)
t (Text
uid 77,0
va (VaSet
)
xt "23800,17500,25000,18500"
st "'0'"
ju 2
blo "25000,18300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ready"
t "std_logic"
preAdd 0
posAdd 0
o 12
suid 11,0
i "'0'"
)
)
)
*12 (CptPort
uid 49,0
ps "OnEdgeStrategy"
shape (Triangle
uid 50,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "26000,18625,26750,19375"
)
tg (CPTG
uid 51,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 52,0
va (VaSet
)
xt "20200,18500,25000,19500"
st "offset : (7:0)"
ju 2
blo "25000,19300"
)
t (Text
uid 78,0
va (VaSet
)
xt "18100,19500,25000,20500"
st "(OTHERS => '0')"
ju 2
blo "25000,20300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "offset"
t "std_logic_vector"
b "(7 DOWNTO 0)"
preAdd 0
posAdd 0
o 13
suid 12,0
i "(OTHERS => '0')"
)
)
)
*13 (CptPort
uid 53,0
ps "OnEdgeStrategy"
shape (Triangle
uid 54,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "10250,19625,11000,20375"
)
tg (CPTG
uid 55,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 56,0
va (VaSet
)
xt "12000,19500,13300,20500"
st "rst"
blo "12000,20300"
)
t (Text
uid 79,0
va (VaSet
)
xt "12000,20500,13200,21500"
st "'0'"
blo "12000,21300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "rst"
t "std_logic"
eolc "--asynch in of DCM"
posAdd 0
o 2
suid 15,0
i "'0'"
)
)
)
*14 (CptPort
uid 57,0
ps "OnEdgeStrategy"
shape (Triangle
uid 58,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "10250,21625,11000,22375"
)
tg (CPTG
uid 59,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 60,0
va (VaSet
)
xt "12000,21500,16400,22500"
st "reset_DCM"
blo "12000,22300"
)
)
thePort (LogicalPort
decl (Decl
n "reset_DCM"
t "std_logic"
eolc "-- asynch in: orders us, to reset the DCM"
posAdd 0
o 10
suid 17,0
)
)
)
]
shape (Rectangle
uid 65,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "11000,7000,26000,25000"
)
oxt "50000,7000,65000,25000"
ttg (MlTextGroup
uid 66,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*15 (Text
uid 67,0
va (VaSet
font "Arial,8,1"
)
xt "15700,15000,21900,16000"
st "FACT_FAD_lib"
blo "15700,15800"
tm "BdLibraryNameMgr"
)
*16 (Text
uid 68,0
va (VaSet
font "Arial,8,1"
)
xt "15700,16000,21500,17000"
st "phase_shifter"
blo "15700,16800"
tm "CptNameMgr"
)
*17 (Text
uid 69,0
va (VaSet
font "Arial,8,1"
)
xt "15700,17000,17500,18000"
st "U_0"
blo "15700,17800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 70,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 71,0
text (MLText
uid 72,0
va (VaSet
font "Courier New,8,0"
)
xt "11000,6000,11000,6000"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 73,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "11250,23250,12750,24750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
sIVOD 1
)
archType 1
archFileType "UNKNOWN"
)
*18 (Net
uid 80,0
lang 10
decl (Decl
n "PSCLK"
t "std_logic"
o 1
suid 1,0
)
declText (MLText
uid 81,0
va (VaSet
font "Courier New,8,0"
)
xt "13000,-12200,29500,-11400"
st "SIGNAL PSCLK       : std_logic
"
)
)
*19 (Net
uid 88,0
lang 10
decl (Decl
n "PSEN"
t "std_logic"
o 2
suid 2,0
)
declText (MLText
uid 89,0
va (VaSet
font "Courier New,8,0"
)
xt "13000,-10600,29500,-9800"
st "SIGNAL PSEN        : std_logic
"
)
)
*20 (Net
uid 97,0
lang 10
decl (Decl
n "PSINCDEC"
t "std_logic"
o 3
suid 3,0
)
declText (MLText
uid 98,0
va (VaSet
font "Courier New,8,0"
)
xt "13000,-9800,29500,-9000"
st "SIGNAL PSINCDEC    : std_logic
"
)
)
*21 (Net
uid 106,0
lang 10
decl (Decl
n "shifting"
t "std_logic"
o 4
suid 4,0
)
declText (MLText
uid 107,0
va (VaSet
font "Courier New,8,0"
)
xt "13000,-3400,29500,-2600"
st "SIGNAL shifting    : std_logic
"
)
)
*22 (Net
uid 115,0
lang 10
decl (Decl
n "ready"
t "std_logic"
o 5
suid 5,0
)
declText (MLText
uid 116,0
va (VaSet
font "Courier New,8,0"
)
xt "13000,-6600,29500,-5800"
st "SIGNAL ready       : std_logic
"
)
)
*23 (Net
uid 124,0
lang 10
decl (Decl
n "offset"
t "std_logic_vector"
b "(7 DOWNTO 0)"
o 6
suid 6,0
)
declText (MLText
uid 125,0
va (VaSet
font "Courier New,8,0"
)
xt "13000,-7400,39500,-6600"
st "SIGNAL offset      : std_logic_vector(7 DOWNTO 0)
"
)
)
*24 (Net
uid 133,0
lang 10
decl (Decl
n "clk"
t "std_logic"
o 7
suid 7,0
)
declText (MLText
uid 134,0
va (VaSet
font "Courier New,8,0"
)
xt "13000,-9000,29500,-8200"
st "SIGNAL clk         : std_logic
"
)
)
*25 (Net
uid 141,0
lang 10
decl (Decl
n "PSDONE"
t "std_logic"
o 8
suid 8,0
)
declText (MLText
uid 142,0
va (VaSet
font "Courier New,8,0"
)
xt "13000,-11400,29500,-10600"
st "SIGNAL PSDONE      : std_logic
"
)
)
*26 (Net
uid 149,0
lang 10
decl (Decl
n "LOCKED"
t "std_logic"
o 9
suid 9,0
)
declText (MLText
uid 150,0
va (VaSet
font "Courier New,8,0"
)
xt "13000,-13000,29500,-12200"
st "SIGNAL LOCKED      : std_logic
"
)
)
*27 (Net
uid 157,0
lang 10
decl (Decl
n "shift_phase"
t "std_logic"
o 10
suid 10,0
)
declText (MLText
uid 158,0
va (VaSet
font "Courier New,8,0"
)
xt "13000,-4200,29500,-3400"
st "SIGNAL shift_phase : std_logic
"
)
)
*28 (Net
uid 165,0
lang 10
decl (Decl
n "direction"
t "std_logic"
o 11
suid 11,0
)
declText (MLText
uid 166,0
va (VaSet
font "Courier New,8,0"
)
xt "13000,-8200,29500,-7400"
st "SIGNAL direction   : std_logic
"
)
)
*29 (Net
uid 173,0
lang 10
decl (Decl
n "rst"
t "std_logic"
o 12
suid 12,0
)
declText (MLText
uid 174,0
va (VaSet
font "Courier New,8,0"
)
xt "13000,-5000,29500,-4200"
st "SIGNAL rst         : std_logic
"
)
)
*30 (Net
uid 182,0
lang 10
decl (Decl
n "reset_DCM"
t "std_logic"
o 13
suid 13,0
)
declText (MLText
uid 183,0
va (VaSet
font "Courier New,8,0"
)
xt "13000,-5800,29500,-5000"
st "SIGNAL reset_DCM   : std_logic
"
)
)
*31 (Blk
uid 190,0
shape (Rectangle
uid 191,0
va (VaSet
vasetType 1
fg "39936,56832,65280"
lineColor "0,0,32768"
lineWidth 2
)
xt "54000,9000,69000,27000"
)
oxt "87000,18000,102000,36000"
ttg (MlTextGroup
uid 192,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*32 (Text
uid 193,0
va (VaSet
font "Arial,8,1"
)
xt "57650,16500,65350,17500"
st "FACT_FAD_TB_lib"
blo "57650,17300"
tm "BdLibraryNameMgr"
)
*33 (Text
uid 194,0
va (VaSet
font "Arial,8,1"
)
xt "57650,17500,66350,18500"
st "phase_shifter_tester"
blo "57650,18300"
tm "BlkNameMgr"
)
*34 (Text
uid 195,0
va (VaSet
font "Arial,8,1"
)
xt "57650,18500,59450,19500"
st "U_1"
blo "57650,19300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 196,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 197,0
text (MLText
uid 198,0
va (VaSet
font "Courier New,8,0"
)
xt "57650,26500,57650,26500"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 199,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "54250,25250,55750,26750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
blkPorts [
"clk"
"PSCLK"
"PSEN"
"PSINCDEC"
"offset"
"ready"
"rst"
"shifting"
"LOCKED"
"PSDONE"
"direction"
"reset_DCM"
"shift_phase"
]
)
*35 (Grouping
uid 310,0
optionalChildren [
*36 (CommentText
uid 312,0
shape (Rectangle
uid 313,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "36000,59000,53000,60000"
)
oxt "18000,70000,35000,71000"
text (MLText
uid 314,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "36200,59000,45800,60000"
st "
by %user on %dd %month %year
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
titleBlock 1
)
*37 (CommentText
uid 315,0
shape (Rectangle
uid 316,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "53000,55000,57000,56000"
)
oxt "35000,66000,39000,67000"
text (MLText
uid 317,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "53200,55000,56200,56000"
st "
Project:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*38 (CommentText
uid 318,0
shape (Rectangle
uid 319,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "36000,57000,53000,58000"
)
oxt "18000,68000,35000,69000"
text (MLText
uid 320,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "36200,57000,46200,58000"
st "
<enter diagram title here>
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
titleBlock 1
)
*39 (CommentText
uid 321,0
shape (Rectangle
uid 322,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "32000,57000,36000,58000"
)
oxt "14000,68000,18000,69000"
text (MLText
uid 323,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "32200,57000,34300,58000"
st "
Title:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*40 (CommentText
uid 324,0
shape (Rectangle
uid 325,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "53000,56000,73000,60000"
)
oxt "35000,67000,55000,71000"
text (MLText
uid 326,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "53200,56200,62400,57200"
st "
<enter comments here>
"
tm "CommentText"
wrapOption 3
visibleHeight 4000
visibleWidth 20000
)
ignorePrefs 1
titleBlock 1
)
*41 (CommentText
uid 327,0
shape (Rectangle
uid 328,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "57000,55000,73000,56000"
)
oxt "39000,66000,55000,67000"
text (MLText
uid 329,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "57200,55000,61700,56000"
st "
%project_name
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 16000
)
position 1
ignorePrefs 1
titleBlock 1
)
*42 (CommentText
uid 330,0
shape (Rectangle
uid 331,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "32000,55000,53000,57000"
)
oxt "14000,66000,35000,68000"
text (MLText
uid 332,0
va (VaSet
fg "32768,0,0"
)
xt "39150,55500,45850,56500"
st "
<company name>
"
ju 0
tm "CommentText"
wrapOption 3
visibleHeight 2000
visibleWidth 21000
)
position 1
ignorePrefs 1
titleBlock 1
)
*43 (CommentText
uid 333,0
shape (Rectangle
uid 334,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "32000,58000,36000,59000"
)
oxt "14000,69000,18000,70000"
text (MLText
uid 335,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "32200,58000,34300,59000"
st "
Path:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*44 (CommentText
uid 336,0
shape (Rectangle
uid 337,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "32000,59000,36000,60000"
)
oxt "14000,70000,18000,71000"
text (MLText
uid 338,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "32200,59000,34900,60000"
st "
Edited:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*45 (CommentText
uid 339,0
shape (Rectangle
uid 340,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "36000,58000,53000,59000"
)
oxt "18000,69000,35000,70000"
text (MLText
uid 341,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "36200,58000,51900,59000"
st "
%library/%unit/%view
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
titleBlock 1
)
]
shape (GroupingShape
uid 311,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
lineWidth 2
)
xt "32000,55000,73000,60000"
)
oxt "14000,66000,55000,71000"
)
*46 (SaComponent
uid 525,0
optionalChildren [
*47 (CptPort
uid 514,0
ps "OnEdgeStrategy"
shape (Triangle
uid 515,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "12000,38625,12750,39375"
)
tg (CPTG
uid 516,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 517,0
va (VaSet
)
xt "9700,38500,11000,39500"
st "clk"
ju 2
blo "11000,39300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "clk"
t "std_logic"
preAdd 0
posAdd 0
o 1
suid 1,0
i "'0'"
)
)
)
*48 (CptPort
uid 518,0
ps "OnEdgeStrategy"
shape (Triangle
uid 519,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "12000,39625,12750,40375"
)
tg (CPTG
uid 520,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 521,0
va (VaSet
)
xt "9700,39500,11000,40500"
st "rst"
ju 2
blo "11000,40300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "rst"
t "std_logic"
preAdd 0
posAdd 0
o 2
suid 2,0
i "'0'"
)
)
)
]
shape (Rectangle
uid 526,0
va (VaSet
vasetType 1
fg "0,49152,49152"
lineColor "0,0,50000"
lineWidth 2
)
xt "4000,38000,12000,42000"
)
oxt "22000,15000,30000,19000"
ttg (MlTextGroup
uid 527,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*49 (Text
uid 528,0
va (VaSet
font "Arial,8,1"
)
xt "4150,42000,11850,43000"
st "FACT_FAD_TB_lib"
blo "4150,42800"
tm "BdLibraryNameMgr"
)
*50 (Text
uid 529,0
va (VaSet
font "Arial,8,1"
)
xt "4150,43000,10850,44000"
st "clock_generator"
blo "4150,43800"
tm "CptNameMgr"
)
*51 (Text
uid 530,0
va (VaSet
font "Arial,8,1"
)
xt "4150,44000,5950,45000"
st "U_2"
blo "4150,44800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 531,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 532,0
text (MLText
uid 533,0
va (VaSet
font "Courier New,8,0"
)
xt "1000,35400,19500,37000"
st "clock_period = 20 ns    ( time )  
reset_time   = 50 ns    ( time )  "
)
header ""
)
elements [
(GiElement
name "clock_period"
type "time"
value "20 ns"
)
(GiElement
name "reset_time"
type "time"
value "50 ns"
)
]
)
viewicon (ZoomableIcon
uid 534,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "4250,40250,5750,41750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*52 (Wire
uid 82,0
shape (OrthoPolyLine
uid 83,0
va (VaSet
vasetType 3
)
xt "26750,9000,36000,9000"
pts [
"26750,9000"
"36000,9000"
]
)
start &3
sat 32
eat 16
st 0
sf 1
tg (WTG
uid 86,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 87,0
va (VaSet
)
xt "28000,8000,30900,9000"
st "PSCLK"
blo "28000,8800"
tm "WireNameMgr"
)
)
on &18
)
*53 (Wire
uid 90,0
shape (OrthoPolyLine
uid 91,0
va (VaSet
vasetType 3
)
xt "26750,11000,36000,11000"
pts [
"26750,11000"
"36000,11000"
]
)
start &4
sat 32
eat 16
st 0
sf 1
tg (WTG
uid 94,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 95,0
va (VaSet
)
xt "28000,10000,30500,11000"
st "PSEN"
blo "28000,10800"
tm "WireNameMgr"
)
)
on &19
)
*54 (Wire
uid 99,0
shape (OrthoPolyLine
uid 100,0
va (VaSet
vasetType 3
)
xt "26750,13000,36000,13000"
pts [
"26750,13000"
"36000,13000"
]
)
start &5
sat 32
eat 16
st 0
sf 1
tg (WTG
uid 103,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 104,0
va (VaSet
)
xt "28000,12000,32500,13000"
st "PSINCDEC"
blo "28000,12800"
tm "WireNameMgr"
)
)
on &20
)
*55 (Wire
uid 108,0
shape (OrthoPolyLine
uid 109,0
va (VaSet
vasetType 3
)
xt "26750,15000,36000,15000"
pts [
"26750,15000"
"36000,15000"
]
)
start &10
sat 32
eat 16
st 0
sf 1
tg (WTG
uid 112,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 113,0
va (VaSet
)
xt "28000,14000,30900,15000"
st "shifting"
blo "28000,14800"
tm "WireNameMgr"
)
)
on &21
)
*56 (Wire
uid 117,0
shape (OrthoPolyLine
uid 118,0
va (VaSet
vasetType 3
)
xt "26750,17000,36000,17000"
pts [
"26750,17000"
"36000,17000"
]
)
start &11
sat 32
eat 16
st 0
sf 1
tg (WTG
uid 121,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 122,0
va (VaSet
)
xt "28000,16000,30200,17000"
st "ready"
blo "28000,16800"
tm "WireNameMgr"
)
)
on &22
)
*57 (Wire
uid 126,0
shape (OrthoPolyLine
uid 127,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "26750,19000,36000,19000"
pts [
"26750,19000"
"36000,19000"
]
)
start &12
sat 32
eat 16
sty 1
st 0
sf 1
tg (WTG
uid 130,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 131,0
va (VaSet
)
xt "28000,18000,32800,19000"
st "offset : (7:0)"
blo "28000,18800"
tm "WireNameMgr"
)
)
on &23
)
*58 (Wire
uid 135,0
shape (OrthoPolyLine
uid 136,0
va (VaSet
vasetType 3
)
xt "1000,9000,19000,39000"
pts [
"12750,39000"
"19000,39000"
"19000,33000"
"1000,33000"
"1000,9000"
"10250,9000"
]
)
start &47
end &2
sat 32
eat 32
st 0
sf 1
tg (WTG
uid 139,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 140,0
va (VaSet
)
xt "14750,38000,16050,39000"
st "clk"
blo "14750,38800"
tm "WireNameMgr"
)
)
on &24
)
*59 (Wire
uid 143,0
shape (OrthoPolyLine
uid 144,0
va (VaSet
vasetType 3
)
xt "3000,11000,10250,11000"
pts [
"3000,11000"
"10250,11000"
]
)
end &6
sat 16
eat 32
st 0
sf 1
tg (WTG
uid 147,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 148,0
va (VaSet
)
xt "4000,10000,7700,11000"
st "PSDONE"
blo "4000,10800"
tm "WireNameMgr"
)
)
on &25
)
*60 (Wire
uid 151,0
shape (OrthoPolyLine
uid 152,0
va (VaSet
vasetType 3
)
xt "3000,13000,10250,13000"
pts [
"3000,13000"
"10250,13000"
]
)
end &7
sat 16
eat 32
st 0
sf 1
tg (WTG
uid 155,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 156,0
va (VaSet
)
xt "4000,12000,7600,13000"
st "LOCKED"
blo "4000,12800"
tm "WireNameMgr"
)
)
on &26
)
*61 (Wire
uid 159,0
shape (OrthoPolyLine
uid 160,0
va (VaSet
vasetType 3
)
xt "3000,17000,10250,17000"
pts [
"3000,17000"
"10250,17000"
]
)
end &8
sat 16
eat 32
st 0
sf 1
tg (WTG
uid 163,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 164,0
va (VaSet
)
xt "4000,16000,8600,17000"
st "shift_phase"
blo "4000,16800"
tm "WireNameMgr"
)
)
on &27
)
*62 (Wire
uid 167,0
shape (OrthoPolyLine
uid 168,0
va (VaSet
vasetType 3
)
xt "3000,19000,10250,19000"
pts [
"3000,19000"
"10250,19000"
]
)
end &9
sat 16
eat 32
st 0
sf 1
tg (WTG
uid 171,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 172,0
va (VaSet
)
xt "4000,18000,7300,19000"
st "direction"
blo "4000,18800"
tm "WireNameMgr"
)
)
on &28
)
*63 (Wire
uid 175,0
shape (OrthoPolyLine
uid 176,0
va (VaSet
vasetType 3
)
xt "3000,20000,10250,20000"
pts [
"10250,20000"
"3000,20000"
]
)
start &13
sat 32
eat 16
st 0
sf 1
tg (WTG
uid 179,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 180,0
va (VaSet
)
xt "4000,19000,5300,20000"
st "rst"
blo "4000,19800"
tm "WireNameMgr"
)
)
on &29
)
*64 (Wire
uid 184,0
shape (OrthoPolyLine
uid 185,0
va (VaSet
vasetType 3
)
xt "3000,22000,10250,22000"
pts [
"3000,22000"
"10250,22000"
]
)
end &14
sat 16
eat 32
st 0
sf 1
tg (WTG
uid 188,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 189,0
va (VaSet
)
xt "4000,21000,8400,22000"
st "reset_DCM"
blo "4000,21800"
tm "WireNameMgr"
)
)
on &30
)
*65 (Wire
uid 200,0
shape (OrthoPolyLine
uid 201,0
va (VaSet
vasetType 3
)
xt "46000,19000,54000,19000"
pts [
"46000,19000"
"54000,19000"
]
)
end &31
sat 16
eat 2
st 0
sf 1
tg (WTG
uid 206,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 207,0
va (VaSet
)
xt "47000,18000,51600,19000"
st "shift_phase"
blo "47000,18800"
tm "WireNameMgr"
)
)
on &27
)
*66 (Wire
uid 208,0
shape (OrthoPolyLine
uid 209,0
va (VaSet
vasetType 3
)
xt "46000,21000,54000,21000"
pts [
"46000,21000"
"54000,21000"
]
)
end &31
sat 16
eat 2
st 0
sf 1
tg (WTG
uid 214,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 215,0
va (VaSet
)
xt "47000,20000,50300,21000"
st "direction"
blo "47000,20800"
tm "WireNameMgr"
)
)
on &28
)
*67 (Wire
uid 216,0
shape (OrthoPolyLine
uid 217,0
va (VaSet
vasetType 3
)
xt "46000,22000,54000,22000"
pts [
"54000,22000"
"46000,22000"
]
)
start &31
sat 1
eat 16
st 0
sf 1
tg (WTG
uid 222,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 223,0
va (VaSet
)
xt "47000,21000,48300,22000"
st "rst"
blo "47000,21800"
tm "WireNameMgr"
)
)
on &29
)
*68 (Wire
uid 225,0
shape (OrthoPolyLine
uid 226,0
va (VaSet
vasetType 3
)
xt "46000,13000,54000,13000"
pts [
"46000,13000"
"54000,13000"
]
)
end &31
sat 16
eat 2
st 0
sf 1
tg (WTG
uid 231,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 232,0
va (VaSet
)
xt "47000,12000,50700,13000"
st "PSDONE"
blo "47000,12800"
tm "WireNameMgr"
)
)
on &25
)
*69 (Wire
uid 233,0
shape (OrthoPolyLine
uid 234,0
va (VaSet
vasetType 3
)
xt "46000,24000,54000,24000"
pts [
"46000,24000"
"54000,24000"
]
)
end &31
sat 16
eat 2
st 0
sf 1
tg (WTG
uid 239,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 240,0
va (VaSet
)
xt "47000,23000,51400,24000"
st "reset_DCM"
blo "47000,23800"
tm "WireNameMgr"
)
)
on &30
)
*70 (Wire
uid 241,0
shape (OrthoPolyLine
uid 242,0
va (VaSet
vasetType 3
)
xt "69000,17000,79000,17000"
pts [
"69000,17000"
"79000,17000"
]
)
start &31
sat 1
eat 16
st 0
sf 1
tg (WTG
uid 247,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 248,0
va (VaSet
)
xt "70000,16000,72900,17000"
st "shifting"
blo "70000,16800"
tm "WireNameMgr"
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)
on &21
)
*71 (Wire
uid 250,0
shape (OrthoPolyLine
uid 251,0
va (VaSet
vasetType 3
)
xt "69000,19000,79000,19000"
pts [
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]
)
start &31
sat 1
eat 16
st 0
sf 1
tg (WTG
uid 256,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 257,0
va (VaSet
)
xt "70000,18000,72200,19000"
st "ready"
blo "70000,18800"
tm "WireNameMgr"
)
)
on &22
)
*72 (Wire
uid 259,0
shape (OrthoPolyLine
uid 260,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "69000,21000,79000,21000"
pts [
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]
)
start &31
sat 1
eat 16
sty 1
st 0
sf 1
tg (WTG
uid 265,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
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va (VaSet
)
xt "71000,20000,75800,21000"
st "offset : (7:0)"
blo "71000,20800"
tm "WireNameMgr"
)
)
on &23
)
*73 (Wire
uid 276,0
shape (OrthoPolyLine
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va (VaSet
vasetType 3
)
xt "46000,15000,54000,15000"
pts [
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]
)
end &31
sat 16
eat 2
st 0
sf 1
tg (WTG
uid 282,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 283,0
va (VaSet
)
xt "47000,14000,50600,15000"
st "LOCKED"
blo "47000,14800"
tm "WireNameMgr"
)
)
on &26
)
*74 (Wire
uid 284,0
shape (OrthoPolyLine
uid 285,0
va (VaSet
vasetType 3
)
xt "69000,11000,79000,11000"
pts [
"69000,11000"
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]
)
start &31
sat 1
eat 16
st 0
sf 1
tg (WTG
uid 290,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 291,0
va (VaSet
)
xt "70000,10000,72900,11000"
st "PSCLK"
blo "70000,10800"
tm "WireNameMgr"
)
)
on &18
)
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uid 292,0
shape (OrthoPolyLine
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va (VaSet
vasetType 3
)
xt "69000,13000,79000,13000"
pts [
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]
)
start &31
sat 1
eat 16
st 0
sf 1
tg (WTG
uid 298,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 299,0
va (VaSet
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xt "70000,12000,72500,13000"
st "PSEN"
blo "70000,12800"
tm "WireNameMgr"
)
)
on &19
)
*76 (Wire
uid 301,0
shape (OrthoPolyLine
uid 302,0
va (VaSet
vasetType 3
)
xt "69000,15000,79000,15000"
pts [
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]
)
start &31
sat 1
eat 16
st 0
sf 1
tg (WTG
uid 307,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 308,0
va (VaSet
)
xt "70000,14000,74500,15000"
st "PSINCDEC"
blo "70000,14800"
tm "WireNameMgr"
)
)
on &20
)
*77 (Wire
uid 535,0
shape (OrthoPolyLine
uid 536,0
va (VaSet
vasetType 3
)
xt "44000,25000,54000,25000"
pts [
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]
)
end &31
sat 16
eat 1
st 0
sf 1
si 0
tg (WTG
uid 541,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 542,0
va (VaSet
)
xt "46000,24000,47300,25000"
st "clk"
blo "46000,24800"
tm "WireNameMgr"
)
)
on &24
)
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isActive 1
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xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
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blo "0,800"
)
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va (VaSet
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USE ieee.std_logic_1164.ALL;
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USE FACT_FAD_lib.fad_definitions.ALL;
USE ieee.std_logic_unsigned.all;
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tm "PackageList"
)
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stg "VerticalLayoutStrategy"
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)
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blo "20000,1800"
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va (VaSet
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xt "20000,2000,27500,4000"
st "`resetall
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tm "BdCompilerDirectivesTextMgr"
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blo "20000,5800"
)
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uid 378,0
va (VaSet
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xt "20000,6000,20000,6000"
tm "BdCompilerDirectivesTextMgr"
)
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text (MLText
va (VaSet
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xt "200,200,2000,1200"
st "
Text
"
tm "CommentText"
wrapOption 3
visibleHeight 4600
visibleWidth 14600
)
)
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shape (RectFrame
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xt "0,0,20000,20000"
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text (Text
va (VaSet
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xt "1000,1000,3800,2000"
st "Panel0"
blo "1000,1800"
tm "PanelText"
)
)
)
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)
xt "0,0,8000,10000"
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ttg (MlTextGroup
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stg "VerticalLayoutStrategy"
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va (VaSet
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xt "2200,3500,5800,4500"
st "<library>"
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tm "BdLibraryNameMgr"
)
*89 (Text
va (VaSet
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)
xt "2200,4500,5600,5500"
st "<block>"
blo "2200,5300"
tm "BlkNameMgr"
)
*90 (Text
va (VaSet
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xt "2200,5500,4000,6500"
st "U_0"
blo "2200,6300"
tm "InstanceNameMgr"
)
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ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
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va (VaSet
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)
xt "2200,13500,2200,13500"
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header ""
)
elements [
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va (VaSet
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fg "49152,49152,49152"
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xt "0,0,1500,1500"
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iconMaskName "UnknownFile.msk"
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)
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xt "0,0,8000,10000"
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ttg (MlTextGroup
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stg "VerticalLayoutStrategy"
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va (VaSet
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xt "550,3500,3450,4500"
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va (VaSet
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xt "550,4500,7450,5500"
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blo "550,5300"
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va (VaSet
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)
xt "550,5500,2350,6500"
st "U_0"
blo "550,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
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xt "-6450,1500,-6450,1500"
)
header ""
)
elements [
]
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portVis (PortSigDisplay
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
visOptions (mwParamsVisibilityOptions
)
)
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shape (Rectangle
va (VaSet
vasetType 1
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lineWidth 2
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xt "0,0,8000,10000"
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ttg (MlTextGroup
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stg "VerticalLayoutStrategy"
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tm "BdLibraryNameMgr"
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tm "CptNameMgr"
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va (VaSet
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tm "InstanceNameMgr"
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matrix (Matrix
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xt "-6100,1500,-6100,1500"
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header ""
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elements [
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va (VaSet
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fg "49152,49152,49152"
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xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
portVis (PortSigDisplay
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archFileType "UNKNOWN"
)
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)
xt "0,0,8000,10000"
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ttg (MlTextGroup
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stg "VerticalLayoutStrategy"
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xt "500,3500,3400,4500"
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va (VaSet
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xt "500,4500,7500,5500"
st "VhdlComponent"
blo "500,5300"
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va (VaSet
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xt "500,5500,2300,6500"
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blo "500,6300"
tm "InstanceNameMgr"
)
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)
ga (GenericAssociation
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text (MLText
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xt "-6500,1500,-6500,1500"
)
header ""
)
elements [
]
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portVis (PortSigDisplay
)
entityPath ""
archName ""
archPath ""
)
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va (VaSet
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lineColor "0,32896,0"
lineWidth 2
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xt "-450,0,8450,10000"
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ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
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xt "50,3500,2950,4500"
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va (VaSet
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blo "50,5300"
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va (VaSet
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tm "InstanceNameMgr"
)
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)
ga (GenericAssociation
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matrix (Matrix
text (MLText
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xt "-6950,1500,-6950,1500"
)
header ""
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elements [
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)
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defaultHdlText (HdlText
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va (VaSet
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lineWidth 2
)
xt "0,0,8000,10000"
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ttg (MlTextGroup
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stg "VerticalLayoutStrategy"
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)
xt "3150,4000,4850,5000"
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blo "3150,4800"
tm "HdlTextNameMgr"
)
*104 (Text
va (VaSet
font "Arial,8,1"
)
xt "3150,5000,3950,6000"
st "1"
blo "3150,5800"
tm "HdlTextNumberMgr"
)
]
)
viewicon (ZoomableIcon
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va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
)
defaultEmbeddedText (EmbeddedText
commentText (CommentText
ps "CenterOffsetStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,18000,5000"
)
text (MLText
va (VaSet
)
xt "200,200,2000,1200"
st "
Text
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 4600
visibleWidth 17600
)
)
)
defaultGlobalConnector (GlobalConnector
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va (VaSet
vasetType 1
fg "65535,65535,0"
)
xt "-1000,-1000,1000,1000"
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)
name (Text
va (VaSet
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xt "-500,-500,500,500"
st "G"
blo "-500,300"
)
)
defaultRipper (Ripper
ps "OnConnectorStrategy"
shape (Line2D
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]
va (VaSet
vasetType 1
)
xt "0,0,1000,1000"
)
)
defaultBdJunction (BdJunction
ps "OnConnectorStrategy"
shape (Circle
va (VaSet
vasetType 1
)
xt "-400,-400,400,400"
radius 400
)
)
defaultPortIoIn (PortIoIn
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
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sl 0
ro 270
xt "-2000,-375,-500,375"
)
(Line
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ro 270
xt "-500,0,0,0"
pts [
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)
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)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
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xt "-1375,-1000,-1375,-1000"
ju 2
blo "-1375,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoOut (PortIoOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
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sl 0
ro 270
xt "500,-375,2000,375"
)
(Line
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ro 270
xt "0,0,500,0"
pts [
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)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
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)
xt "625,-1000,625,-1000"
blo "625,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoInOut (PortIoInOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
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sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
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"500,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
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xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultPortIoBuffer (PortIoBuffer
shape (CompositeShape
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
)
optionalChildren [
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sl 0
xt "500,-375,2000,375"
)
(Line
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xt "0,0,500,0"
pts [
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)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
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)
defaultSignal (Wire
shape (OrthoPolyLine
va (VaSet
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)
pts [
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ss 0
es 0
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
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xt "0,0,1900,1000"
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blo "0,800"
tm "WireNameMgr"
)
)
)
defaultBus (Wire
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va (VaSet
vasetType 3
lineWidth 2
)
pts [
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ss 0
es 0
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,0,2400,1000"
st "dbus0"
blo "0,800"
tm "WireNameMgr"
)
)
)
defaultBundle (Bundle
shape (OrthoPolyLine
va (VaSet
vasetType 3
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lineWidth 2
)
pts [
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)
ss 0
es 0
sat 32
eat 32
textGroup (BiTextGroup
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stg "VerticalLayoutStrategy"
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blo "0,800"
tm "BundleNameMgr"
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bundleNet &0
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lineColor "0,0,32768"
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xt "0,0,10000,12000"
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portMapText (BiTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
first (MLText
va (VaSet
)
)
second (MLText
va (VaSet
)
tm "PortMapTextMgr"
)
)
)
defaultGenFrame (Frame
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vasetType 1
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lineColor "26368,26368,26368"
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lineWidth 3
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xt "0,0,20000,20000"
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title (TextAssociate
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text (MLText
va (VaSet
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xt "0,-1100,12600,-100"
st "g0: FOR i IN 0 TO n GENERATE"
tm "FrameTitleTextMgr"
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seqNum (FrameSequenceNumber
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fg "65535,65535,65535"
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xt "50,50,1250,1450"
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num (Text
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st "1"
blo "250,1050"
tm "FrameSeqNumMgr"
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stg "VerticalLayoutStrategy"
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*106 (MLText
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tm "BdFrameDeclTextMgr"
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xt "50,50,1250,1450"
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num (Text
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xt "250,250,1050,1250"
st "1"
blo "250,1050"
tm "FrameSeqNumMgr"
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decls (MlTextGroup
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stg "VerticalLayoutStrategy"
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font "Arial,8,1"
)
xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*108 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
)
]
)
style 3
)
defaultSaCptPort (CptPort
ps "OnEdgeStrategy"
shape (Triangle
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1800,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultSaCptPortBuffer (CptPort
ps "OnEdgeStrategy"
shape (Diamond
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1800,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
m 3
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultDeclText (MLText
va (VaSet
font "Courier New,8,0"
)
)
archDeclarativeBlock (BdArchDeclBlock
uid 1,0
stg "BdArchDeclBlockLS"
declLabel (Text
uid 2,0
va (VaSet
font "Arial,8,1"
)
xt "11000,-16000,16400,-15000"
st "Declarations"
blo "11000,-15200"
)
portLabel (Text
uid 3,0
va (VaSet
font "Arial,8,1"
)
xt "11000,-15000,13700,-14000"
st "Ports:"
blo "11000,-14200"
)
preUserLabel (Text
uid 4,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "11000,-16000,14800,-15000"
st "Pre User:"
blo "11000,-15200"
)
preUserText (MLText
uid 5,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "11000,-16000,11000,-16000"
tm "BdDeclarativeTextMgr"
)
diagSignalLabel (Text
uid 6,0
va (VaSet
font "Arial,8,1"
)
xt "11000,-14000,18100,-13000"
st "Diagram Signals:"
blo "11000,-13200"
)
postUserLabel (Text
uid 7,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "11000,-16000,15700,-15000"
st "Post User:"
blo "11000,-15200"
)
postUserText (MLText
uid 8,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "11000,-16000,11000,-16000"
tm "BdDeclarativeTextMgr"
)
)
commonDM (CommonDM
ldm (LogicalDM
suid 14,0
usingSuid 1
emptyRow *109 (LEmptyRow
)
uid 381,0
optionalChildren [
*110 (RefLabelRowHdr
)
*111 (TitleRowHdr
)
*112 (FilterRowHdr
)
*113 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*114 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*115 (GroupColHdr
tm "GroupColHdrMgr"
)
*116 (NameColHdr
tm "BlockDiagramNameColHdrMgr"
)
*117 (ModeColHdr
tm "BlockDiagramModeColHdrMgr"
)
*118 (TypeColHdr
tm "BlockDiagramTypeColHdrMgr"
)
*119 (BoundsColHdr
tm "BlockDiagramBoundsColHdrMgr"
)
*120 (InitColHdr
tm "BlockDiagramInitColHdrMgr"
)
*121 (EolColHdr
tm "BlockDiagramEolColHdrMgr"
)
*122 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "PSCLK"
t "std_logic"
o 1
suid 1,0
)
)
uid 342,0
)
*123 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "PSEN"
t "std_logic"
o 2
suid 2,0
)
)
uid 344,0
)
*124 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "PSINCDEC"
t "std_logic"
o 3
suid 3,0
)
)
uid 346,0
)
*125 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "shifting"
t "std_logic"
o 4
suid 4,0
)
)
uid 348,0
)
*126 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "ready"
t "std_logic"
o 5
suid 5,0
)
)
uid 350,0
)
*127 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "offset"
t "std_logic_vector"
b "(7 DOWNTO 0)"
o 6
suid 6,0
)
)
uid 352,0
)
*128 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "clk"
t "std_logic"
o 7
suid 7,0
)
)
uid 354,0
)
*129 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "PSDONE"
t "std_logic"
o 8
suid 8,0
)
)
uid 356,0
)
*130 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "LOCKED"
t "std_logic"
o 9
suid 9,0
)
)
uid 358,0
)
*131 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "shift_phase"
t "std_logic"
o 10
suid 10,0
)
)
uid 360,0
)
*132 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "direction"
t "std_logic"
o 11
suid 11,0
)
)
uid 362,0
)
*133 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "rst"
t "std_logic"
o 12
suid 12,0
)
)
uid 364,0
)
*134 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "reset_DCM"
t "std_logic"
o 13
suid 13,0
)
)
uid 366,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 394,0
optionalChildren [
*135 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *136 (MRCItem
litem &109
pos 13
dimension 20
)
uid 396,0
optionalChildren [
*137 (MRCItem
litem &110
pos 0
dimension 20
uid 397,0
)
*138 (MRCItem
litem &111
pos 1
dimension 23
uid 398,0
)
*139 (MRCItem
litem &112
pos 2
hidden 1
dimension 20
uid 399,0
)
*140 (MRCItem
litem &122
pos 0
dimension 20
uid 343,0
)
*141 (MRCItem
litem &123
pos 1
dimension 20
uid 345,0
)
*142 (MRCItem
litem &124
pos 2
dimension 20
uid 347,0
)
*143 (MRCItem
litem &125
pos 3
dimension 20
uid 349,0
)
*144 (MRCItem
litem &126
pos 4
dimension 20
uid 351,0
)
*145 (MRCItem
litem &127
pos 5
dimension 20
uid 353,0
)
*146 (MRCItem
litem &128
pos 6
dimension 20
uid 355,0
)
*147 (MRCItem
litem &129
pos 7
dimension 20
uid 357,0
)
*148 (MRCItem
litem &130
pos 8
dimension 20
uid 359,0
)
*149 (MRCItem
litem &131
pos 9
dimension 20
uid 361,0
)
*150 (MRCItem
litem &132
pos 10
dimension 20
uid 363,0
)
*151 (MRCItem
litem &133
pos 11
dimension 20
uid 365,0
)
*152 (MRCItem
litem &134
pos 12
dimension 20
uid 367,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 400,0
optionalChildren [
*153 (MRCItem
litem &113
pos 0
dimension 20
uid 401,0
)
*154 (MRCItem
litem &115
pos 1
dimension 50
uid 402,0
)
*155 (MRCItem
litem &116
pos 2
dimension 100
uid 403,0
)
*156 (MRCItem
litem &117
pos 3
dimension 50
uid 404,0
)
*157 (MRCItem
litem &118
pos 4
dimension 100
uid 405,0
)
*158 (MRCItem
litem &119
pos 5
dimension 100
uid 406,0
)
*159 (MRCItem
litem &120
pos 6
dimension 50
uid 407,0
)
*160 (MRCItem
litem &121
pos 7
dimension 80
uid 408,0
)
]
)
fixedCol 4
fixedRow 2
name "Ports"
uid 395,0
vaOverrides [
]
)
]
)
uid 380,0
)
genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *161 (LEmptyRow
)
uid 410,0
optionalChildren [
*162 (RefLabelRowHdr
)
*163 (TitleRowHdr
)
*164 (FilterRowHdr
)
*165 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*166 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*167 (GroupColHdr
tm "GroupColHdrMgr"
)
*168 (NameColHdr
tm "GenericNameColHdrMgr"
)
*169 (TypeColHdr
tm "GenericTypeColHdrMgr"
)
*170 (InitColHdr
tm "GenericValueColHdrMgr"
)
*171 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
)
*172 (EolColHdr
tm "GenericEolColHdrMgr"
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 422,0
optionalChildren [
*173 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *174 (MRCItem
litem &161
pos 0
dimension 20
)
uid 424,0
optionalChildren [
*175 (MRCItem
litem &162
pos 0
dimension 20
uid 425,0
)
*176 (MRCItem
litem &163
pos 1
dimension 23
uid 426,0
)
*177 (MRCItem
litem &164
pos 2
hidden 1
dimension 20
uid 427,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 428,0
optionalChildren [
*178 (MRCItem
litem &165
pos 0
dimension 20
uid 429,0
)
*179 (MRCItem
litem &167
pos 1
dimension 50
uid 430,0
)
*180 (MRCItem
litem &168
pos 2
dimension 100
uid 431,0
)
*181 (MRCItem
litem &169
pos 3
dimension 100
uid 432,0
)
*182 (MRCItem
litem &170
pos 4
dimension 50
uid 433,0
)
*183 (MRCItem
litem &171
pos 5
dimension 50
uid 434,0
)
*184 (MRCItem
litem &172
pos 6
dimension 80
uid 435,0
)
]
)
fixedCol 3
fixedRow 2
name "Ports"
uid 423,0
vaOverrides [
]
)
]
)
uid 409,0
type 1
)
activeModelName "BlockDiag"
)