source: firmware/FAD/FACT_FAD_TB_lib/hds/phase_shifter_tb/struct.bd@ 18342

Last change on this file since 18342 was 11755, checked in by neise, 13 years ago
reinit of this svn repos .... it was all too messy deleted the old folders and restarted with FACT_FAD_lib only. (well and the testbenches)
File size: 55.4 KB
Line 
1DocumentHdrVersion "1.1"
2Header (DocumentHdr
3version 2
4dmPackageRefs [
5(DmPackageRef
6library "ieee"
7unitName "std_logic_1164"
8itemName "ALL"
9)
10(DmPackageRef
11library "IEEE"
12unitName "NUMERIC_STD"
13itemName "ALL"
14)
15(DmPackageRef
16library "FACT_FAD_lib"
17unitName "fad_definitions"
18itemName "ALL"
19)
20(DmPackageRef
21library "ieee"
22unitName "std_logic_unsigned"
23)
24(DmPackageRef
25library "ieee"
26unitName "std_logic_arith"
27)
28]
29instances [
30(Instance
31name "U_0"
32duLibraryName "FACT_FAD_lib"
33duName "phase_shifter"
34elements [
35]
36mwi 0
37uid 64,0
38)
39(Instance
40name "U_1"
41duLibraryName "FACT_FAD_TB_lib"
42duName "phase_shifter_tester"
43elements [
44]
45mwi 0
46uid 190,0
47)
48(Instance
49name "U_2"
50duLibraryName "FACT_FAD_TB_lib"
51duName "clock_generator"
52elements [
53(GiElement
54name "clock_period"
55type "time"
56value "20 ns"
57)
58(GiElement
59name "reset_time"
60type "time"
61value "50 ns"
62)
63]
64mwi 0
65uid 525,0
66)
67]
68libraryRefs [
69"ieee"
70"FACT_FAD_lib"
71]
72)
73version "29.1"
74appVersion "2009.2 (Build 10)"
75noEmbeddedEditors 1
76model (BlockDiag
77VExpander (VariableExpander
78vvMap [
79(vvPair
80variable "HDLDir"
81value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hdl"
82)
83(vvPair
84variable "HDSDir"
85value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
86)
87(vvPair
88variable "SideDataDesignDir"
89value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\phase_shifter_tb\\struct.bd.info"
90)
91(vvPair
92variable "SideDataUserDir"
93value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\phase_shifter_tb\\struct.bd.user"
94)
95(vvPair
96variable "SourceDir"
97value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
98)
99(vvPair
100variable "appl"
101value "HDL Designer"
102)
103(vvPair
104variable "arch_name"
105value "struct"
106)
107(vvPair
108variable "config"
109value "%(unit)_%(view)_config"
110)
111(vvPair
112variable "d"
113value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\phase_shifter_tb"
114)
115(vvPair
116variable "d_logical"
117value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\phase_shifter_tb"
118)
119(vvPair
120variable "date"
121value "14.02.2011"
122)
123(vvPair
124variable "day"
125value "Mo"
126)
127(vvPair
128variable "day_long"
129value "Montag"
130)
131(vvPair
132variable "dd"
133value "14"
134)
135(vvPair
136variable "entity_name"
137value "phase_shifter_tb"
138)
139(vvPair
140variable "ext"
141value "<TBD>"
142)
143(vvPair
144variable "f"
145value "struct.bd"
146)
147(vvPair
148variable "f_logical"
149value "struct.bd"
150)
151(vvPair
152variable "f_noext"
153value "struct"
154)
155(vvPair
156variable "group"
157value "UNKNOWN"
158)
159(vvPair
160variable "host"
161value "E5B-LABOR6"
162)
163(vvPair
164variable "language"
165value "VHDL"
166)
167(vvPair
168variable "library"
169value "FACT_FAD_TB_lib"
170)
171(vvPair
172variable "library_downstream_ISEPARInvoke"
173value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
174)
175(vvPair
176variable "library_downstream_ImpactInvoke"
177value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
178)
179(vvPair
180variable "library_downstream_ModelSimCompiler"
181value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/work"
182)
183(vvPair
184variable "library_downstream_XSTDataPrep"
185value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
186)
187(vvPair
188variable "mm"
189value "02"
190)
191(vvPair
192variable "module_name"
193value "phase_shifter_tb"
194)
195(vvPair
196variable "month"
197value "Feb"
198)
199(vvPair
200variable "month_long"
201value "Februar"
202)
203(vvPair
204variable "p"
205value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\phase_shifter_tb\\struct.bd"
206)
207(vvPair
208variable "p_logical"
209value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\phase_shifter_tb\\struct.bd"
210)
211(vvPair
212variable "package_name"
213value "<Undefined Variable>"
214)
215(vvPair
216variable "project_name"
217value "FACT_FAD"
218)
219(vvPair
220variable "series"
221value "HDL Designer Series"
222)
223(vvPair
224variable "task_DesignCompilerPath"
225value "<TBD>"
226)
227(vvPair
228variable "task_LeonardoPath"
229value "<TBD>"
230)
231(vvPair
232variable "task_ModelSimPath"
233value "C:\\modeltech_6.6a\\win32"
234)
235(vvPair
236variable "task_NC-SimPath"
237value "<TBD>"
238)
239(vvPair
240variable "task_PrecisionRTLPath"
241value "<TBD>"
242)
243(vvPair
244variable "task_QuestaSimPath"
245value "<TBD>"
246)
247(vvPair
248variable "task_VCSPath"
249value "<TBD>"
250)
251(vvPair
252variable "this_ext"
253value "bd"
254)
255(vvPair
256variable "this_file"
257value "struct"
258)
259(vvPair
260variable "this_file_logical"
261value "struct"
262)
263(vvPair
264variable "time"
265value "13:39:02"
266)
267(vvPair
268variable "unit"
269value "phase_shifter_tb"
270)
271(vvPair
272variable "user"
273value "dneise"
274)
275(vvPair
276variable "version"
277value "2009.2 (Build 10)"
278)
279(vvPair
280variable "view"
281value "struct"
282)
283(vvPair
284variable "year"
285value "2011"
286)
287(vvPair
288variable "yy"
289value "11"
290)
291]
292)
293LanguageMgr "VhdlLangMgr"
294uid 379,0
295optionalChildren [
296*1 (SaComponent
297uid 64,0
298optionalChildren [
299*2 (CptPort
300uid 9,0
301ps "OnEdgeStrategy"
302shape (Triangle
303uid 10,0
304ro 90
305va (VaSet
306vasetType 1
307fg "0,65535,0"
308)
309xt "10250,8625,11000,9375"
310)
311tg (CPTG
312uid 11,0
313ps "CptPortTextPlaceStrategy"
314stg "VerticalLayoutStrategy"
315f (Text
316uid 12,0
317va (VaSet
318)
319xt "12000,8500,13900,9500"
320st "CLK"
321blo "12000,9300"
322)
323)
324thePort (LogicalPort
325decl (Decl
326n "CLK"
327t "std_logic"
328preAdd 0
329posAdd 0
330o 1
331suid 1,0
332)
333)
334)
335*3 (CptPort
336uid 13,0
337ps "OnEdgeStrategy"
338shape (Triangle
339uid 14,0
340ro 90
341va (VaSet
342vasetType 1
343fg "0,65535,0"
344)
345xt "26000,8625,26750,9375"
346)
347tg (CPTG
348uid 15,0
349ps "CptPortTextPlaceStrategy"
350stg "RightVerticalLayoutStrategy"
351f (Text
352uid 16,0
353va (VaSet
354)
355xt "22100,8500,25000,9500"
356st "PSCLK"
357ju 2
358blo "25000,9300"
359)
360)
361thePort (LogicalPort
362m 1
363decl (Decl
364n "PSCLK"
365t "std_logic"
366prec "-- interface to: clock_generator_variable_PS_struct.vhd"
367preAdd 0
368posAdd 0
369o 3
370suid 2,0
371)
372)
373)
374*4 (CptPort
375uid 17,0
376ps "OnEdgeStrategy"
377shape (Triangle
378uid 18,0
379ro 90
380va (VaSet
381vasetType 1
382fg "0,65535,0"
383)
384xt "26000,10625,26750,11375"
385)
386tg (CPTG
387uid 19,0
388ps "CptPortTextPlaceStrategy"
389stg "RightVerticalLayoutStrategy"
390f (Text
391uid 20,0
392va (VaSet
393)
394xt "22500,10500,25000,11500"
395st "PSEN"
396ju 2
397blo "25000,11300"
398)
399t (Text
400uid 74,0
401va (VaSet
402)
403xt "23800,11500,25000,12500"
404st "'0'"
405ju 2
406blo "25000,12300"
407)
408)
409thePort (LogicalPort
410m 1
411decl (Decl
412n "PSEN"
413t "std_logic"
414preAdd 0
415posAdd 0
416o 4
417suid 3,0
418i "'0'"
419)
420)
421)
422*5 (CptPort
423uid 21,0
424ps "OnEdgeStrategy"
425shape (Triangle
426uid 22,0
427ro 90
428va (VaSet
429vasetType 1
430fg "0,65535,0"
431)
432xt "26000,12625,26750,13375"
433)
434tg (CPTG
435uid 23,0
436ps "CptPortTextPlaceStrategy"
437stg "RightVerticalLayoutStrategy"
438f (Text
439uid 24,0
440va (VaSet
441)
442xt "20500,12500,25000,13500"
443st "PSINCDEC"
444ju 2
445blo "25000,13300"
446)
447t (Text
448uid 75,0
449va (VaSet
450)
451xt "23800,13500,25000,14500"
452st "'1'"
453ju 2
454blo "25000,14300"
455)
456)
457thePort (LogicalPort
458m 1
459decl (Decl
460n "PSINCDEC"
461t "std_logic"
462eolc "-- default is 'incrementing'"
463preAdd 0
464posAdd 0
465o 5
466suid 4,0
467i "'1'"
468)
469)
470)
471*6 (CptPort
472uid 25,0
473ps "OnEdgeStrategy"
474shape (Triangle
475uid 26,0
476ro 90
477va (VaSet
478vasetType 1
479fg "0,65535,0"
480)
481xt "10250,10625,11000,11375"
482)
483tg (CPTG
484uid 27,0
485ps "CptPortTextPlaceStrategy"
486stg "VerticalLayoutStrategy"
487f (Text
488uid 28,0
489va (VaSet
490)
491xt "12000,10500,15700,11500"
492st "PSDONE"
493blo "12000,11300"
494)
495)
496thePort (LogicalPort
497decl (Decl
498n "PSDONE"
499t "std_logic"
500eolc "-- will pulse once, if phase shifting was done."
501preAdd 0
502posAdd 0
503o 6
504suid 5,0
505)
506)
507)
508*7 (CptPort
509uid 29,0
510ps "OnEdgeStrategy"
511shape (Triangle
512uid 30,0
513ro 90
514va (VaSet
515vasetType 1
516fg "0,65535,0"
517)
518xt "10250,12625,11000,13375"
519)
520tg (CPTG
521uid 31,0
522ps "CptPortTextPlaceStrategy"
523stg "VerticalLayoutStrategy"
524f (Text
525uid 32,0
526va (VaSet
527)
528xt "12000,12500,15600,13500"
529st "LOCKED"
530blo "12000,13300"
531)
532)
533thePort (LogicalPort
534decl (Decl
535n "LOCKED"
536t "std_logic"
537eolc "-- when is this going high?"
538preAdd 0
539posAdd 0
540o 7
541suid 6,0
542)
543)
544)
545*8 (CptPort
546uid 33,0
547ps "OnEdgeStrategy"
548shape (Triangle
549uid 34,0
550ro 90
551va (VaSet
552vasetType 1
553fg "0,65535,0"
554)
555xt "10250,16625,11000,17375"
556)
557tg (CPTG
558uid 35,0
559ps "CptPortTextPlaceStrategy"
560stg "VerticalLayoutStrategy"
561f (Text
562uid 36,0
563va (VaSet
564)
565xt "12000,16500,16600,17500"
566st "shift_phase"
567blo "12000,17300"
568)
569)
570thePort (LogicalPort
571decl (Decl
572n "shift_phase"
573t "std_logic"
574prec "-- interface to: w5300_modul.vhd"
575preAdd 0
576posAdd 0
577o 8
578suid 8,0
579)
580)
581)
582*9 (CptPort
583uid 37,0
584ps "OnEdgeStrategy"
585shape (Triangle
586uid 38,0
587ro 90
588va (VaSet
589vasetType 1
590fg "0,65535,0"
591)
592xt "10250,18625,11000,19375"
593)
594tg (CPTG
595uid 39,0
596ps "CptPortTextPlaceStrategy"
597stg "VerticalLayoutStrategy"
598f (Text
599uid 40,0
600va (VaSet
601)
602xt "12000,18500,15300,19500"
603st "direction"
604blo "12000,19300"
605)
606)
607thePort (LogicalPort
608decl (Decl
609n "direction"
610t "std_logic"
611eolc "-- corresponds to 'PSINCDEC'"
612preAdd 0
613posAdd 0
614o 9
615suid 9,0
616)
617)
618)
619*10 (CptPort
620uid 41,0
621ps "OnEdgeStrategy"
622shape (Triangle
623uid 42,0
624ro 90
625va (VaSet
626vasetType 1
627fg "0,65535,0"
628)
629xt "26000,14625,26750,15375"
630)
631tg (CPTG
632uid 43,0
633ps "CptPortTextPlaceStrategy"
634stg "RightVerticalLayoutStrategy"
635f (Text
636uid 44,0
637va (VaSet
638)
639xt "22100,14500,25000,15500"
640st "shifting"
641ju 2
642blo "25000,15300"
643)
644t (Text
645uid 76,0
646va (VaSet
647)
648xt "23800,15500,25000,16500"
649st "'0'"
650ju 2
651blo "25000,16300"
652)
653)
654thePort (LogicalPort
655m 1
656decl (Decl
657n "shifting"
658t "std_logic"
659prec "-- status:"
660preAdd 0
661posAdd 0
662o 11
663suid 10,0
664i "'0'"
665)
666)
667)
668*11 (CptPort
669uid 45,0
670ps "OnEdgeStrategy"
671shape (Triangle
672uid 46,0
673ro 90
674va (VaSet
675vasetType 1
676fg "0,65535,0"
677)
678xt "26000,16625,26750,17375"
679)
680tg (CPTG
681uid 47,0
682ps "CptPortTextPlaceStrategy"
683stg "RightVerticalLayoutStrategy"
684f (Text
685uid 48,0
686va (VaSet
687)
688xt "22800,16500,25000,17500"
689st "ready"
690ju 2
691blo "25000,17300"
692)
693t (Text
694uid 77,0
695va (VaSet
696)
697xt "23800,17500,25000,18500"
698st "'0'"
699ju 2
700blo "25000,18300"
701)
702)
703thePort (LogicalPort
704m 1
705decl (Decl
706n "ready"
707t "std_logic"
708preAdd 0
709posAdd 0
710o 12
711suid 11,0
712i "'0'"
713)
714)
715)
716*12 (CptPort
717uid 49,0
718ps "OnEdgeStrategy"
719shape (Triangle
720uid 50,0
721ro 90
722va (VaSet
723vasetType 1
724fg "0,65535,0"
725)
726xt "26000,18625,26750,19375"
727)
728tg (CPTG
729uid 51,0
730ps "CptPortTextPlaceStrategy"
731stg "RightVerticalLayoutStrategy"
732f (Text
733uid 52,0
734va (VaSet
735)
736xt "20200,18500,25000,19500"
737st "offset : (7:0)"
738ju 2
739blo "25000,19300"
740)
741t (Text
742uid 78,0
743va (VaSet
744)
745xt "18100,19500,25000,20500"
746st "(OTHERS => '0')"
747ju 2
748blo "25000,20300"
749)
750)
751thePort (LogicalPort
752m 1
753decl (Decl
754n "offset"
755t "std_logic_vector"
756b "(7 DOWNTO 0)"
757preAdd 0
758posAdd 0
759o 13
760suid 12,0
761i "(OTHERS => '0')"
762)
763)
764)
765*13 (CptPort
766uid 53,0
767ps "OnEdgeStrategy"
768shape (Triangle
769uid 54,0
770ro 270
771va (VaSet
772vasetType 1
773fg "0,65535,0"
774)
775xt "10250,19625,11000,20375"
776)
777tg (CPTG
778uid 55,0
779ps "CptPortTextPlaceStrategy"
780stg "VerticalLayoutStrategy"
781f (Text
782uid 56,0
783va (VaSet
784)
785xt "12000,19500,13300,20500"
786st "rst"
787blo "12000,20300"
788)
789t (Text
790uid 79,0
791va (VaSet
792)
793xt "12000,20500,13200,21500"
794st "'0'"
795blo "12000,21300"
796)
797)
798thePort (LogicalPort
799m 1
800decl (Decl
801n "rst"
802t "std_logic"
803eolc "--asynch in of DCM"
804posAdd 0
805o 2
806suid 15,0
807i "'0'"
808)
809)
810)
811*14 (CptPort
812uid 57,0
813ps "OnEdgeStrategy"
814shape (Triangle
815uid 58,0
816ro 90
817va (VaSet
818vasetType 1
819fg "0,65535,0"
820)
821xt "10250,21625,11000,22375"
822)
823tg (CPTG
824uid 59,0
825ps "CptPortTextPlaceStrategy"
826stg "VerticalLayoutStrategy"
827f (Text
828uid 60,0
829va (VaSet
830)
831xt "12000,21500,16400,22500"
832st "reset_DCM"
833blo "12000,22300"
834)
835)
836thePort (LogicalPort
837decl (Decl
838n "reset_DCM"
839t "std_logic"
840eolc "-- asynch in: orders us, to reset the DCM"
841posAdd 0
842o 10
843suid 17,0
844)
845)
846)
847]
848shape (Rectangle
849uid 65,0
850va (VaSet
851vasetType 1
852fg "0,65535,0"
853lineColor "0,32896,0"
854lineWidth 2
855)
856xt "11000,7000,26000,25000"
857)
858oxt "50000,7000,65000,25000"
859ttg (MlTextGroup
860uid 66,0
861ps "CenterOffsetStrategy"
862stg "VerticalLayoutStrategy"
863textVec [
864*15 (Text
865uid 67,0
866va (VaSet
867font "Arial,8,1"
868)
869xt "15700,15000,21900,16000"
870st "FACT_FAD_lib"
871blo "15700,15800"
872tm "BdLibraryNameMgr"
873)
874*16 (Text
875uid 68,0
876va (VaSet
877font "Arial,8,1"
878)
879xt "15700,16000,21500,17000"
880st "phase_shifter"
881blo "15700,16800"
882tm "CptNameMgr"
883)
884*17 (Text
885uid 69,0
886va (VaSet
887font "Arial,8,1"
888)
889xt "15700,17000,17500,18000"
890st "U_0"
891blo "15700,17800"
892tm "InstanceNameMgr"
893)
894]
895)
896ga (GenericAssociation
897uid 70,0
898ps "EdgeToEdgeStrategy"
899matrix (Matrix
900uid 71,0
901text (MLText
902uid 72,0
903va (VaSet
904font "Courier New,8,0"
905)
906xt "11000,6000,11000,6000"
907)
908header ""
909)
910elements [
911]
912)
913viewicon (ZoomableIcon
914uid 73,0
915sl 0
916va (VaSet
917vasetType 1
918fg "49152,49152,49152"
919)
920xt "11250,23250,12750,24750"
921iconName "VhdlFileViewIcon.png"
922iconMaskName "VhdlFileViewIcon.msk"
923ftype 10
924)
925ordering 1
926viewiconposition 0
927portVis (PortSigDisplay
928sIVOD 1
929)
930archType 1
931archFileType "UNKNOWN"
932)
933*18 (Net
934uid 80,0
935lang 10
936decl (Decl
937n "PSCLK"
938t "std_logic"
939o 1
940suid 1,0
941)
942declText (MLText
943uid 81,0
944va (VaSet
945font "Courier New,8,0"
946)
947xt "13000,-12200,29500,-11400"
948st "SIGNAL PSCLK : std_logic
949"
950)
951)
952*19 (Net
953uid 88,0
954lang 10
955decl (Decl
956n "PSEN"
957t "std_logic"
958o 2
959suid 2,0
960)
961declText (MLText
962uid 89,0
963va (VaSet
964font "Courier New,8,0"
965)
966xt "13000,-10600,29500,-9800"
967st "SIGNAL PSEN : std_logic
968"
969)
970)
971*20 (Net
972uid 97,0
973lang 10
974decl (Decl
975n "PSINCDEC"
976t "std_logic"
977o 3
978suid 3,0
979)
980declText (MLText
981uid 98,0
982va (VaSet
983font "Courier New,8,0"
984)
985xt "13000,-9800,29500,-9000"
986st "SIGNAL PSINCDEC : std_logic
987"
988)
989)
990*21 (Net
991uid 106,0
992lang 10
993decl (Decl
994n "shifting"
995t "std_logic"
996o 4
997suid 4,0
998)
999declText (MLText
1000uid 107,0
1001va (VaSet
1002font "Courier New,8,0"
1003)
1004xt "13000,-3400,29500,-2600"
1005st "SIGNAL shifting : std_logic
1006"
1007)
1008)
1009*22 (Net
1010uid 115,0
1011lang 10
1012decl (Decl
1013n "ready"
1014t "std_logic"
1015o 5
1016suid 5,0
1017)
1018declText (MLText
1019uid 116,0
1020va (VaSet
1021font "Courier New,8,0"
1022)
1023xt "13000,-6600,29500,-5800"
1024st "SIGNAL ready : std_logic
1025"
1026)
1027)
1028*23 (Net
1029uid 124,0
1030lang 10
1031decl (Decl
1032n "offset"
1033t "std_logic_vector"
1034b "(7 DOWNTO 0)"
1035o 6
1036suid 6,0
1037)
1038declText (MLText
1039uid 125,0
1040va (VaSet
1041font "Courier New,8,0"
1042)
1043xt "13000,-7400,39500,-6600"
1044st "SIGNAL offset : std_logic_vector(7 DOWNTO 0)
1045"
1046)
1047)
1048*24 (Net
1049uid 133,0
1050lang 10
1051decl (Decl
1052n "clk"
1053t "std_logic"
1054o 7
1055suid 7,0
1056)
1057declText (MLText
1058uid 134,0
1059va (VaSet
1060font "Courier New,8,0"
1061)
1062xt "13000,-9000,29500,-8200"
1063st "SIGNAL clk : std_logic
1064"
1065)
1066)
1067*25 (Net
1068uid 141,0
1069lang 10
1070decl (Decl
1071n "PSDONE"
1072t "std_logic"
1073o 8
1074suid 8,0
1075)
1076declText (MLText
1077uid 142,0
1078va (VaSet
1079font "Courier New,8,0"
1080)
1081xt "13000,-11400,29500,-10600"
1082st "SIGNAL PSDONE : std_logic
1083"
1084)
1085)
1086*26 (Net
1087uid 149,0
1088lang 10
1089decl (Decl
1090n "LOCKED"
1091t "std_logic"
1092o 9
1093suid 9,0
1094)
1095declText (MLText
1096uid 150,0
1097va (VaSet
1098font "Courier New,8,0"
1099)
1100xt "13000,-13000,29500,-12200"
1101st "SIGNAL LOCKED : std_logic
1102"
1103)
1104)
1105*27 (Net
1106uid 157,0
1107lang 10
1108decl (Decl
1109n "shift_phase"
1110t "std_logic"
1111o 10
1112suid 10,0
1113)
1114declText (MLText
1115uid 158,0
1116va (VaSet
1117font "Courier New,8,0"
1118)
1119xt "13000,-4200,29500,-3400"
1120st "SIGNAL shift_phase : std_logic
1121"
1122)
1123)
1124*28 (Net
1125uid 165,0
1126lang 10
1127decl (Decl
1128n "direction"
1129t "std_logic"
1130o 11
1131suid 11,0
1132)
1133declText (MLText
1134uid 166,0
1135va (VaSet
1136font "Courier New,8,0"
1137)
1138xt "13000,-8200,29500,-7400"
1139st "SIGNAL direction : std_logic
1140"
1141)
1142)
1143*29 (Net
1144uid 173,0
1145lang 10
1146decl (Decl
1147n "rst"
1148t "std_logic"
1149o 12
1150suid 12,0
1151)
1152declText (MLText
1153uid 174,0
1154va (VaSet
1155font "Courier New,8,0"
1156)
1157xt "13000,-5000,29500,-4200"
1158st "SIGNAL rst : std_logic
1159"
1160)
1161)
1162*30 (Net
1163uid 182,0
1164lang 10
1165decl (Decl
1166n "reset_DCM"
1167t "std_logic"
1168o 13
1169suid 13,0
1170)
1171declText (MLText
1172uid 183,0
1173va (VaSet
1174font "Courier New,8,0"
1175)
1176xt "13000,-5800,29500,-5000"
1177st "SIGNAL reset_DCM : std_logic
1178"
1179)
1180)
1181*31 (Blk
1182uid 190,0
1183shape (Rectangle
1184uid 191,0
1185va (VaSet
1186vasetType 1
1187fg "39936,56832,65280"
1188lineColor "0,0,32768"
1189lineWidth 2
1190)
1191xt "54000,9000,69000,27000"
1192)
1193oxt "87000,18000,102000,36000"
1194ttg (MlTextGroup
1195uid 192,0
1196ps "CenterOffsetStrategy"
1197stg "VerticalLayoutStrategy"
1198textVec [
1199*32 (Text
1200uid 193,0
1201va (VaSet
1202font "Arial,8,1"
1203)
1204xt "57650,16500,65350,17500"
1205st "FACT_FAD_TB_lib"
1206blo "57650,17300"
1207tm "BdLibraryNameMgr"
1208)
1209*33 (Text
1210uid 194,0
1211va (VaSet
1212font "Arial,8,1"
1213)
1214xt "57650,17500,66350,18500"
1215st "phase_shifter_tester"
1216blo "57650,18300"
1217tm "BlkNameMgr"
1218)
1219*34 (Text
1220uid 195,0
1221va (VaSet
1222font "Arial,8,1"
1223)
1224xt "57650,18500,59450,19500"
1225st "U_1"
1226blo "57650,19300"
1227tm "InstanceNameMgr"
1228)
1229]
1230)
1231ga (GenericAssociation
1232uid 196,0
1233ps "EdgeToEdgeStrategy"
1234matrix (Matrix
1235uid 197,0
1236text (MLText
1237uid 198,0
1238va (VaSet
1239font "Courier New,8,0"
1240)
1241xt "57650,26500,57650,26500"
1242)
1243header ""
1244)
1245elements [
1246]
1247)
1248viewicon (ZoomableIcon
1249uid 199,0
1250sl 0
1251va (VaSet
1252vasetType 1
1253fg "49152,49152,49152"
1254)
1255xt "54250,25250,55750,26750"
1256iconName "VhdlFileViewIcon.png"
1257iconMaskName "VhdlFileViewIcon.msk"
1258ftype 10
1259)
1260ordering 1
1261viewiconposition 0
1262blkPorts [
1263"clk"
1264"PSCLK"
1265"PSEN"
1266"PSINCDEC"
1267"offset"
1268"ready"
1269"rst"
1270"shifting"
1271"LOCKED"
1272"PSDONE"
1273"direction"
1274"reset_DCM"
1275"shift_phase"
1276]
1277)
1278*35 (Grouping
1279uid 310,0
1280optionalChildren [
1281*36 (CommentText
1282uid 312,0
1283shape (Rectangle
1284uid 313,0
1285sl 0
1286va (VaSet
1287vasetType 1
1288fg "65280,65280,46080"
1289)
1290xt "36000,59000,53000,60000"
1291)
1292oxt "18000,70000,35000,71000"
1293text (MLText
1294uid 314,0
1295va (VaSet
1296fg "0,0,32768"
1297bg "0,0,32768"
1298)
1299xt "36200,59000,45800,60000"
1300st "
1301by %user on %dd %month %year
1302"
1303tm "CommentText"
1304wrapOption 3
1305visibleHeight 1000
1306visibleWidth 17000
1307)
1308position 1
1309ignorePrefs 1
1310titleBlock 1
1311)
1312*37 (CommentText
1313uid 315,0
1314shape (Rectangle
1315uid 316,0
1316sl 0
1317va (VaSet
1318vasetType 1
1319fg "65280,65280,46080"
1320)
1321xt "53000,55000,57000,56000"
1322)
1323oxt "35000,66000,39000,67000"
1324text (MLText
1325uid 317,0
1326va (VaSet
1327fg "0,0,32768"
1328bg "0,0,32768"
1329)
1330xt "53200,55000,56200,56000"
1331st "
1332Project:
1333"
1334tm "CommentText"
1335wrapOption 3
1336visibleHeight 1000
1337visibleWidth 4000
1338)
1339position 1
1340ignorePrefs 1
1341titleBlock 1
1342)
1343*38 (CommentText
1344uid 318,0
1345shape (Rectangle
1346uid 319,0
1347sl 0
1348va (VaSet
1349vasetType 1
1350fg "65280,65280,46080"
1351)
1352xt "36000,57000,53000,58000"
1353)
1354oxt "18000,68000,35000,69000"
1355text (MLText
1356uid 320,0
1357va (VaSet
1358fg "0,0,32768"
1359bg "0,0,32768"
1360)
1361xt "36200,57000,46200,58000"
1362st "
1363<enter diagram title here>
1364"
1365tm "CommentText"
1366wrapOption 3
1367visibleHeight 1000
1368visibleWidth 17000
1369)
1370position 1
1371ignorePrefs 1
1372titleBlock 1
1373)
1374*39 (CommentText
1375uid 321,0
1376shape (Rectangle
1377uid 322,0
1378sl 0
1379va (VaSet
1380vasetType 1
1381fg "65280,65280,46080"
1382)
1383xt "32000,57000,36000,58000"
1384)
1385oxt "14000,68000,18000,69000"
1386text (MLText
1387uid 323,0
1388va (VaSet
1389fg "0,0,32768"
1390bg "0,0,32768"
1391)
1392xt "32200,57000,34300,58000"
1393st "
1394Title:
1395"
1396tm "CommentText"
1397wrapOption 3
1398visibleHeight 1000
1399visibleWidth 4000
1400)
1401position 1
1402ignorePrefs 1
1403titleBlock 1
1404)
1405*40 (CommentText
1406uid 324,0
1407shape (Rectangle
1408uid 325,0
1409sl 0
1410va (VaSet
1411vasetType 1
1412fg "65280,65280,46080"
1413)
1414xt "53000,56000,73000,60000"
1415)
1416oxt "35000,67000,55000,71000"
1417text (MLText
1418uid 326,0
1419va (VaSet
1420fg "0,0,32768"
1421bg "0,0,32768"
1422)
1423xt "53200,56200,62400,57200"
1424st "
1425<enter comments here>
1426"
1427tm "CommentText"
1428wrapOption 3
1429visibleHeight 4000
1430visibleWidth 20000
1431)
1432ignorePrefs 1
1433titleBlock 1
1434)
1435*41 (CommentText
1436uid 327,0
1437shape (Rectangle
1438uid 328,0
1439sl 0
1440va (VaSet
1441vasetType 1
1442fg "65280,65280,46080"
1443)
1444xt "57000,55000,73000,56000"
1445)
1446oxt "39000,66000,55000,67000"
1447text (MLText
1448uid 329,0
1449va (VaSet
1450fg "0,0,32768"
1451bg "0,0,32768"
1452)
1453xt "57200,55000,61700,56000"
1454st "
1455%project_name
1456"
1457tm "CommentText"
1458wrapOption 3
1459visibleHeight 1000
1460visibleWidth 16000
1461)
1462position 1
1463ignorePrefs 1
1464titleBlock 1
1465)
1466*42 (CommentText
1467uid 330,0
1468shape (Rectangle
1469uid 331,0
1470sl 0
1471va (VaSet
1472vasetType 1
1473fg "65280,65280,46080"
1474)
1475xt "32000,55000,53000,57000"
1476)
1477oxt "14000,66000,35000,68000"
1478text (MLText
1479uid 332,0
1480va (VaSet
1481fg "32768,0,0"
1482)
1483xt "39150,55500,45850,56500"
1484st "
1485<company name>
1486"
1487ju 0
1488tm "CommentText"
1489wrapOption 3
1490visibleHeight 2000
1491visibleWidth 21000
1492)
1493position 1
1494ignorePrefs 1
1495titleBlock 1
1496)
1497*43 (CommentText
1498uid 333,0
1499shape (Rectangle
1500uid 334,0
1501sl 0
1502va (VaSet
1503vasetType 1
1504fg "65280,65280,46080"
1505)
1506xt "32000,58000,36000,59000"
1507)
1508oxt "14000,69000,18000,70000"
1509text (MLText
1510uid 335,0
1511va (VaSet
1512fg "0,0,32768"
1513bg "0,0,32768"
1514)
1515xt "32200,58000,34300,59000"
1516st "
1517Path:
1518"
1519tm "CommentText"
1520wrapOption 3
1521visibleHeight 1000
1522visibleWidth 4000
1523)
1524position 1
1525ignorePrefs 1
1526titleBlock 1
1527)
1528*44 (CommentText
1529uid 336,0
1530shape (Rectangle
1531uid 337,0
1532sl 0
1533va (VaSet
1534vasetType 1
1535fg "65280,65280,46080"
1536)
1537xt "32000,59000,36000,60000"
1538)
1539oxt "14000,70000,18000,71000"
1540text (MLText
1541uid 338,0
1542va (VaSet
1543fg "0,0,32768"
1544bg "0,0,32768"
1545)
1546xt "32200,59000,34900,60000"
1547st "
1548Edited:
1549"
1550tm "CommentText"
1551wrapOption 3
1552visibleHeight 1000
1553visibleWidth 4000
1554)
1555position 1
1556ignorePrefs 1
1557titleBlock 1
1558)
1559*45 (CommentText
1560uid 339,0
1561shape (Rectangle
1562uid 340,0
1563sl 0
1564va (VaSet
1565vasetType 1
1566fg "65280,65280,46080"
1567)
1568xt "36000,58000,53000,59000"
1569)
1570oxt "18000,69000,35000,70000"
1571text (MLText
1572uid 341,0
1573va (VaSet
1574fg "0,0,32768"
1575bg "0,0,32768"
1576)
1577xt "36200,58000,51900,59000"
1578st "
1579%library/%unit/%view
1580"
1581tm "CommentText"
1582wrapOption 3
1583visibleHeight 1000
1584visibleWidth 17000
1585)
1586position 1
1587ignorePrefs 1
1588titleBlock 1
1589)
1590]
1591shape (GroupingShape
1592uid 311,0
1593va (VaSet
1594vasetType 1
1595fg "65535,65535,65535"
1596lineStyle 2
1597lineWidth 2
1598)
1599xt "32000,55000,73000,60000"
1600)
1601oxt "14000,66000,55000,71000"
1602)
1603*46 (SaComponent
1604uid 525,0
1605optionalChildren [
1606*47 (CptPort
1607uid 514,0
1608ps "OnEdgeStrategy"
1609shape (Triangle
1610uid 515,0
1611ro 90
1612va (VaSet
1613vasetType 1
1614fg "0,65535,0"
1615)
1616xt "12000,38625,12750,39375"
1617)
1618tg (CPTG
1619uid 516,0
1620ps "CptPortTextPlaceStrategy"
1621stg "RightVerticalLayoutStrategy"
1622f (Text
1623uid 517,0
1624va (VaSet
1625)
1626xt "9700,38500,11000,39500"
1627st "clk"
1628ju 2
1629blo "11000,39300"
1630)
1631)
1632thePort (LogicalPort
1633m 1
1634decl (Decl
1635n "clk"
1636t "std_logic"
1637preAdd 0
1638posAdd 0
1639o 1
1640suid 1,0
1641i "'0'"
1642)
1643)
1644)
1645*48 (CptPort
1646uid 518,0
1647ps "OnEdgeStrategy"
1648shape (Triangle
1649uid 519,0
1650ro 90
1651va (VaSet
1652vasetType 1
1653fg "0,65535,0"
1654)
1655xt "12000,39625,12750,40375"
1656)
1657tg (CPTG
1658uid 520,0
1659ps "CptPortTextPlaceStrategy"
1660stg "RightVerticalLayoutStrategy"
1661f (Text
1662uid 521,0
1663va (VaSet
1664)
1665xt "9700,39500,11000,40500"
1666st "rst"
1667ju 2
1668blo "11000,40300"
1669)
1670)
1671thePort (LogicalPort
1672m 1
1673decl (Decl
1674n "rst"
1675t "std_logic"
1676preAdd 0
1677posAdd 0
1678o 2
1679suid 2,0
1680i "'0'"
1681)
1682)
1683)
1684]
1685shape (Rectangle
1686uid 526,0
1687va (VaSet
1688vasetType 1
1689fg "0,49152,49152"
1690lineColor "0,0,50000"
1691lineWidth 2
1692)
1693xt "4000,38000,12000,42000"
1694)
1695oxt "22000,15000,30000,19000"
1696ttg (MlTextGroup
1697uid 527,0
1698ps "CenterOffsetStrategy"
1699stg "VerticalLayoutStrategy"
1700textVec [
1701*49 (Text
1702uid 528,0
1703va (VaSet
1704font "Arial,8,1"
1705)
1706xt "4150,42000,11850,43000"
1707st "FACT_FAD_TB_lib"
1708blo "4150,42800"
1709tm "BdLibraryNameMgr"
1710)
1711*50 (Text
1712uid 529,0
1713va (VaSet
1714font "Arial,8,1"
1715)
1716xt "4150,43000,10850,44000"
1717st "clock_generator"
1718blo "4150,43800"
1719tm "CptNameMgr"
1720)
1721*51 (Text
1722uid 530,0
1723va (VaSet
1724font "Arial,8,1"
1725)
1726xt "4150,44000,5950,45000"
1727st "U_2"
1728blo "4150,44800"
1729tm "InstanceNameMgr"
1730)
1731]
1732)
1733ga (GenericAssociation
1734uid 531,0
1735ps "EdgeToEdgeStrategy"
1736matrix (Matrix
1737uid 532,0
1738text (MLText
1739uid 533,0
1740va (VaSet
1741font "Courier New,8,0"
1742)
1743xt "1000,35400,19500,37000"
1744st "clock_period = 20 ns ( time )
1745reset_time = 50 ns ( time ) "
1746)
1747header ""
1748)
1749elements [
1750(GiElement
1751name "clock_period"
1752type "time"
1753value "20 ns"
1754)
1755(GiElement
1756name "reset_time"
1757type "time"
1758value "50 ns"
1759)
1760]
1761)
1762viewicon (ZoomableIcon
1763uid 534,0
1764sl 0
1765va (VaSet
1766vasetType 1
1767fg "49152,49152,49152"
1768)
1769xt "4250,40250,5750,41750"
1770iconName "VhdlFileViewIcon.png"
1771iconMaskName "VhdlFileViewIcon.msk"
1772ftype 10
1773)
1774ordering 1
1775viewiconposition 0
1776portVis (PortSigDisplay
1777)
1778archFileType "UNKNOWN"
1779)
1780*52 (Wire
1781uid 82,0
1782shape (OrthoPolyLine
1783uid 83,0
1784va (VaSet
1785vasetType 3
1786)
1787xt "26750,9000,36000,9000"
1788pts [
1789"26750,9000"
1790"36000,9000"
1791]
1792)
1793start &3
1794sat 32
1795eat 16
1796st 0
1797sf 1
1798tg (WTG
1799uid 86,0
1800ps "ConnStartEndStrategy"
1801stg "STSignalDisplayStrategy"
1802f (Text
1803uid 87,0
1804va (VaSet
1805)
1806xt "28000,8000,30900,9000"
1807st "PSCLK"
1808blo "28000,8800"
1809tm "WireNameMgr"
1810)
1811)
1812on &18
1813)
1814*53 (Wire
1815uid 90,0
1816shape (OrthoPolyLine
1817uid 91,0
1818va (VaSet
1819vasetType 3
1820)
1821xt "26750,11000,36000,11000"
1822pts [
1823"26750,11000"
1824"36000,11000"
1825]
1826)
1827start &4
1828sat 32
1829eat 16
1830st 0
1831sf 1
1832tg (WTG
1833uid 94,0
1834ps "ConnStartEndStrategy"
1835stg "STSignalDisplayStrategy"
1836f (Text
1837uid 95,0
1838va (VaSet
1839)
1840xt "28000,10000,30500,11000"
1841st "PSEN"
1842blo "28000,10800"
1843tm "WireNameMgr"
1844)
1845)
1846on &19
1847)
1848*54 (Wire
1849uid 99,0
1850shape (OrthoPolyLine
1851uid 100,0
1852va (VaSet
1853vasetType 3
1854)
1855xt "26750,13000,36000,13000"
1856pts [
1857"26750,13000"
1858"36000,13000"
1859]
1860)
1861start &5
1862sat 32
1863eat 16
1864st 0
1865sf 1
1866tg (WTG
1867uid 103,0
1868ps "ConnStartEndStrategy"
1869stg "STSignalDisplayStrategy"
1870f (Text
1871uid 104,0
1872va (VaSet
1873)
1874xt "28000,12000,32500,13000"
1875st "PSINCDEC"
1876blo "28000,12800"
1877tm "WireNameMgr"
1878)
1879)
1880on &20
1881)
1882*55 (Wire
1883uid 108,0
1884shape (OrthoPolyLine
1885uid 109,0
1886va (VaSet
1887vasetType 3
1888)
1889xt "26750,15000,36000,15000"
1890pts [
1891"26750,15000"
1892"36000,15000"
1893]
1894)
1895start &10
1896sat 32
1897eat 16
1898st 0
1899sf 1
1900tg (WTG
1901uid 112,0
1902ps "ConnStartEndStrategy"
1903stg "STSignalDisplayStrategy"
1904f (Text
1905uid 113,0
1906va (VaSet
1907)
1908xt "28000,14000,30900,15000"
1909st "shifting"
1910blo "28000,14800"
1911tm "WireNameMgr"
1912)
1913)
1914on &21
1915)
1916*56 (Wire
1917uid 117,0
1918shape (OrthoPolyLine
1919uid 118,0
1920va (VaSet
1921vasetType 3
1922)
1923xt "26750,17000,36000,17000"
1924pts [
1925"26750,17000"
1926"36000,17000"
1927]
1928)
1929start &11
1930sat 32
1931eat 16
1932st 0
1933sf 1
1934tg (WTG
1935uid 121,0
1936ps "ConnStartEndStrategy"
1937stg "STSignalDisplayStrategy"
1938f (Text
1939uid 122,0
1940va (VaSet
1941)
1942xt "28000,16000,30200,17000"
1943st "ready"
1944blo "28000,16800"
1945tm "WireNameMgr"
1946)
1947)
1948on &22
1949)
1950*57 (Wire
1951uid 126,0
1952shape (OrthoPolyLine
1953uid 127,0
1954va (VaSet
1955vasetType 3
1956lineWidth 2
1957)
1958xt "26750,19000,36000,19000"
1959pts [
1960"26750,19000"
1961"36000,19000"
1962]
1963)
1964start &12
1965sat 32
1966eat 16
1967sty 1
1968st 0
1969sf 1
1970tg (WTG
1971uid 130,0
1972ps "ConnStartEndStrategy"
1973stg "STSignalDisplayStrategy"
1974f (Text
1975uid 131,0
1976va (VaSet
1977)
1978xt "28000,18000,32800,19000"
1979st "offset : (7:0)"
1980blo "28000,18800"
1981tm "WireNameMgr"
1982)
1983)
1984on &23
1985)
1986*58 (Wire
1987uid 135,0
1988shape (OrthoPolyLine
1989uid 136,0
1990va (VaSet
1991vasetType 3
1992)
1993xt "1000,9000,19000,39000"
1994pts [
1995"12750,39000"
1996"19000,39000"
1997"19000,33000"
1998"1000,33000"
1999"1000,9000"
2000"10250,9000"
2001]
2002)
2003start &47
2004end &2
2005sat 32
2006eat 32
2007st 0
2008sf 1
2009tg (WTG
2010uid 139,0
2011ps "ConnStartEndStrategy"
2012stg "STSignalDisplayStrategy"
2013f (Text
2014uid 140,0
2015va (VaSet
2016)
2017xt "14750,38000,16050,39000"
2018st "clk"
2019blo "14750,38800"
2020tm "WireNameMgr"
2021)
2022)
2023on &24
2024)
2025*59 (Wire
2026uid 143,0
2027shape (OrthoPolyLine
2028uid 144,0
2029va (VaSet
2030vasetType 3
2031)
2032xt "3000,11000,10250,11000"
2033pts [
2034"3000,11000"
2035"10250,11000"
2036]
2037)
2038end &6
2039sat 16
2040eat 32
2041st 0
2042sf 1
2043tg (WTG
2044uid 147,0
2045ps "ConnStartEndStrategy"
2046stg "STSignalDisplayStrategy"
2047f (Text
2048uid 148,0
2049va (VaSet
2050)
2051xt "4000,10000,7700,11000"
2052st "PSDONE"
2053blo "4000,10800"
2054tm "WireNameMgr"
2055)
2056)
2057on &25
2058)
2059*60 (Wire
2060uid 151,0
2061shape (OrthoPolyLine
2062uid 152,0
2063va (VaSet
2064vasetType 3
2065)
2066xt "3000,13000,10250,13000"
2067pts [
2068"3000,13000"
2069"10250,13000"
2070]
2071)
2072end &7
2073sat 16
2074eat 32
2075st 0
2076sf 1
2077tg (WTG
2078uid 155,0
2079ps "ConnStartEndStrategy"
2080stg "STSignalDisplayStrategy"
2081f (Text
2082uid 156,0
2083va (VaSet
2084)
2085xt "4000,12000,7600,13000"
2086st "LOCKED"
2087blo "4000,12800"
2088tm "WireNameMgr"
2089)
2090)
2091on &26
2092)
2093*61 (Wire
2094uid 159,0
2095shape (OrthoPolyLine
2096uid 160,0
2097va (VaSet
2098vasetType 3
2099)
2100xt "3000,17000,10250,17000"
2101pts [
2102"3000,17000"
2103"10250,17000"
2104]
2105)
2106end &8
2107sat 16
2108eat 32
2109st 0
2110sf 1
2111tg (WTG
2112uid 163,0
2113ps "ConnStartEndStrategy"
2114stg "STSignalDisplayStrategy"
2115f (Text
2116uid 164,0
2117va (VaSet
2118)
2119xt "4000,16000,8600,17000"
2120st "shift_phase"
2121blo "4000,16800"
2122tm "WireNameMgr"
2123)
2124)
2125on &27
2126)
2127*62 (Wire
2128uid 167,0
2129shape (OrthoPolyLine
2130uid 168,0
2131va (VaSet
2132vasetType 3
2133)
2134xt "3000,19000,10250,19000"
2135pts [
2136"3000,19000"
2137"10250,19000"
2138]
2139)
2140end &9
2141sat 16
2142eat 32
2143st 0
2144sf 1
2145tg (WTG
2146uid 171,0
2147ps "ConnStartEndStrategy"
2148stg "STSignalDisplayStrategy"
2149f (Text
2150uid 172,0
2151va (VaSet
2152)
2153xt "4000,18000,7300,19000"
2154st "direction"
2155blo "4000,18800"
2156tm "WireNameMgr"
2157)
2158)
2159on &28
2160)
2161*63 (Wire
2162uid 175,0
2163shape (OrthoPolyLine
2164uid 176,0
2165va (VaSet
2166vasetType 3
2167)
2168xt "3000,20000,10250,20000"
2169pts [
2170"10250,20000"
2171"3000,20000"
2172]
2173)
2174start &13
2175sat 32
2176eat 16
2177st 0
2178sf 1
2179tg (WTG
2180uid 179,0
2181ps "ConnStartEndStrategy"
2182stg "STSignalDisplayStrategy"
2183f (Text
2184uid 180,0
2185va (VaSet
2186)
2187xt "4000,19000,5300,20000"
2188st "rst"
2189blo "4000,19800"
2190tm "WireNameMgr"
2191)
2192)
2193on &29
2194)
2195*64 (Wire
2196uid 184,0
2197shape (OrthoPolyLine
2198uid 185,0
2199va (VaSet
2200vasetType 3
2201)
2202xt "3000,22000,10250,22000"
2203pts [
2204"3000,22000"
2205"10250,22000"
2206]
2207)
2208end &14
2209sat 16
2210eat 32
2211st 0
2212sf 1
2213tg (WTG
2214uid 188,0
2215ps "ConnStartEndStrategy"
2216stg "STSignalDisplayStrategy"
2217f (Text
2218uid 189,0
2219va (VaSet
2220)
2221xt "4000,21000,8400,22000"
2222st "reset_DCM"
2223blo "4000,21800"
2224tm "WireNameMgr"
2225)
2226)
2227on &30
2228)
2229*65 (Wire
2230uid 200,0
2231shape (OrthoPolyLine
2232uid 201,0
2233va (VaSet
2234vasetType 3
2235)
2236xt "46000,19000,54000,19000"
2237pts [
2238"46000,19000"
2239"54000,19000"
2240]
2241)
2242end &31
2243sat 16
2244eat 2
2245st 0
2246sf 1
2247tg (WTG
2248uid 206,0
2249ps "ConnStartEndStrategy"
2250stg "STSignalDisplayStrategy"
2251f (Text
2252uid 207,0
2253va (VaSet
2254)
2255xt "47000,18000,51600,19000"
2256st "shift_phase"
2257blo "47000,18800"
2258tm "WireNameMgr"
2259)
2260)
2261on &27
2262)
2263*66 (Wire
2264uid 208,0
2265shape (OrthoPolyLine
2266uid 209,0
2267va (VaSet
2268vasetType 3
2269)
2270xt "46000,21000,54000,21000"
2271pts [
2272"46000,21000"
2273"54000,21000"
2274]
2275)
2276end &31
2277sat 16
2278eat 2
2279st 0
2280sf 1
2281tg (WTG
2282uid 214,0
2283ps "ConnStartEndStrategy"
2284stg "STSignalDisplayStrategy"
2285f (Text
2286uid 215,0
2287va (VaSet
2288)
2289xt "47000,20000,50300,21000"
2290st "direction"
2291blo "47000,20800"
2292tm "WireNameMgr"
2293)
2294)
2295on &28
2296)
2297*67 (Wire
2298uid 216,0
2299shape (OrthoPolyLine
2300uid 217,0
2301va (VaSet
2302vasetType 3
2303)
2304xt "46000,22000,54000,22000"
2305pts [
2306"54000,22000"
2307"46000,22000"
2308]
2309)
2310start &31
2311sat 1
2312eat 16
2313st 0
2314sf 1
2315tg (WTG
2316uid 222,0
2317ps "ConnStartEndStrategy"
2318stg "STSignalDisplayStrategy"
2319f (Text
2320uid 223,0
2321va (VaSet
2322)
2323xt "47000,21000,48300,22000"
2324st "rst"
2325blo "47000,21800"
2326tm "WireNameMgr"
2327)
2328)
2329on &29
2330)
2331*68 (Wire
2332uid 225,0
2333shape (OrthoPolyLine
2334uid 226,0
2335va (VaSet
2336vasetType 3
2337)
2338xt "46000,13000,54000,13000"
2339pts [
2340"46000,13000"
2341"54000,13000"
2342]
2343)
2344end &31
2345sat 16
2346eat 2
2347st 0
2348sf 1
2349tg (WTG
2350uid 231,0
2351ps "ConnStartEndStrategy"
2352stg "STSignalDisplayStrategy"
2353f (Text
2354uid 232,0
2355va (VaSet
2356)
2357xt "47000,12000,50700,13000"
2358st "PSDONE"
2359blo "47000,12800"
2360tm "WireNameMgr"
2361)
2362)
2363on &25
2364)
2365*69 (Wire
2366uid 233,0
2367shape (OrthoPolyLine
2368uid 234,0
2369va (VaSet
2370vasetType 3
2371)
2372xt "46000,24000,54000,24000"
2373pts [
2374"46000,24000"
2375"54000,24000"
2376]
2377)
2378end &31
2379sat 16
2380eat 2
2381st 0
2382sf 1
2383tg (WTG
2384uid 239,0
2385ps "ConnStartEndStrategy"
2386stg "STSignalDisplayStrategy"
2387f (Text
2388uid 240,0
2389va (VaSet
2390)
2391xt "47000,23000,51400,24000"
2392st "reset_DCM"
2393blo "47000,23800"
2394tm "WireNameMgr"
2395)
2396)
2397on &30
2398)
2399*70 (Wire
2400uid 241,0
2401shape (OrthoPolyLine
2402uid 242,0
2403va (VaSet
2404vasetType 3
2405)
2406xt "69000,17000,79000,17000"
2407pts [
2408"69000,17000"
2409"79000,17000"
2410]
2411)
2412start &31
2413sat 1
2414eat 16
2415st 0
2416sf 1
2417tg (WTG
2418uid 247,0
2419ps "ConnStartEndStrategy"
2420stg "STSignalDisplayStrategy"
2421f (Text
2422uid 248,0
2423va (VaSet
2424)
2425xt "70000,16000,72900,17000"
2426st "shifting"
2427blo "70000,16800"
2428tm "WireNameMgr"
2429)
2430)
2431on &21
2432)
2433*71 (Wire
2434uid 250,0
2435shape (OrthoPolyLine
2436uid 251,0
2437va (VaSet
2438vasetType 3
2439)
2440xt "69000,19000,79000,19000"
2441pts [
2442"69000,19000"
2443"79000,19000"
2444]
2445)
2446start &31
2447sat 1
2448eat 16
2449st 0
2450sf 1
2451tg (WTG
2452uid 256,0
2453ps "ConnStartEndStrategy"
2454stg "STSignalDisplayStrategy"
2455f (Text
2456uid 257,0
2457va (VaSet
2458)
2459xt "70000,18000,72200,19000"
2460st "ready"
2461blo "70000,18800"
2462tm "WireNameMgr"
2463)
2464)
2465on &22
2466)
2467*72 (Wire
2468uid 259,0
2469shape (OrthoPolyLine
2470uid 260,0
2471va (VaSet
2472vasetType 3
2473lineWidth 2
2474)
2475xt "69000,21000,79000,21000"
2476pts [
2477"69000,21000"
2478"79000,21000"
2479]
2480)
2481start &31
2482sat 1
2483eat 16
2484sty 1
2485st 0
2486sf 1
2487tg (WTG
2488uid 265,0
2489ps "ConnStartEndStrategy"
2490stg "STSignalDisplayStrategy"
2491f (Text
2492uid 266,0
2493va (VaSet
2494)
2495xt "71000,20000,75800,21000"
2496st "offset : (7:0)"
2497blo "71000,20800"
2498tm "WireNameMgr"
2499)
2500)
2501on &23
2502)
2503*73 (Wire
2504uid 276,0
2505shape (OrthoPolyLine
2506uid 277,0
2507va (VaSet
2508vasetType 3
2509)
2510xt "46000,15000,54000,15000"
2511pts [
2512"46000,15000"
2513"54000,15000"
2514]
2515)
2516end &31
2517sat 16
2518eat 2
2519st 0
2520sf 1
2521tg (WTG
2522uid 282,0
2523ps "ConnStartEndStrategy"
2524stg "STSignalDisplayStrategy"
2525f (Text
2526uid 283,0
2527va (VaSet
2528)
2529xt "47000,14000,50600,15000"
2530st "LOCKED"
2531blo "47000,14800"
2532tm "WireNameMgr"
2533)
2534)
2535on &26
2536)
2537*74 (Wire
2538uid 284,0
2539shape (OrthoPolyLine
2540uid 285,0
2541va (VaSet
2542vasetType 3
2543)
2544xt "69000,11000,79000,11000"
2545pts [
2546"69000,11000"
2547"79000,11000"
2548]
2549)
2550start &31
2551sat 1
2552eat 16
2553st 0
2554sf 1
2555tg (WTG
2556uid 290,0
2557ps "ConnStartEndStrategy"
2558stg "STSignalDisplayStrategy"
2559f (Text
2560uid 291,0
2561va (VaSet
2562)
2563xt "70000,10000,72900,11000"
2564st "PSCLK"
2565blo "70000,10800"
2566tm "WireNameMgr"
2567)
2568)
2569on &18
2570)
2571*75 (Wire
2572uid 292,0
2573shape (OrthoPolyLine
2574uid 293,0
2575va (VaSet
2576vasetType 3
2577)
2578xt "69000,13000,79000,13000"
2579pts [
2580"69000,13000"
2581"79000,13000"
2582]
2583)
2584start &31
2585sat 1
2586eat 16
2587st 0
2588sf 1
2589tg (WTG
2590uid 298,0
2591ps "ConnStartEndStrategy"
2592stg "STSignalDisplayStrategy"
2593f (Text
2594uid 299,0
2595va (VaSet
2596)
2597xt "70000,12000,72500,13000"
2598st "PSEN"
2599blo "70000,12800"
2600tm "WireNameMgr"
2601)
2602)
2603on &19
2604)
2605*76 (Wire
2606uid 301,0
2607shape (OrthoPolyLine
2608uid 302,0
2609va (VaSet
2610vasetType 3
2611)
2612xt "69000,15000,79000,15000"
2613pts [
2614"69000,15000"
2615"79000,15000"
2616]
2617)
2618start &31
2619sat 1
2620eat 16
2621st 0
2622sf 1
2623tg (WTG
2624uid 307,0
2625ps "ConnStartEndStrategy"
2626stg "STSignalDisplayStrategy"
2627f (Text
2628uid 308,0
2629va (VaSet
2630)
2631xt "70000,14000,74500,15000"
2632st "PSINCDEC"
2633blo "70000,14800"
2634tm "WireNameMgr"
2635)
2636)
2637on &20
2638)
2639*77 (Wire
2640uid 535,0
2641shape (OrthoPolyLine
2642uid 536,0
2643va (VaSet
2644vasetType 3
2645)
2646xt "44000,25000,54000,25000"
2647pts [
2648"44000,25000"
2649"54000,25000"
2650]
2651)
2652end &31
2653sat 16
2654eat 1
2655st 0
2656sf 1
2657si 0
2658tg (WTG
2659uid 541,0
2660ps "ConnStartEndStrategy"
2661stg "STSignalDisplayStrategy"
2662f (Text
2663uid 542,0
2664va (VaSet
2665)
2666xt "46000,24000,47300,25000"
2667st "clk"
2668blo "46000,24800"
2669tm "WireNameMgr"
2670)
2671)
2672on &24
2673)
2674]
2675bg "65535,65535,65535"
2676grid (Grid
2677origin "0,0"
2678isVisible 1
2679isActive 1
2680xSpacing 1000
2681xySpacing 1000
2682xShown 1
2683yShown 1
2684color "26368,26368,26368"
2685)
2686packageList *78 (PackageList
2687uid 368,0
2688stg "VerticalLayoutStrategy"
2689textVec [
2690*79 (Text
2691uid 369,0
2692va (VaSet
2693font "arial,8,1"
2694)
2695xt "0,0,5400,1000"
2696st "Package List"
2697blo "0,800"
2698)
2699*80 (MLText
2700uid 370,0
2701va (VaSet
2702)
2703xt "0,1000,15000,8000"
2704st "LIBRARY ieee;
2705USE ieee.std_logic_1164.ALL;
2706USE IEEE.NUMERIC_STD.ALL;
2707LIBRARY FACT_FAD_lib;
2708USE FACT_FAD_lib.fad_definitions.ALL;
2709USE ieee.std_logic_unsigned.all;
2710USE ieee.std_logic_arith.all;"
2711tm "PackageList"
2712)
2713]
2714)
2715compDirBlock (MlTextGroup
2716uid 371,0
2717stg "VerticalLayoutStrategy"
2718textVec [
2719*81 (Text
2720uid 372,0
2721va (VaSet
2722isHidden 1
2723font "Arial,8,1"
2724)
2725xt "20000,0,28100,1000"
2726st "Compiler Directives"
2727blo "20000,800"
2728)
2729*82 (Text
2730uid 373,0
2731va (VaSet
2732isHidden 1
2733font "Arial,8,1"
2734)
2735xt "20000,1000,29600,2000"
2736st "Pre-module directives:"
2737blo "20000,1800"
2738)
2739*83 (MLText
2740uid 374,0
2741va (VaSet
2742isHidden 1
2743)
2744xt "20000,2000,27500,4000"
2745st "`resetall
2746`timescale 1ns/10ps"
2747tm "BdCompilerDirectivesTextMgr"
2748)
2749*84 (Text
2750uid 375,0
2751va (VaSet
2752isHidden 1
2753font "Arial,8,1"
2754)
2755xt "20000,4000,30100,5000"
2756st "Post-module directives:"
2757blo "20000,4800"
2758)
2759*85 (MLText
2760uid 376,0
2761va (VaSet
2762isHidden 1
2763)
2764xt "20000,0,20000,0"
2765tm "BdCompilerDirectivesTextMgr"
2766)
2767*86 (Text
2768uid 377,0
2769va (VaSet
2770isHidden 1
2771font "Arial,8,1"
2772)
2773xt "20000,5000,29900,6000"
2774st "End-module directives:"
2775blo "20000,5800"
2776)
2777*87 (MLText
2778uid 378,0
2779va (VaSet
2780isHidden 1
2781)
2782xt "20000,6000,20000,6000"
2783tm "BdCompilerDirectivesTextMgr"
2784)
2785]
2786associable 1
2787)
2788windowSize "-4,-4,1284,998"
2789viewArea "22779,-12050,84296,37083"
2790cachedDiagramExtent "0,-16000,79400,60000"
2791hasePageBreakOrigin 1
2792pageBreakOrigin "0,0"
2793lastUid 576,0
2794defaultCommentText (CommentText
2795shape (Rectangle
2796layer 0
2797va (VaSet
2798vasetType 1
2799fg "65280,65280,46080"
2800lineColor "0,0,32768"
2801)
2802xt "0,0,15000,5000"
2803)
2804text (MLText
2805va (VaSet
2806fg "0,0,32768"
2807)
2808xt "200,200,2000,1200"
2809st "
2810Text
2811"
2812tm "CommentText"
2813wrapOption 3
2814visibleHeight 4600
2815visibleWidth 14600
2816)
2817)
2818defaultPanel (Panel
2819shape (RectFrame
2820va (VaSet
2821vasetType 1
2822fg "65535,65535,65535"
2823lineColor "32768,0,0"
2824lineWidth 3
2825)
2826xt "0,0,20000,20000"
2827)
2828title (TextAssociate
2829ps "TopLeftStrategy"
2830text (Text
2831va (VaSet
2832font "Arial,8,1"
2833)
2834xt "1000,1000,3800,2000"
2835st "Panel0"
2836blo "1000,1800"
2837tm "PanelText"
2838)
2839)
2840)
2841defaultBlk (Blk
2842shape (Rectangle
2843va (VaSet
2844vasetType 1
2845fg "39936,56832,65280"
2846lineColor "0,0,32768"
2847lineWidth 2
2848)
2849xt "0,0,8000,10000"
2850)
2851ttg (MlTextGroup
2852ps "CenterOffsetStrategy"
2853stg "VerticalLayoutStrategy"
2854textVec [
2855*88 (Text
2856va (VaSet
2857font "Arial,8,1"
2858)
2859xt "2200,3500,5800,4500"
2860st "<library>"
2861blo "2200,4300"
2862tm "BdLibraryNameMgr"
2863)
2864*89 (Text
2865va (VaSet
2866font "Arial,8,1"
2867)
2868xt "2200,4500,5600,5500"
2869st "<block>"
2870blo "2200,5300"
2871tm "BlkNameMgr"
2872)
2873*90 (Text
2874va (VaSet
2875font "Arial,8,1"
2876)
2877xt "2200,5500,4000,6500"
2878st "U_0"
2879blo "2200,6300"
2880tm "InstanceNameMgr"
2881)
2882]
2883)
2884ga (GenericAssociation
2885ps "EdgeToEdgeStrategy"
2886matrix (Matrix
2887text (MLText
2888va (VaSet
2889font "Courier New,8,0"
2890)
2891xt "2200,13500,2200,13500"
2892)
2893header ""
2894)
2895elements [
2896]
2897)
2898viewicon (ZoomableIcon
2899sl 0
2900va (VaSet
2901vasetType 1
2902fg "49152,49152,49152"
2903)
2904xt "0,0,1500,1500"
2905iconName "UnknownFile.png"
2906iconMaskName "UnknownFile.msk"
2907)
2908viewiconposition 0
2909)
2910defaultMWComponent (MWC
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2913vasetType 1
2914fg "0,65535,0"
2915lineColor "0,32896,0"
2916lineWidth 2
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2918xt "0,0,8000,10000"
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2920ttg (MlTextGroup
2921ps "CenterOffsetStrategy"
2922stg "VerticalLayoutStrategy"
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2930blo "550,4300"
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2938blo "550,5300"
2939)
2940*93 (Text
2941va (VaSet
2942font "Arial,8,1"
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2944xt "550,5500,2350,6500"
2945st "U_0"
2946blo "550,6300"
2947tm "InstanceNameMgr"
2948)
2949]
2950)
2951ga (GenericAssociation
2952ps "EdgeToEdgeStrategy"
2953matrix (Matrix
2954text (MLText
2955va (VaSet
2956font "Courier New,8,0"
2957)
2958xt "-6450,1500,-6450,1500"
2959)
2960header ""
2961)
2962elements [
2963]
2964)
2965portVis (PortSigDisplay
2966)
2967prms (Property
2968pclass "params"
2969pname "params"
2970ptn "String"
2971)
2972visOptions (mwParamsVisibilityOptions
2973)
2974)
2975defaultSaComponent (SaComponent
2976shape (Rectangle
2977va (VaSet
2978vasetType 1
2979fg "0,65535,0"
2980lineColor "0,32896,0"
2981lineWidth 2
2982)
2983xt "0,0,8000,10000"
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2985ttg (MlTextGroup
2986ps "CenterOffsetStrategy"
2987stg "VerticalLayoutStrategy"
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2990va (VaSet
2991font "Arial,8,1"
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2995blo "900,4300"
2996tm "BdLibraryNameMgr"
2997)
2998*95 (Text
2999va (VaSet
3000font "Arial,8,1"
3001)
3002xt "900,4500,7100,5500"
3003st "SaComponent"
3004blo "900,5300"
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3006)
3007*96 (Text
3008va (VaSet
3009font "Arial,8,1"
3010)
3011xt "900,5500,2700,6500"
3012st "U_0"
3013blo "900,6300"
3014tm "InstanceNameMgr"
3015)
3016]
3017)
3018ga (GenericAssociation
3019ps "EdgeToEdgeStrategy"
3020matrix (Matrix
3021text (MLText
3022va (VaSet
3023font "Courier New,8,0"
3024)
3025xt "-6100,1500,-6100,1500"
3026)
3027header ""
3028)
3029elements [
3030]
3031)
3032viewicon (ZoomableIcon
3033sl 0
3034va (VaSet
3035vasetType 1
3036fg "49152,49152,49152"
3037)
3038xt "0,0,1500,1500"
3039iconName "UnknownFile.png"
3040iconMaskName "UnknownFile.msk"
3041)
3042viewiconposition 0
3043portVis (PortSigDisplay
3044)
3045archFileType "UNKNOWN"
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3047defaultVhdlComponent (VhdlComponent
3048shape (Rectangle
3049va (VaSet
3050vasetType 1
3051fg "0,65535,0"
3052lineColor "0,32896,0"
3053lineWidth 2
3054)
3055xt "0,0,8000,10000"
3056)
3057ttg (MlTextGroup
3058ps "CenterOffsetStrategy"
3059stg "VerticalLayoutStrategy"
3060textVec [
3061*97 (Text
3062va (VaSet
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3067blo "500,4300"
3068)
3069*98 (Text
3070va (VaSet
3071font "Arial,8,1"
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3073xt "500,4500,7500,5500"
3074st "VhdlComponent"
3075blo "500,5300"
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3077*99 (Text
3078va (VaSet
3079font "Arial,8,1"
3080)
3081xt "500,5500,2300,6500"
3082st "U_0"
3083blo "500,6300"
3084tm "InstanceNameMgr"
3085)
3086]
3087)
3088ga (GenericAssociation
3089ps "EdgeToEdgeStrategy"
3090matrix (Matrix
3091text (MLText
3092va (VaSet
3093font "Courier New,8,0"
3094)
3095xt "-6500,1500,-6500,1500"
3096)
3097header ""
3098)
3099elements [
3100]
3101)
3102portVis (PortSigDisplay
3103)
3104entityPath ""
3105archName ""
3106archPath ""
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3108defaultVerilogComponent (VerilogComponent
3109shape (Rectangle
3110va (VaSet
3111vasetType 1
3112fg "0,65535,0"
3113lineColor "0,32896,0"
3114lineWidth 2
3115)
3116xt "-450,0,8450,10000"
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3118ttg (MlTextGroup
3119ps "CenterOffsetStrategy"
3120stg "VerticalLayoutStrategy"
3121textVec [
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3123va (VaSet
3124font "Arial,8,1"
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3130*101 (Text
3131va (VaSet
3132font "Arial,8,1"
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3134xt "50,4500,7950,5500"
3135st "VerilogComponent"
3136blo "50,5300"
3137)
3138*102 (Text
3139va (VaSet
3140font "Arial,8,1"
3141)
3142xt "50,5500,1850,6500"
3143st "U_0"
3144blo "50,6300"
3145tm "InstanceNameMgr"
3146)
3147]
3148)
3149ga (GenericAssociation
3150ps "EdgeToEdgeStrategy"
3151matrix (Matrix
3152text (MLText
3153va (VaSet
3154font "Courier New,8,0"
3155)
3156xt "-6950,1500,-6950,1500"
3157)
3158header ""
3159)
3160elements [
3161]
3162)
3163entityPath ""
3164)
3165defaultHdlText (HdlText
3166shape (Rectangle
3167va (VaSet
3168vasetType 1
3169fg "65535,65535,37120"
3170lineColor "0,0,32768"
3171lineWidth 2
3172)
3173xt "0,0,8000,10000"
3174)
3175ttg (MlTextGroup
3176ps "CenterOffsetStrategy"
3177stg "VerticalLayoutStrategy"
3178textVec [
3179*103 (Text
3180va (VaSet
3181font "Arial,8,1"
3182)
3183xt "3150,4000,4850,5000"
3184st "eb1"
3185blo "3150,4800"
3186tm "HdlTextNameMgr"
3187)
3188*104 (Text
3189va (VaSet
3190font "Arial,8,1"
3191)
3192xt "3150,5000,3950,6000"
3193st "1"
3194blo "3150,5800"
3195tm "HdlTextNumberMgr"
3196)
3197]
3198)
3199viewicon (ZoomableIcon
3200sl 0
3201va (VaSet
3202vasetType 1
3203fg "49152,49152,49152"
3204)
3205xt "0,0,1500,1500"
3206iconName "UnknownFile.png"
3207iconMaskName "UnknownFile.msk"
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3209viewiconposition 0
3210)
3211defaultEmbeddedText (EmbeddedText
3212commentText (CommentText
3213ps "CenterOffsetStrategy"
3214shape (Rectangle
3215va (VaSet
3216vasetType 1
3217fg "65535,65535,65535"
3218lineColor "0,0,32768"
3219lineWidth 2
3220)
3221xt "0,0,18000,5000"
3222)
3223text (MLText
3224va (VaSet
3225)
3226xt "200,200,2000,1200"
3227st "
3228Text
3229"
3230tm "HdlTextMgr"
3231wrapOption 3
3232visibleHeight 4600
3233visibleWidth 17600
3234)
3235)
3236)
3237defaultGlobalConnector (GlobalConnector
3238shape (Circle
3239va (VaSet
3240vasetType 1
3241fg "65535,65535,0"
3242)
3243xt "-1000,-1000,1000,1000"
3244radius 1000
3245)
3246name (Text
3247va (VaSet
3248font "Arial,8,1"
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3250xt "-500,-500,500,500"
3251st "G"
3252blo "-500,300"
3253)
3254)
3255defaultRipper (Ripper
3256ps "OnConnectorStrategy"
3257shape (Line2D
3258pts [
3259"0,0"
3260"1000,1000"
3261]
3262va (VaSet
3263vasetType 1
3264)
3265xt "0,0,1000,1000"
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3267)
3268defaultBdJunction (BdJunction
3269ps "OnConnectorStrategy"
3270shape (Circle
3271va (VaSet
3272vasetType 1
3273)
3274xt "-400,-400,400,400"
3275radius 400
3276)
3277)
3278defaultPortIoIn (PortIoIn
3279shape (CompositeShape
3280va (VaSet
3281vasetType 1
3282fg "0,0,32768"
3283)
3284optionalChildren [
3285(Pentagon
3286sl 0
3287ro 270
3288xt "-2000,-375,-500,375"
3289)
3290(Line
3291sl 0
3292ro 270
3293xt "-500,0,0,0"
3294pts [
3295"-500,0"
3296"0,0"
3297]
3298)
3299]
3300)
3301stc 0
3302sf 1
3303tg (WTG
3304ps "PortIoTextPlaceStrategy"
3305stg "STSignalDisplayStrategy"
3306f (Text
3307va (VaSet
3308)
3309xt "-1375,-1000,-1375,-1000"
3310ju 2
3311blo "-1375,-1000"
3312tm "WireNameMgr"
3313)
3314)
3315)
3316defaultPortIoOut (PortIoOut
3317shape (CompositeShape
3318va (VaSet
3319vasetType 1
3320fg "0,0,32768"
3321)
3322optionalChildren [
3323(Pentagon
3324sl 0
3325ro 270
3326xt "500,-375,2000,375"
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3328(Line
3329sl 0
3330ro 270
3331xt "0,0,500,0"
3332pts [
3333"0,0"
3334"500,0"
3335]
3336)
3337]
3338)
3339stc 0
3340sf 1
3341tg (WTG
3342ps "PortIoTextPlaceStrategy"
3343stg "STSignalDisplayStrategy"
3344f (Text
3345va (VaSet
3346)
3347xt "625,-1000,625,-1000"
3348blo "625,-1000"
3349tm "WireNameMgr"
3350)
3351)
3352)
3353defaultPortIoInOut (PortIoInOut
3354shape (CompositeShape
3355va (VaSet
3356vasetType 1
3357fg "0,0,32768"
3358)
3359optionalChildren [
3360(Hexagon
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3362xt "500,-375,2000,375"
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3364(Line
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3366xt "0,0,500,0"
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3368"0,0"
3369"500,0"
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3371)
3372]
3373)
3374stc 0
3375sf 1
3376tg (WTG
3377ps "PortIoTextPlaceStrategy"
3378stg "STSignalDisplayStrategy"
3379f (Text
3380va (VaSet
3381)
3382xt "0,-375,0,-375"
3383blo "0,-375"
3384tm "WireNameMgr"
3385)
3386)
3387)
3388defaultPortIoBuffer (PortIoBuffer
3389shape (CompositeShape
3390va (VaSet
3391vasetType 1
3392fg "65535,65535,65535"
3393lineColor "0,0,32768"
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3395optionalChildren [
3396(Hexagon
3397sl 0
3398xt "500,-375,2000,375"
3399)
3400(Line
3401sl 0
3402xt "0,0,500,0"
3403pts [
3404"0,0"
3405"500,0"
3406]
3407)
3408]
3409)
3410stc 0
3411sf 1
3412tg (WTG
3413ps "PortIoTextPlaceStrategy"
3414stg "STSignalDisplayStrategy"
3415f (Text
3416va (VaSet
3417)
3418xt "0,-375,0,-375"
3419blo "0,-375"
3420tm "WireNameMgr"
3421)
3422)
3423)
3424defaultSignal (Wire
3425shape (OrthoPolyLine
3426va (VaSet
3427vasetType 3
3428)
3429pts [
3430"0,0"
3431"0,0"
3432]
3433)
3434ss 0
3435es 0
3436sat 32
3437eat 32
3438st 0
3439sf 1
3440si 0
3441tg (WTG
3442ps "ConnStartEndStrategy"
3443stg "STSignalDisplayStrategy"
3444f (Text
3445va (VaSet
3446)
3447xt "0,0,1900,1000"
3448st "sig0"
3449blo "0,800"
3450tm "WireNameMgr"
3451)
3452)
3453)
3454defaultBus (Wire
3455shape (OrthoPolyLine
3456va (VaSet
3457vasetType 3
3458lineWidth 2
3459)
3460pts [
3461"0,0"
3462"0,0"
3463]
3464)
3465ss 0
3466es 0
3467sat 32
3468eat 32
3469sty 1
3470st 0
3471sf 1
3472si 0
3473tg (WTG
3474ps "ConnStartEndStrategy"
3475stg "STSignalDisplayStrategy"
3476f (Text
3477va (VaSet
3478)
3479xt "0,0,2400,1000"
3480st "dbus0"
3481blo "0,800"
3482tm "WireNameMgr"
3483)
3484)
3485)
3486defaultBundle (Bundle
3487shape (OrthoPolyLine
3488va (VaSet
3489vasetType 3
3490lineColor "32768,0,0"
3491lineWidth 2
3492)
3493pts [
3494"0,0"
3495"0,0"
3496]
3497)
3498ss 0
3499es 0
3500sat 32
3501eat 32
3502textGroup (BiTextGroup
3503ps "ConnStartEndStrategy"
3504stg "VerticalLayoutStrategy"
3505first (Text
3506va (VaSet
3507)
3508xt "0,0,3000,1000"
3509st "bundle0"
3510blo "0,800"
3511tm "BundleNameMgr"
3512)
3513second (MLText
3514va (VaSet
3515)
3516xt "0,1000,1000,2000"
3517st "()"
3518tm "BundleContentsMgr"
3519)
3520)
3521bundleNet &0
3522)
3523defaultPortMapFrame (PortMapFrame
3524ps "PortMapFrameStrategy"
3525shape (RectFrame
3526va (VaSet
3527vasetType 1
3528fg "65535,65535,65535"
3529lineColor "0,0,32768"
3530lineWidth 2
3531)
3532xt "0,0,10000,12000"
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3534portMapText (BiTextGroup
3535ps "BottomRightOffsetStrategy"
3536stg "VerticalLayoutStrategy"
3537first (MLText
3538va (VaSet
3539)
3540)
3541second (MLText
3542va (VaSet
3543)
3544tm "PortMapTextMgr"
3545)
3546)
3547)
3548defaultGenFrame (Frame
3549shape (RectFrame
3550va (VaSet
3551vasetType 1
3552fg "65535,65535,65535"
3553lineColor "26368,26368,26368"
3554lineStyle 2
3555lineWidth 3
3556)
3557xt "0,0,20000,20000"
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3559title (TextAssociate
3560ps "TopLeftStrategy"
3561text (MLText
3562va (VaSet
3563)
3564xt "0,-1100,12600,-100"
3565st "g0: FOR i IN 0 TO n GENERATE"
3566tm "FrameTitleTextMgr"
3567)
3568)
3569seqNum (FrameSequenceNumber
3570ps "TopLeftStrategy"
3571shape (Rectangle
3572va (VaSet
3573vasetType 1
3574fg "65535,65535,65535"
3575)
3576xt "50,50,1250,1450"
3577)
3578num (Text
3579va (VaSet
3580)
3581xt "250,250,1050,1250"
3582st "1"
3583blo "250,1050"
3584tm "FrameSeqNumMgr"
3585)
3586)
3587decls (MlTextGroup
3588ps "BottomRightOffsetStrategy"
3589stg "VerticalLayoutStrategy"
3590textVec [
3591*105 (Text
3592va (VaSet
3593font "Arial,8,1"
3594)
3595xt "14100,20000,22000,21000"
3596st "Frame Declarations"
3597blo "14100,20800"
3598)
3599*106 (MLText
3600va (VaSet
3601)
3602xt "14100,21000,14100,21000"
3603tm "BdFrameDeclTextMgr"
3604)
3605]
3606)
3607)
3608defaultBlockFrame (Frame
3609shape (RectFrame
3610va (VaSet
3611vasetType 1
3612fg "65535,65535,65535"
3613lineColor "26368,26368,26368"
3614lineStyle 1
3615lineWidth 3
3616)
3617xt "0,0,20000,20000"
3618)
3619title (TextAssociate
3620ps "TopLeftStrategy"
3621text (MLText
3622va (VaSet
3623)
3624xt "0,-1100,7400,-100"
3625st "b0: BLOCK (guard)"
3626tm "FrameTitleTextMgr"
3627)
3628)
3629seqNum (FrameSequenceNumber
3630ps "TopLeftStrategy"
3631shape (Rectangle
3632va (VaSet
3633vasetType 1
3634fg "65535,65535,65535"
3635)
3636xt "50,50,1250,1450"
3637)
3638num (Text
3639va (VaSet
3640)
3641xt "250,250,1050,1250"
3642st "1"
3643blo "250,1050"
3644tm "FrameSeqNumMgr"
3645)
3646)
3647decls (MlTextGroup
3648ps "BottomRightOffsetStrategy"
3649stg "VerticalLayoutStrategy"
3650textVec [
3651*107 (Text
3652va (VaSet
3653font "Arial,8,1"
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3655xt "14100,20000,22000,21000"
3656st "Frame Declarations"
3657blo "14100,20800"
3658)
3659*108 (MLText
3660va (VaSet
3661)
3662xt "14100,21000,14100,21000"
3663tm "BdFrameDeclTextMgr"
3664)
3665]
3666)
3667style 3
3668)
3669defaultSaCptPort (CptPort
3670ps "OnEdgeStrategy"
3671shape (Triangle
3672ro 90
3673va (VaSet
3674vasetType 1
3675fg "0,65535,0"
3676)
3677xt "0,0,750,750"
3678)
3679tg (CPTG
3680ps "CptPortTextPlaceStrategy"
3681stg "VerticalLayoutStrategy"
3682f (Text
3683va (VaSet
3684)
3685xt "0,750,1800,1750"
3686st "Port"
3687blo "0,1550"
3688)
3689)
3690thePort (LogicalPort
3691decl (Decl
3692n "Port"
3693t ""
3694o 0
3695)
3696)
3697)
3698defaultSaCptPortBuffer (CptPort
3699ps "OnEdgeStrategy"
3700shape (Diamond
3701va (VaSet
3702vasetType 1
3703fg "65535,65535,65535"
3704)
3705xt "0,0,750,750"
3706)
3707tg (CPTG
3708ps "CptPortTextPlaceStrategy"
3709stg "VerticalLayoutStrategy"
3710f (Text
3711va (VaSet
3712)
3713xt "0,750,1800,1750"
3714st "Port"
3715blo "0,1550"
3716)
3717)
3718thePort (LogicalPort
3719m 3
3720decl (Decl
3721n "Port"
3722t ""
3723o 0
3724)
3725)
3726)
3727defaultDeclText (MLText
3728va (VaSet
3729font "Courier New,8,0"
3730)
3731)
3732archDeclarativeBlock (BdArchDeclBlock
3733uid 1,0
3734stg "BdArchDeclBlockLS"
3735declLabel (Text
3736uid 2,0
3737va (VaSet
3738font "Arial,8,1"
3739)
3740xt "11000,-16000,16400,-15000"
3741st "Declarations"
3742blo "11000,-15200"
3743)
3744portLabel (Text
3745uid 3,0
3746va (VaSet
3747font "Arial,8,1"
3748)
3749xt "11000,-15000,13700,-14000"
3750st "Ports:"
3751blo "11000,-14200"
3752)
3753preUserLabel (Text
3754uid 4,0
3755va (VaSet
3756isHidden 1
3757font "Arial,8,1"
3758)
3759xt "11000,-16000,14800,-15000"
3760st "Pre User:"
3761blo "11000,-15200"
3762)
3763preUserText (MLText
3764uid 5,0
3765va (VaSet
3766isHidden 1
3767font "Courier New,8,0"
3768)
3769xt "11000,-16000,11000,-16000"
3770tm "BdDeclarativeTextMgr"
3771)
3772diagSignalLabel (Text
3773uid 6,0
3774va (VaSet
3775font "Arial,8,1"
3776)
3777xt "11000,-14000,18100,-13000"
3778st "Diagram Signals:"
3779blo "11000,-13200"
3780)
3781postUserLabel (Text
3782uid 7,0
3783va (VaSet
3784isHidden 1
3785font "Arial,8,1"
3786)
3787xt "11000,-16000,15700,-15000"
3788st "Post User:"
3789blo "11000,-15200"
3790)
3791postUserText (MLText
3792uid 8,0
3793va (VaSet
3794isHidden 1
3795font "Courier New,8,0"
3796)
3797xt "11000,-16000,11000,-16000"
3798tm "BdDeclarativeTextMgr"
3799)
3800)
3801commonDM (CommonDM
3802ldm (LogicalDM
3803suid 14,0
3804usingSuid 1
3805emptyRow *109 (LEmptyRow
3806)
3807uid 381,0
3808optionalChildren [
3809*110 (RefLabelRowHdr
3810)
3811*111 (TitleRowHdr
3812)
3813*112 (FilterRowHdr
3814)
3815*113 (RefLabelColHdr
3816tm "RefLabelColHdrMgr"
3817)
3818*114 (RowExpandColHdr
3819tm "RowExpandColHdrMgr"
3820)
3821*115 (GroupColHdr
3822tm "GroupColHdrMgr"
3823)
3824*116 (NameColHdr
3825tm "BlockDiagramNameColHdrMgr"
3826)
3827*117 (ModeColHdr
3828tm "BlockDiagramModeColHdrMgr"
3829)
3830*118 (TypeColHdr
3831tm "BlockDiagramTypeColHdrMgr"
3832)
3833*119 (BoundsColHdr
3834tm "BlockDiagramBoundsColHdrMgr"
3835)
3836*120 (InitColHdr
3837tm "BlockDiagramInitColHdrMgr"
3838)
3839*121 (EolColHdr
3840tm "BlockDiagramEolColHdrMgr"
3841)
3842*122 (LeafLogPort
3843port (LogicalPort
3844lang 10
3845m 4
3846decl (Decl
3847n "PSCLK"
3848t "std_logic"
3849o 1
3850suid 1,0
3851)
3852)
3853uid 342,0
3854)
3855*123 (LeafLogPort
3856port (LogicalPort
3857lang 10
3858m 4
3859decl (Decl
3860n "PSEN"
3861t "std_logic"
3862o 2
3863suid 2,0
3864)
3865)
3866uid 344,0
3867)
3868*124 (LeafLogPort
3869port (LogicalPort
3870lang 10
3871m 4
3872decl (Decl
3873n "PSINCDEC"
3874t "std_logic"
3875o 3
3876suid 3,0
3877)
3878)
3879uid 346,0
3880)
3881*125 (LeafLogPort
3882port (LogicalPort
3883lang 10
3884m 4
3885decl (Decl
3886n "shifting"
3887t "std_logic"
3888o 4
3889suid 4,0
3890)
3891)
3892uid 348,0
3893)
3894*126 (LeafLogPort
3895port (LogicalPort
3896lang 10
3897m 4
3898decl (Decl
3899n "ready"
3900t "std_logic"
3901o 5
3902suid 5,0
3903)
3904)
3905uid 350,0
3906)
3907*127 (LeafLogPort
3908port (LogicalPort
3909lang 10
3910m 4
3911decl (Decl
3912n "offset"
3913t "std_logic_vector"
3914b "(7 DOWNTO 0)"
3915o 6
3916suid 6,0
3917)
3918)
3919uid 352,0
3920)
3921*128 (LeafLogPort
3922port (LogicalPort
3923lang 10
3924m 4
3925decl (Decl
3926n "clk"
3927t "std_logic"
3928o 7
3929suid 7,0
3930)
3931)
3932uid 354,0
3933)
3934*129 (LeafLogPort
3935port (LogicalPort
3936lang 10
3937m 4
3938decl (Decl
3939n "PSDONE"
3940t "std_logic"
3941o 8
3942suid 8,0
3943)
3944)
3945uid 356,0
3946)
3947*130 (LeafLogPort
3948port (LogicalPort
3949lang 10
3950m 4
3951decl (Decl
3952n "LOCKED"
3953t "std_logic"
3954o 9
3955suid 9,0
3956)
3957)
3958uid 358,0
3959)
3960*131 (LeafLogPort
3961port (LogicalPort
3962lang 10
3963m 4
3964decl (Decl
3965n "shift_phase"
3966t "std_logic"
3967o 10
3968suid 10,0
3969)
3970)
3971uid 360,0
3972)
3973*132 (LeafLogPort
3974port (LogicalPort
3975lang 10
3976m 4
3977decl (Decl
3978n "direction"
3979t "std_logic"
3980o 11
3981suid 11,0
3982)
3983)
3984uid 362,0
3985)
3986*133 (LeafLogPort
3987port (LogicalPort
3988lang 10
3989m 4
3990decl (Decl
3991n "rst"
3992t "std_logic"
3993o 12
3994suid 12,0
3995)
3996)
3997uid 364,0
3998)
3999*134 (LeafLogPort
4000port (LogicalPort
4001lang 10
4002m 4
4003decl (Decl
4004n "reset_DCM"
4005t "std_logic"
4006o 13
4007suid 13,0
4008)
4009)
4010uid 366,0
4011)
4012]
4013)
4014pdm (PhysicalDM
4015displayShortBounds 1
4016editShortBounds 1
4017uid 394,0
4018optionalChildren [
4019*135 (Sheet
4020sheetRow (SheetRow
4021headerVa (MVa
4022cellColor "49152,49152,49152"
4023fontColor "0,0,0"
4024font "Tahoma,10,0"
4025)
4026cellVa (MVa
4027cellColor "65535,65535,65535"
4028fontColor "0,0,0"
4029font "Tahoma,10,0"
4030)
4031groupVa (MVa
4032cellColor "39936,56832,65280"
4033fontColor "0,0,0"
4034font "Tahoma,10,0"
4035)
4036emptyMRCItem *136 (MRCItem
4037litem &109
4038pos 13
4039dimension 20
4040)
4041uid 396,0
4042optionalChildren [
4043*137 (MRCItem
4044litem &110
4045pos 0
4046dimension 20
4047uid 397,0
4048)
4049*138 (MRCItem
4050litem &111
4051pos 1
4052dimension 23
4053uid 398,0
4054)
4055*139 (MRCItem
4056litem &112
4057pos 2
4058hidden 1
4059dimension 20
4060uid 399,0
4061)
4062*140 (MRCItem
4063litem &122
4064pos 0
4065dimension 20
4066uid 343,0
4067)
4068*141 (MRCItem
4069litem &123
4070pos 1
4071dimension 20
4072uid 345,0
4073)
4074*142 (MRCItem
4075litem &124
4076pos 2
4077dimension 20
4078uid 347,0
4079)
4080*143 (MRCItem
4081litem &125
4082pos 3
4083dimension 20
4084uid 349,0
4085)
4086*144 (MRCItem
4087litem &126
4088pos 4
4089dimension 20
4090uid 351,0
4091)
4092*145 (MRCItem
4093litem &127
4094pos 5
4095dimension 20
4096uid 353,0
4097)
4098*146 (MRCItem
4099litem &128
4100pos 6
4101dimension 20
4102uid 355,0
4103)
4104*147 (MRCItem
4105litem &129
4106pos 7
4107dimension 20
4108uid 357,0
4109)
4110*148 (MRCItem
4111litem &130
4112pos 8
4113dimension 20
4114uid 359,0
4115)
4116*149 (MRCItem
4117litem &131
4118pos 9
4119dimension 20
4120uid 361,0
4121)
4122*150 (MRCItem
4123litem &132
4124pos 10
4125dimension 20
4126uid 363,0
4127)
4128*151 (MRCItem
4129litem &133
4130pos 11
4131dimension 20
4132uid 365,0
4133)
4134*152 (MRCItem
4135litem &134
4136pos 12
4137dimension 20
4138uid 367,0
4139)
4140]
4141)
4142sheetCol (SheetCol
4143propVa (MVa
4144cellColor "0,49152,49152"
4145fontColor "0,0,0"
4146font "Tahoma,10,0"
4147textAngle 90
4148)
4149uid 400,0
4150optionalChildren [
4151*153 (MRCItem
4152litem &113
4153pos 0
4154dimension 20
4155uid 401,0
4156)
4157*154 (MRCItem
4158litem &115
4159pos 1
4160dimension 50
4161uid 402,0
4162)
4163*155 (MRCItem
4164litem &116
4165pos 2
4166dimension 100
4167uid 403,0
4168)
4169*156 (MRCItem
4170litem &117
4171pos 3
4172dimension 50
4173uid 404,0
4174)
4175*157 (MRCItem
4176litem &118
4177pos 4
4178dimension 100
4179uid 405,0
4180)
4181*158 (MRCItem
4182litem &119
4183pos 5
4184dimension 100
4185uid 406,0
4186)
4187*159 (MRCItem
4188litem &120
4189pos 6
4190dimension 50
4191uid 407,0
4192)
4193*160 (MRCItem
4194litem &121
4195pos 7
4196dimension 80
4197uid 408,0
4198)
4199]
4200)
4201fixedCol 4
4202fixedRow 2
4203name "Ports"
4204uid 395,0
4205vaOverrides [
4206]
4207)
4208]
4209)
4210uid 380,0
4211)
4212genericsCommonDM (CommonDM
4213ldm (LogicalDM
4214emptyRow *161 (LEmptyRow
4215)
4216uid 410,0
4217optionalChildren [
4218*162 (RefLabelRowHdr
4219)
4220*163 (TitleRowHdr
4221)
4222*164 (FilterRowHdr
4223)
4224*165 (RefLabelColHdr
4225tm "RefLabelColHdrMgr"
4226)
4227*166 (RowExpandColHdr
4228tm "RowExpandColHdrMgr"
4229)
4230*167 (GroupColHdr
4231tm "GroupColHdrMgr"
4232)
4233*168 (NameColHdr
4234tm "GenericNameColHdrMgr"
4235)
4236*169 (TypeColHdr
4237tm "GenericTypeColHdrMgr"
4238)
4239*170 (InitColHdr
4240tm "GenericValueColHdrMgr"
4241)
4242*171 (PragmaColHdr
4243tm "GenericPragmaColHdrMgr"
4244)
4245*172 (EolColHdr
4246tm "GenericEolColHdrMgr"
4247)
4248]
4249)
4250pdm (PhysicalDM
4251displayShortBounds 1
4252editShortBounds 1
4253uid 422,0
4254optionalChildren [
4255*173 (Sheet
4256sheetRow (SheetRow
4257headerVa (MVa
4258cellColor "49152,49152,49152"
4259fontColor "0,0,0"
4260font "Tahoma,10,0"
4261)
4262cellVa (MVa
4263cellColor "65535,65535,65535"
4264fontColor "0,0,0"
4265font "Tahoma,10,0"
4266)
4267groupVa (MVa
4268cellColor "39936,56832,65280"
4269fontColor "0,0,0"
4270font "Tahoma,10,0"
4271)
4272emptyMRCItem *174 (MRCItem
4273litem &161
4274pos 0
4275dimension 20
4276)
4277uid 424,0
4278optionalChildren [
4279*175 (MRCItem
4280litem &162
4281pos 0
4282dimension 20
4283uid 425,0
4284)
4285*176 (MRCItem
4286litem &163
4287pos 1
4288dimension 23
4289uid 426,0
4290)
4291*177 (MRCItem
4292litem &164
4293pos 2
4294hidden 1
4295dimension 20
4296uid 427,0
4297)
4298]
4299)
4300sheetCol (SheetCol
4301propVa (MVa
4302cellColor "0,49152,49152"
4303fontColor "0,0,0"
4304font "Tahoma,10,0"
4305textAngle 90
4306)
4307uid 428,0
4308optionalChildren [
4309*178 (MRCItem
4310litem &165
4311pos 0
4312dimension 20
4313uid 429,0
4314)
4315*179 (MRCItem
4316litem &167
4317pos 1
4318dimension 50
4319uid 430,0
4320)
4321*180 (MRCItem
4322litem &168
4323pos 2
4324dimension 100
4325uid 431,0
4326)
4327*181 (MRCItem
4328litem &169
4329pos 3
4330dimension 100
4331uid 432,0
4332)
4333*182 (MRCItem
4334litem &170
4335pos 4
4336dimension 50
4337uid 433,0
4338)
4339*183 (MRCItem
4340litem &171
4341pos 5
4342dimension 50
4343uid 434,0
4344)
4345*184 (MRCItem
4346litem &172
4347pos 6
4348dimension 80
4349uid 435,0
4350)
4351]
4352)
4353fixedCol 3
4354fixedRow 2
4355name "Ports"
4356uid 423,0
4357vaOverrides [
4358]
4359)
4360]
4361)
4362uid 409,0
4363type 1
4364)
4365activeModelName "BlockDiag"
4366)
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