DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
dmPackageRefs [
(DmPackageRef
library "ieee"
unitName "std_logic_1164"
itemName "ALL"
)
(DmPackageRef
library "ieee"
unitName "std_logic_arith"
itemName "ALL"
)
(DmPackageRef
library "ieee"
unitName "std_logic_unsigned"
)
]
instances [
(Instance
name "U_0"
duLibraryName "FACT_FAD_lib"
duName "spi_ltc2600"
elements [
]
mwi 0
uid 53,0
)
(Instance
name "U_1"
duLibraryName "FACT_FAD_TB_lib"
duName "spi_ltc2600_tester"
elements [
]
mwi 0
uid 151,0
)
(Instance
name "U_2"
duLibraryName "FACT_FAD_TB_lib"
duName "clock_generator"
elements [
(GiElement
name "clock_period"
type "time"
value "20 ns"
)
(GiElement
name "reset_time"
type "time"
value "50 ns"
)
]
mwi 0
uid 448,0
)
]
libraryRefs [
"ieee"
]
)
version "29.1"
appVersion "2009.2 (Build 10)"
noEmbeddedEditors 1
model (BlockDiag
VExpander (VariableExpander
vvMap [
(vvPair
variable "HDLDir"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hdl"
)
(vvPair
variable "HDSDir"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\spi_ltc2600_tb\\struct.bd.info"
)
(vvPair
variable "SideDataUserDir"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\spi_ltc2600_tb\\struct.bd.user"
)
(vvPair
variable "SourceDir"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "struct"
)
(vvPair
variable "config"
value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\spi_ltc2600_tb"
)
(vvPair
variable "d_logical"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\spi_ltc2600_tb"
)
(vvPair
variable "date"
value "03.02.2011"
)
(vvPair
variable "day"
value "Do"
)
(vvPair
variable "day_long"
value "Donnerstag"
)
(vvPair
variable "dd"
value "03"
)
(vvPair
variable "entity_name"
value "spi_ltc2600_tb"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "struct.bd"
)
(vvPair
variable "f_logical"
value "struct.bd"
)
(vvPair
variable "f_noext"
value "struct"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "E5B-LABOR6"
)
(vvPair
variable "language"
value "VHDL"
)
(vvPair
variable "library"
value "FACT_FAD_TB_lib"
)
(vvPair
variable "library_downstream_ISEPARInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
)
(vvPair
variable "library_downstream_ImpactInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/work"
)
(vvPair
variable "library_downstream_XSTDataPrep"
value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
)
(vvPair
variable "mm"
value "02"
)
(vvPair
variable "module_name"
value "spi_ltc2600_tb"
)
(vvPair
variable "month"
value "Feb"
)
(vvPair
variable "month_long"
value "Februar"
)
(vvPair
variable "p"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\spi_ltc2600_tb\\struct.bd"
)
(vvPair
variable "p_logical"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\spi_ltc2600_tb\\struct.bd"
)
(vvPair
variable "package_name"
value "<Undefined Variable>"
)
(vvPair
variable "project_name"
value "FACT_FAD"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "C:\\modeltech_6.6a\\win32"
)
(vvPair
variable "task_NC-SimPath"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
)
(vvPair
variable "task_QuestaSimPath"
value "<TBD>"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "this_ext"
value "bd"
)
(vvPair
variable "this_file"
value "struct"
)
(vvPair
variable "this_file_logical"
value "struct"
)
(vvPair
variable "time"
value "20:11:18"
)
(vvPair
variable "unit"
value "spi_ltc2600_tb"
)
(vvPair
variable "user"
value "dneise"
)
(vvPair
variable "version"
value "2009.2 (Build 10)"
)
(vvPair
variable "view"
value "struct"
)
(vvPair
variable "year"
value "2011"
)
(vvPair
variable "yy"
value "11"
)
]
)
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ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
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thePort (LogicalPort
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n "clk"
t "std_logic"
o 1
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)
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ps "OnEdgeStrategy"
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thePort (LogicalPort
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decl (Decl
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b "(15 downto 0)"
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ps "OnEdgeStrategy"
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ro 90
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portVis (PortSigDisplay
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oxt "14000,68000,18000,69000"
text (MLText
uid 262,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "22200,46000,24300,47000"
st "
Title:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*36 (CommentText
uid 263,0
shape (Rectangle
uid 264,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "43000,45000,63000,49000"
)
oxt "35000,67000,55000,71000"
text (MLText
uid 265,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "43200,45200,52400,46200"
st "
<enter comments here>
"
tm "CommentText"
wrapOption 3
visibleHeight 4000
visibleWidth 20000
)
ignorePrefs 1
titleBlock 1
)
*37 (CommentText
uid 266,0
shape (Rectangle
uid 267,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "47000,44000,63000,45000"
)
oxt "39000,66000,55000,67000"
text (MLText
uid 268,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "47200,44000,51700,45000"
st "
%project_name
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 16000
)
position 1
ignorePrefs 1
titleBlock 1
)
*38 (CommentText
uid 269,0
shape (Rectangle
uid 270,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "22000,44000,43000,46000"
)
oxt "14000,66000,35000,68000"
text (MLText
uid 271,0
va (VaSet
fg "32768,0,0"
)
xt "29150,44500,35850,45500"
st "
<company name>
"
ju 0
tm "CommentText"
wrapOption 3
visibleHeight 2000
visibleWidth 21000
)
position 1
ignorePrefs 1
titleBlock 1
)
*39 (CommentText
uid 272,0
shape (Rectangle
uid 273,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "22000,47000,26000,48000"
)
oxt "14000,69000,18000,70000"
text (MLText
uid 274,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "22200,47000,24300,48000"
st "
Path:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*40 (CommentText
uid 275,0
shape (Rectangle
uid 276,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "22000,48000,26000,49000"
)
oxt "14000,70000,18000,71000"
text (MLText
uid 277,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "22200,48000,24900,49000"
st "
Edited:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*41 (CommentText
uid 278,0
shape (Rectangle
uid 279,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "26000,47000,43000,48000"
)
oxt "18000,69000,35000,70000"
text (MLText
uid 280,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "26200,47000,41200,48000"
st "
%library/%unit/%view
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
titleBlock 1
)
]
shape (GroupingShape
uid 250,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
lineWidth 2
)
xt "22000,44000,63000,49000"
)
oxt "14000,66000,55000,71000"
)
*42 (SaComponent
uid 448,0
optionalChildren [
*43 (CptPort
uid 437,0
ps "OnEdgeStrategy"
shape (Triangle
uid 438,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "10000,30625,10750,31375"
)
tg (CPTG
uid 439,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 440,0
va (VaSet
)
xt "7700,30500,9000,31500"
st "clk"
ju 2
blo "9000,31300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "clk"
t "std_logic"
preAdd 0
posAdd 0
o 1
suid 1,0
i "'0'"
)
)
)
*44 (CptPort
uid 441,0
ps "OnEdgeStrategy"
shape (Triangle
uid 442,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "10000,31625,10750,32375"
)
tg (CPTG
uid 443,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 444,0
va (VaSet
)
xt "7700,31500,9000,32500"
st "rst"
ju 2
blo "9000,32300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "rst"
t "std_logic"
preAdd 0
posAdd 0
o 2
suid 2,0
i "'0'"
)
)
)
]
shape (Rectangle
uid 449,0
va (VaSet
vasetType 1
fg "0,49152,49152"
lineColor "0,0,50000"
lineWidth 2
)
xt "2000,30000,10000,34000"
)
oxt "22000,15000,30000,19000"
ttg (MlTextGroup
uid 450,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*45 (Text
uid 451,0
va (VaSet
font "Arial,8,1"
)
xt "2150,34000,9850,35000"
st "FACT_FAD_TB_lib"
blo "2150,34800"
tm "BdLibraryNameMgr"
)
*46 (Text
uid 452,0
va (VaSet
font "Arial,8,1"
)
xt "2150,35000,8850,36000"
st "clock_generator"
blo "2150,35800"
tm "CptNameMgr"
)
*47 (Text
uid 453,0
va (VaSet
font "Arial,8,1"
)
xt "2150,36000,3950,37000"
st "U_2"
blo "2150,36800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 454,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 455,0
text (MLText
uid 456,0
va (VaSet
font "Courier New,8,0"
)
xt "-1000,28400,17500,30000"
st "clock_period = 20 ns    ( time )  
reset_time   = 50 ns    ( time )  "
)
header ""
)
elements [
(GiElement
name "clock_period"
type "time"
value "20 ns"
)
(GiElement
name "reset_time"
type "time"
value "50 ns"
)
]
)
viewicon (ZoomableIcon
uid 457,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "2250,32250,3750,33750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*48 (Wire
uid 65,0
shape (OrthoPolyLine
uid 66,0
va (VaSet
vasetType 3
)
xt "12750,15000,17000,15000"
pts [
"12750,15000"
"17000,15000"
]
)
start &3
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 69,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 70,0
va (VaSet
)
xt "14000,14000,16400,15000"
st "SCLK"
blo "14000,14800"
tm "WireNameMgr"
)
)
on &16
)
*49 (Wire
uid 73,0
shape (OrthoPolyLine
uid 74,0
va (VaSet
vasetType 3
)
xt "12750,16000,17000,16000"
pts [
"12750,16000"
"17000,16000"
]
)
start &4
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 77,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 78,0
va (VaSet
)
xt "14000,15000,15500,16000"
st "CS"
blo "14000,15800"
tm "WireNameMgr"
)
)
on &17
)
*50 (Wire
uid 81,0
shape (OrthoPolyLine
uid 82,0
va (VaSet
vasetType 3
)
xt "12750,17000,17000,17000"
pts [
"12750,17000"
"17000,17000"
]
)
start &5
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 85,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 86,0
va (VaSet
)
xt "14000,16000,16400,17000"
st "MOSI"
blo "14000,16800"
tm "WireNameMgr"
)
)
on &18
)
*51 (Wire
uid 89,0
shape (OrthoPolyLine
uid 90,0
va (VaSet
vasetType 3
)
xt "12750,18000,17000,18000"
pts [
"12750,18000"
"17000,18000"
]
)
start &6
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 93,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 94,0
va (VaSet
)
xt "14000,17000,16400,18000"
st "MISO"
blo "14000,17800"
tm "WireNameMgr"
)
)
on &19
)
*52 (Wire
uid 97,0
shape (OrthoPolyLine
uid 98,0
va (VaSet
vasetType 3
)
xt "12750,19000,17000,19000"
pts [
"12750,19000"
"17000,19000"
]
)
start &11
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 101,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 102,0
va (VaSet
)
xt "14000,18000,16200,19000"
st "ready"
blo "14000,18800"
tm "WireNameMgr"
)
)
on &20
)
*53 (Wire
uid 105,0
shape (OrthoPolyLine
uid 106,0
va (VaSet
vasetType 3
)
xt "12750,20000,17000,20000"
pts [
"12750,20000"
"17000,20000"
]
)
start &12
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 109,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 110,0
va (VaSet
)
xt "14000,19000,15900,20000"
st "busy"
blo "14000,19800"
tm "WireNameMgr"
)
)
on &21
)
*54 (Wire
uid 113,0
shape (OrthoPolyLine
uid 114,0
va (VaSet
vasetType 3
)
xt "-9000,15000,-750,15000"
pts [
"-9000,15000"
"-750,15000"
]
)
end &2
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 117,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 118,0
va (VaSet
)
xt "-8000,14000,-6700,15000"
st "clk"
blo "-8000,14800"
tm "WireNameMgr"
)
)
on &22
)
*55 (Wire
uid 121,0
shape (OrthoPolyLine
uid 122,0
va (VaSet
vasetType 3
)
xt "-9000,16000,-750,16000"
pts [
"-9000,16000"
"-750,16000"
]
)
end &7
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 125,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 126,0
va (VaSet
)
xt "-8000,15000,-4900,16000"
st "transmit"
blo "-8000,15800"
tm "WireNameMgr"
)
)
on &23
)
*56 (Wire
uid 129,0
shape (OrthoPolyLine
uid 130,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-9000,17000,-750,17000"
pts [
"-9000,17000"
"-750,17000"
]
)
end &8
sat 16
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 133,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 134,0
va (VaSet
)
xt "-8000,16000,-1800,17000"
st "command : (3:0)"
blo "-8000,16800"
tm "WireNameMgr"
)
)
on &24
)
*57 (Wire
uid 137,0
shape (OrthoPolyLine
uid 138,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-9000,18000,-750,18000"
pts [
"-9000,18000"
"-750,18000"
]
)
end &9
sat 16
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 141,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 142,0
va (VaSet
)
xt "-8000,17000,-2300,18000"
st "address : (3:0)"
blo "-8000,17800"
tm "WireNameMgr"
)
)
on &25
)
*58 (Wire
uid 145,0
shape (OrthoPolyLine
uid 146,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-9000,19000,-750,19000"
pts [
"-9000,19000"
"-750,19000"
]
)
end &10
sat 16
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 149,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 150,0
va (VaSet
)
xt "-8000,18000,-3200,19000"
st "data : (15:0)"
blo "-8000,18800"
tm "WireNameMgr"
)
)
on &26
)
*59 (Wire
uid 161,0
shape (OrthoPolyLine
uid 162,0
va (VaSet
vasetType 3
)
xt "42000,17000,47000,17000"
pts [
"42000,17000"
"47000,17000"
]
)
start &27
sat 1
eat 16
st 0
sf 1
si 0
tg (WTG
uid 167,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 168,0
va (VaSet
)
xt "44000,16000,46400,17000"
st "MOSI"
blo "44000,16800"
tm "WireNameMgr"
)
)
on &18
)
*60 (Wire
uid 169,0
shape (OrthoPolyLine
uid 170,0
va (VaSet
vasetType 3
)
xt "42000,20000,47000,20000"
pts [
"42000,20000"
"47000,20000"
]
)
start &27
sat 1
eat 16
st 0
sf 1
si 0
tg (WTG
uid 175,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 176,0
va (VaSet
)
xt "44000,19000,45900,20000"
st "busy"
blo "44000,19800"
tm "WireNameMgr"
)
)
on &21
)
*61 (Wire
uid 177,0
shape (OrthoPolyLine
uid 178,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "21000,18000,30000,18000"
pts [
"21000,18000"
"30000,18000"
]
)
end &27
sat 16
eat 2
sty 1
st 0
sf 1
si 0
tg (WTG
uid 183,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 184,0
va (VaSet
)
xt "22000,17000,27700,18000"
st "address : (3:0)"
blo "22000,17800"
tm "WireNameMgr"
)
)
on &25
)
*62 (Wire
uid 185,0
shape (OrthoPolyLine
uid 186,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "21000,17000,30000,17000"
pts [
"21000,17000"
"30000,17000"
]
)
end &27
sat 16
eat 2
sty 1
st 0
sf 1
si 0
tg (WTG
uid 191,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 192,0
va (VaSet
)
xt "22000,16000,28200,17000"
st "command : (3:0)"
blo "22000,16800"
tm "WireNameMgr"
)
)
on &24
)
*63 (Wire
uid 193,0
shape (OrthoPolyLine
uid 194,0
va (VaSet
vasetType 3
)
xt "21000,16000,30000,16000"
pts [
"21000,16000"
"30000,16000"
]
)
end &27
sat 16
eat 2
st 0
sf 1
si 0
tg (WTG
uid 199,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 200,0
va (VaSet
)
xt "22000,15000,25100,16000"
st "transmit"
blo "22000,15800"
tm "WireNameMgr"
)
)
on &23
)
*64 (Wire
uid 201,0
shape (OrthoPolyLine
uid 202,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "21000,19000,30000,19000"
pts [
"21000,19000"
"30000,19000"
]
)
end &27
sat 16
eat 2
sty 1
st 0
sf 1
si 0
tg (WTG
uid 207,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 208,0
va (VaSet
)
xt "22000,18000,26800,19000"
st "data : (15:0)"
blo "22000,18800"
tm "WireNameMgr"
)
)
on &26
)
*65 (Wire
uid 209,0
shape (OrthoPolyLine
uid 210,0
va (VaSet
vasetType 3
)
xt "42000,19000,47000,19000"
pts [
"42000,19000"
"47000,19000"
]
)
start &27
sat 1
eat 16
st 0
sf 1
si 0
tg (WTG
uid 215,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 216,0
va (VaSet
)
xt "44000,18000,46200,19000"
st "ready"
blo "44000,18800"
tm "WireNameMgr"
)
)
on &20
)
*66 (Wire
uid 217,0
shape (OrthoPolyLine
uid 218,0
va (VaSet
vasetType 3
)
xt "42000,15000,47000,15000"
pts [
"42000,15000"
"47000,15000"
]
)
start &27
sat 1
eat 16
st 0
sf 1
si 0
tg (WTG
uid 223,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 224,0
va (VaSet
)
xt "44000,14000,46400,15000"
st "SCLK"
blo "44000,14800"
tm "WireNameMgr"
)
)
on &16
)
*67 (Wire
uid 233,0
shape (OrthoPolyLine
uid 234,0
va (VaSet
vasetType 3
)
xt "42000,16000,47000,16000"
pts [
"42000,16000"
"47000,16000"
]
)
start &27
sat 1
eat 16
st 0
sf 1
si 0
tg (WTG
uid 239,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 240,0
va (VaSet
)
xt "43000,15000,44500,16000"
st "CS"
blo "43000,15800"
tm "WireNameMgr"
)
)
on &17
)
*68 (Wire
uid 241,0
shape (OrthoPolyLine
uid 242,0
va (VaSet
vasetType 3
)
xt "42000,18000,47000,18000"
pts [
"42000,18000"
"47000,18000"
]
)
start &27
sat 1
eat 16
st 0
sf 1
si 0
tg (WTG
uid 247,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 248,0
va (VaSet
)
xt "44000,17000,46400,18000"
st "MISO"
blo "44000,17800"
tm "WireNameMgr"
)
)
on &19
)
*69 (Wire
uid 468,0
shape (OrthoPolyLine
uid 469,0
va (VaSet
vasetType 3
)
xt "10750,31000,14000,31000"
pts [
"10750,31000"
"14000,31000"
]
)
start &43
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 472,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 473,0
va (VaSet
)
xt "12000,30000,13300,31000"
st "clk"
blo "12000,30800"
tm "WireNameMgr"
)
)
on &22
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 1
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *70 (PackageList
uid 303,0
stg "VerticalLayoutStrategy"
textVec [
*71 (Text
uid 304,0
va (VaSet
font "arial,8,1"
)
xt "0,0,5400,1000"
st "Package List"
blo "0,800"
)
*72 (MLText
uid 305,0
va (VaSet
)
xt "0,1000,12400,5000"
st "LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.all;"
tm "PackageList"
)
]
)
compDirBlock (MlTextGroup
uid 306,0
stg "VerticalLayoutStrategy"
textVec [
*73 (Text
uid 307,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,0,28100,1000"
st "Compiler Directives"
blo "20000,800"
)
*74 (Text
uid 308,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,1000,29600,2000"
st "Pre-module directives:"
blo "20000,1800"
)
*75 (MLText
uid 309,0
va (VaSet
isHidden 1
)
xt "20000,2000,27500,4000"
st "`resetall
`timescale 1ns/10ps"
tm "BdCompilerDirectivesTextMgr"
)
*76 (Text
uid 310,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,4000,30100,5000"
st "Post-module directives:"
blo "20000,4800"
)
*77 (MLText
uid 311,0
va (VaSet
isHidden 1
)
xt "20000,0,20000,0"
tm "BdCompilerDirectivesTextMgr"
)
*78 (Text
uid 312,0
va (VaSet
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