source: firmware/FAD/FACT_FAD_TB_lib/hds/timer_tb/struct.bd.bak@ 17033

Last change on this file since 17033 was 11755, checked in by neise, 13 years ago
reinit of this svn repos .... it was all too messy deleted the old folders and restarted with FACT_FAD_lib only. (well and the testbenches)
File size: 46.2 KB
Line 
1DocumentHdrVersion "1.1"
2Header (DocumentHdr
3version 2
4dmPackageRefs [
5(DmPackageRef
6library "ieee"
7unitName "std_logic_1164"
8itemName "ALL"
9)
10(DmPackageRef
11library "ieee"
12unitName "std_logic_arith"
13itemName "ALL"
14)
15(DmPackageRef
16library "ieee"
17unitName "std_logic_unsigned"
18)
19]
20instances [
21(Instance
22name "U_0"
23duLibraryName "FACT_FAD_lib"
24duName "timer"
25elements [
26(GiElement
27name "TIMER_WIDTH"
28type "integer"
29value "32"
30)
31(GiElement
32name "PRESCALER"
33type "integer"
34value "5000"
35)
36]
37mwi 0
38uid 534,0
39)
40(Instance
41name "U_1"
42duLibraryName "FACT_FAD_TB_lib"
43duName "timer_tester"
44elements [
45]
46mwi 0
47uid 604,0
48)
49(Instance
50name "U_2"
51duLibraryName "FACT_FAD_TB_lib"
52duName "clock_generator"
53elements [
54(GiElement
55name "clock_period"
56type "time"
57value "20 ns"
58)
59(GiElement
60name "reset_time"
61type "time"
62value "50 ns"
63)
64]
65mwi 0
66uid 645,0
67)
68]
69libraryRefs [
70"ieee"
71]
72)
73version "29.1"
74appVersion "2009.2 (Build 10)"
75noEmbeddedEditors 1
76model (BlockDiag
77VExpander (VariableExpander
78vvMap [
79(vvPair
80variable "HDLDir"
81value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hdl"
82)
83(vvPair
84variable "HDSDir"
85value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
86)
87(vvPair
88variable "SideDataDesignDir"
89value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\timer_tb\\struct.bd.info"
90)
91(vvPair
92variable "SideDataUserDir"
93value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\timer_tb\\struct.bd.user"
94)
95(vvPair
96variable "SourceDir"
97value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
98)
99(vvPair
100variable "appl"
101value "HDL Designer"
102)
103(vvPair
104variable "arch_name"
105value "struct"
106)
107(vvPair
108variable "config"
109value "%(unit)_%(view)_config"
110)
111(vvPair
112variable "d"
113value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\timer_tb"
114)
115(vvPair
116variable "d_logical"
117value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\timer_tb"
118)
119(vvPair
120variable "date"
121value "23.02.2011"
122)
123(vvPair
124variable "day"
125value "Mi"
126)
127(vvPair
128variable "day_long"
129value "Mittwoch"
130)
131(vvPair
132variable "dd"
133value "23"
134)
135(vvPair
136variable "entity_name"
137value "timer_tb"
138)
139(vvPair
140variable "ext"
141value "<TBD>"
142)
143(vvPair
144variable "f"
145value "struct.bd"
146)
147(vvPair
148variable "f_logical"
149value "struct.bd"
150)
151(vvPair
152variable "f_noext"
153value "struct"
154)
155(vvPair
156variable "group"
157value "UNKNOWN"
158)
159(vvPair
160variable "host"
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162)
163(vvPair
164variable "language"
165value "VHDL"
166)
167(vvPair
168variable "library"
169value "FACT_FAD_TB_lib"
170)
171(vvPair
172variable "library_downstream_HdsLintPlugin"
173value "$HDS_PROJECT_DIR\\FACT_FAD_TB_lib\\designcheck"
174)
175(vvPair
176variable "library_downstream_ISEPARInvoke"
177value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
178)
179(vvPair
180variable "library_downstream_ImpactInvoke"
181value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
182)
183(vvPair
184variable "library_downstream_ModelSimCompiler"
185value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/work"
186)
187(vvPair
188variable "library_downstream_XSTDataPrep"
189value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
190)
191(vvPair
192variable "mm"
193value "02"
194)
195(vvPair
196variable "module_name"
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198)
199(vvPair
200variable "month"
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202)
203(vvPair
204variable "month_long"
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206)
207(vvPair
208variable "p"
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210)
211(vvPair
212variable "p_logical"
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214)
215(vvPair
216variable "package_name"
217value "<Undefined Variable>"
218)
219(vvPair
220variable "project_name"
221value "FACT_FAD"
222)
223(vvPair
224variable "series"
225value "HDL Designer Series"
226)
227(vvPair
228variable "task_DesignCompilerPath"
229value "<TBD>"
230)
231(vvPair
232variable "task_LeonardoPath"
233value "<TBD>"
234)
235(vvPair
236variable "task_ModelSimPath"
237value "C:\\modeltech_6.6a\\win32"
238)
239(vvPair
240variable "task_NC-SimPath"
241value "<TBD>"
242)
243(vvPair
244variable "task_PrecisionRTLPath"
245value "<TBD>"
246)
247(vvPair
248variable "task_QuestaSimPath"
249value "<TBD>"
250)
251(vvPair
252variable "task_VCSPath"
253value "<TBD>"
254)
255(vvPair
256variable "this_ext"
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258)
259(vvPair
260variable "this_file"
261value "struct"
262)
263(vvPair
264variable "this_file_logical"
265value "struct"
266)
267(vvPair
268variable "time"
269value "12:23:40"
270)
271(vvPair
272variable "unit"
273value "timer_tb"
274)
275(vvPair
276variable "user"
277value "dneise"
278)
279(vvPair
280variable "version"
281value "2009.2 (Build 10)"
282)
283(vvPair
284variable "view"
285value "struct"
286)
287(vvPair
288variable "year"
289value "2011"
290)
291(vvPair
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293value "11"
294)
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296)
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979)
980viewicon (ZoomableIcon
981uid 543,0
982sl 0
983va (VaSet
984vasetType 1
985fg "49152,49152,49152"
986)
987xt "9250,16250,10750,17750"
988iconName "VhdlFileViewIcon.png"
989iconMaskName "VhdlFileViewIcon.msk"
990ftype 10
991)
992ordering 1
993viewiconposition 0
994portVis (PortSigDisplay
995)
996archFileType "UNKNOWN"
997)
998*26 (Net
999uid 544,0
1000decl (Decl
1001n "clk"
1002t "std_logic"
1003o 5
1004suid 8,0
1005)
1006declText (MLText
1007uid 545,0
1008va (VaSet
1009font "Courier New,8,0"
1010)
1011xt "22000,3000,39500,3800"
1012st "SIGNAL clk : std_logic"
1013)
1014)
1015*27 (Net
1016uid 558,0
1017decl (Decl
1018n "reset_synch_i"
1019t "std_logic"
1020o 6
1021suid 9,0
1022)
1023declText (MLText
1024uid 559,0
1025va (VaSet
1026font "Courier New,8,0"
1027)
1028xt "22000,4600,39500,5400"
1029st "SIGNAL reset_synch_i : std_logic"
1030)
1031)
1032*28 (SaComponent
1033uid 604,0
1034optionalChildren [
1035*29 (CptPort
1036uid 588,0
1037ps "OnEdgeStrategy"
1038shape (Triangle
1039uid 589,0
1040ro 270
1041va (VaSet
1042vasetType 1
1043fg "0,65535,0"
1044)
1045xt "15250,29625,16000,30375"
1046)
1047tg (CPTG
1048uid 590,0
1049ps "CptPortTextPlaceStrategy"
1050stg "VerticalLayoutStrategy"
1051f (Text
1052uid 591,0
1053va (VaSet
1054)
1055xt "17000,29500,20200,30500"
1056st "enable_i"
1057blo "17000,30300"
1058)
1059)
1060thePort (LogicalPort
1061lang 10
1062m 1
1063decl (Decl
1064n "enable_i"
1065t "std_logic"
1066o 3
1067suid 16,0
1068)
1069)
1070)
1071*30 (CptPort
1072uid 592,0
1073ps "OnEdgeStrategy"
1074shape (Triangle
1075uid 593,0
1076ro 270
1077va (VaSet
1078vasetType 1
1079fg "0,65535,0"
1080)
1081xt "15250,28625,16000,29375"
1082)
1083tg (CPTG
1084uid 594,0
1085ps "CptPortTextPlaceStrategy"
1086stg "VerticalLayoutStrategy"
1087f (Text
1088uid 595,0
1089va (VaSet
1090)
1091xt "17000,28500,19900,29500"
1092st "synch_i"
1093blo "17000,29300"
1094)
1095)
1096thePort (LogicalPort
1097lang 10
1098m 1
1099decl (Decl
1100n "synch_i"
1101t "std_logic"
1102o 6
1103suid 17,0
1104)
1105)
1106)
1107*31 (CptPort
1108uid 596,0
1109ps "OnEdgeStrategy"
1110shape (Triangle
1111uid 597,0
1112ro 270
1113va (VaSet
1114vasetType 1
1115fg "0,65535,0"
1116)
1117xt "34000,28625,34750,29375"
1118)
1119tg (CPTG
1120uid 598,0
1121ps "CptPortTextPlaceStrategy"
1122stg "RightVerticalLayoutStrategy"
1123f (Text
1124uid 599,0
1125va (VaSet
1126)
1127xt "29100,28500,33000,29500"
1128st "synched_o"
1129ju 2
1130blo "33000,29300"
1131)
1132)
1133thePort (LogicalPort
1134lang 10
1135decl (Decl
1136n "synched_o"
1137t "std_logic"
1138o 1
1139suid 18,0
1140)
1141)
1142)
1143*32 (CptPort
1144uid 600,0
1145ps "OnEdgeStrategy"
1146shape (Triangle
1147uid 601,0
1148ro 270
1149va (VaSet
1150vasetType 1
1151fg "0,65535,0"
1152)
1153xt "34000,27625,34750,28375"
1154)
1155tg (CPTG
1156uid 602,0
1157ps "CptPortTextPlaceStrategy"
1158stg "RightVerticalLayoutStrategy"
1159f (Text
1160uid 603,0
1161va (VaSet
1162)
1163xt "30400,27500,33000,28500"
1164st "time_o"
1165ju 2
1166blo "33000,28300"
1167)
1168)
1169thePort (LogicalPort
1170lang 10
1171decl (Decl
1172n "time_o"
1173t "std_logic_vector"
1174b "( 31 DOWNTO 0)"
1175o 2
1176suid 19,0
1177)
1178)
1179)
1180*33 (CptPort
1181uid 614,0
1182ps "OnEdgeStrategy"
1183shape (Triangle
1184uid 615,0
1185ro 90
1186va (VaSet
1187vasetType 1
1188fg "0,65535,0"
1189)
1190xt "34000,29625,34750,30375"
1191)
1192tg (CPTG
1193uid 616,0
1194ps "CptPortTextPlaceStrategy"
1195stg "RightVerticalLayoutStrategy"
1196f (Text
1197uid 617,0
1198va (VaSet
1199)
1200xt "31700,29500,33000,30500"
1201st "clk"
1202ju 2
1203blo "33000,30300"
1204)
1205)
1206thePort (LogicalPort
1207lang 10
1208m 1
1209decl (Decl
1210n "clk"
1211t "std_logic"
1212o 5
1213)
1214)
1215)
1216*34 (CptPort
1217uid 618,0
1218ps "OnEdgeStrategy"
1219shape (Triangle
1220uid 619,0
1221ro 90
1222va (VaSet
1223vasetType 1
1224fg "0,65535,0"
1225)
1226xt "34000,30625,34750,31375"
1227)
1228tg (CPTG
1229uid 620,0
1230ps "CptPortTextPlaceStrategy"
1231stg "RightVerticalLayoutStrategy"
1232f (Text
1233uid 621,0
1234va (VaSet
1235)
1236xt "27600,30500,33000,31500"
1237st "reset_synch_i"
1238ju 2
1239blo "33000,31300"
1240)
1241)
1242thePort (LogicalPort
1243lang 10
1244m 1
1245decl (Decl
1246n "reset_synch_i"
1247t "std_logic"
1248o 4
1249)
1250)
1251)
1252]
1253shape (Rectangle
1254uid 605,0
1255va (VaSet
1256vasetType 1
1257fg "0,65535,0"
1258lineColor "0,32896,0"
1259lineWidth 2
1260)
1261xt "16000,27000,34000,32000"
1262)
1263oxt "15000,6000,33000,10000"
1264ttg (MlTextGroup
1265uid 606,0
1266ps "CenterOffsetStrategy"
1267stg "VerticalLayoutStrategy"
1268textVec [
1269*35 (Text
1270uid 607,0
1271va (VaSet
1272font "Arial,8,1"
1273)
1274xt "21150,28000,28850,29000"
1275st "FACT_FAD_TB_lib"
1276blo "21150,28800"
1277tm "BdLibraryNameMgr"
1278)
1279*36 (Text
1280uid 608,0
1281va (VaSet
1282font "Arial,8,1"
1283)
1284xt "21150,29000,26350,30000"
1285st "timer_tester"
1286blo "21150,29800"
1287tm "CptNameMgr"
1288)
1289*37 (Text
1290uid 609,0
1291va (VaSet
1292font "Arial,8,1"
1293)
1294xt "21150,30000,22950,31000"
1295st "U_1"
1296blo "21150,30800"
1297tm "InstanceNameMgr"
1298)
1299]
1300)
1301ga (GenericAssociation
1302uid 610,0
1303ps "EdgeToEdgeStrategy"
1304matrix (Matrix
1305uid 611,0
1306text (MLText
1307uid 612,0
1308va (VaSet
1309font "Courier New,8,0"
1310)
1311xt "1000,25800,1000,25800"
1312)
1313header ""
1314)
1315elements [
1316]
1317)
1318viewicon (ZoomableIcon
1319uid 613,0
1320sl 0
1321va (VaSet
1322vasetType 1
1323fg "49152,49152,49152"
1324)
1325xt "16250,30250,17750,31750"
1326iconName "VhdlFileViewIcon.png"
1327iconMaskName "VhdlFileViewIcon.msk"
1328ftype 10
1329)
1330ordering 1
1331viewiconposition 0
1332portVis (PortSigDisplay
1333sTC 0
1334sF 0
1335)
1336archFileType "UNKNOWN"
1337)
1338*38 (SaComponent
1339uid 645,0
1340optionalChildren [
1341*39 (CptPort
1342uid 634,0
1343ps "OnEdgeStrategy"
1344shape (Triangle
1345uid 635,0
1346ro 90
1347va (VaSet
1348vasetType 1
1349fg "0,65535,0"
1350)
1351xt "13000,37625,13750,38375"
1352)
1353tg (CPTG
1354uid 636,0
1355ps "CptPortTextPlaceStrategy"
1356stg "RightVerticalLayoutStrategy"
1357f (Text
1358uid 637,0
1359va (VaSet
1360)
1361xt "10700,37500,12000,38500"
1362st "clk"
1363ju 2
1364blo "12000,38300"
1365)
1366)
1367thePort (LogicalPort
1368m 1
1369decl (Decl
1370n "clk"
1371t "std_logic"
1372preAdd 0
1373posAdd 0
1374o 1
1375suid 1,0
1376i "'0'"
1377)
1378)
1379)
1380*40 (CptPort
1381uid 638,0
1382ps "OnEdgeStrategy"
1383shape (Triangle
1384uid 639,0
1385ro 90
1386va (VaSet
1387vasetType 1
1388fg "0,65535,0"
1389)
1390xt "13000,38625,13750,39375"
1391)
1392tg (CPTG
1393uid 640,0
1394ps "CptPortTextPlaceStrategy"
1395stg "RightVerticalLayoutStrategy"
1396f (Text
1397uid 641,0
1398va (VaSet
1399)
1400xt "10700,38500,12000,39500"
1401st "rst"
1402ju 2
1403blo "12000,39300"
1404)
1405)
1406thePort (LogicalPort
1407m 1
1408decl (Decl
1409n "rst"
1410t "std_logic"
1411preAdd 0
1412posAdd 0
1413o 2
1414suid 2,0
1415i "'0'"
1416)
1417)
1418)
1419*41 (CommentText
1420uid 642,0
1421ps "EdgeToEdgeStrategy"
1422shape (Rectangle
1423uid 643,0
1424layer 0
1425va (VaSet
1426vasetType 1
1427fg "65280,65280,46080"
1428lineColor "0,0,32768"
1429)
1430xt "4500,26000,19500,30000"
1431)
1432oxt "21500,4000,36500,8000"
1433text (MLText
1434uid 644,0
1435va (VaSet
1436fg "0,0,32768"
1437)
1438xt "4700,26200,14500,27200"
1439st "
1440-- synthesis translate_off
1441"
1442tm "CommentText"
1443wrapOption 3
1444visibleHeight 4000
1445visibleWidth 15000
1446)
1447included 1
1448excludeCommentLeader 1
1449)
1450]
1451shape (Rectangle
1452uid 646,0
1453va (VaSet
1454vasetType 1
1455fg "0,49152,49152"
1456lineColor "0,0,50000"
1457lineWidth 2
1458)
1459xt "5000,37000,13000,41000"
1460)
1461oxt "22000,15000,30000,19000"
1462ttg (MlTextGroup
1463uid 647,0
1464ps "CenterOffsetStrategy"
1465stg "VerticalLayoutStrategy"
1466textVec [
1467*42 (Text
1468uid 648,0
1469va (VaSet
1470font "Arial,8,1"
1471)
1472xt "5150,41000,12850,42000"
1473st "FACT_FAD_TB_lib"
1474blo "5150,41800"
1475tm "BdLibraryNameMgr"
1476)
1477*43 (Text
1478uid 649,0
1479va (VaSet
1480font "Arial,8,1"
1481)
1482xt "5150,42000,11850,43000"
1483st "clock_generator"
1484blo "5150,42800"
1485tm "CptNameMgr"
1486)
1487*44 (Text
1488uid 650,0
1489va (VaSet
1490font "Arial,8,1"
1491)
1492xt "5150,43000,6950,44000"
1493st "U_2"
1494blo "5150,43800"
1495tm "InstanceNameMgr"
1496)
1497]
1498)
1499ga (GenericAssociation
1500uid 651,0
1501ps "EdgeToEdgeStrategy"
1502matrix (Matrix
1503uid 652,0
1504text (MLText
1505uid 653,0
1506va (VaSet
1507font "Courier New,8,0"
1508)
1509xt "4500,28400,23000,30000"
1510st "clock_period = 20 ns ( time )
1511reset_time = 50 ns ( time )
1512"
1513)
1514header ""
1515)
1516elements [
1517(GiElement
1518name "clock_period"
1519type "time"
1520value "20 ns"
1521)
1522(GiElement
1523name "reset_time"
1524type "time"
1525value "50 ns"
1526)
1527]
1528)
1529viewicon (ZoomableIcon
1530uid 654,0
1531sl 0
1532va (VaSet
1533vasetType 1
1534fg "49152,49152,49152"
1535)
1536xt "5250,39250,6750,40750"
1537iconName "VhdlFileViewIcon.png"
1538iconMaskName "VhdlFileViewIcon.msk"
1539ftype 10
1540)
1541ordering 1
1542viewiconposition 0
1543portVis (PortSigDisplay
1544)
1545archFileType "UNKNOWN"
1546)
1547*45 (Wire
1548uid 93,0
1549shape (OrthoPolyLine
1550uid 94,0
1551va (VaSet
1552vasetType 3
1553)
1554xt "10000,30000,15250,30000"
1555pts [
1556"10000,30000"
1557"15250,30000"
1558]
1559)
1560end &29
1561sat 16
1562eat 32
1563st 0
1564sf 1
1565si 0
1566tg (WTG
1567uid 99,0
1568ps "ConnStartEndStrategy"
1569stg "STSignalDisplayStrategy"
1570f (Text
1571uid 100,0
1572va (VaSet
1573)
1574xt "11000,29000,14200,30000"
1575st "enable_i"
1576blo "11000,29800"
1577tm "WireNameMgr"
1578)
1579)
1580on &4
1581)
1582*46 (Wire
1583uid 109,0
1584shape (OrthoPolyLine
1585uid 110,0
1586va (VaSet
1587vasetType 3
1588)
1589xt "10000,29000,15250,29000"
1590pts [
1591"10000,29000"
1592"15250,29000"
1593]
1594)
1595end &30
1596sat 16
1597eat 32
1598st 0
1599sf 1
1600si 0
1601tg (WTG
1602uid 115,0
1603ps "ConnStartEndStrategy"
1604stg "STSignalDisplayStrategy"
1605f (Text
1606uid 116,0
1607va (VaSet
1608)
1609xt "11000,28000,13900,29000"
1610st "synch_i"
1611blo "11000,28800"
1612tm "WireNameMgr"
1613)
1614)
1615on &3
1616)
1617*47 (Wire
1618uid 117,0
1619shape (OrthoPolyLine
1620uid 118,0
1621va (VaSet
1622vasetType 3
1623lineWidth 2
1624)
1625xt "34750,28000,48000,28000"
1626pts [
1627"34750,28000"
1628"48000,28000"
1629]
1630)
1631start &32
1632sat 32
1633eat 16
1634sty 1
1635st 0
1636sf 1
1637si 0
1638tg (WTG
1639uid 123,0
1640ps "ConnStartEndStrategy"
1641stg "STSignalDisplayStrategy"
1642f (Text
1643uid 124,0
1644va (VaSet
1645)
1646xt "36000,27000,47400,28000"
1647st "time_o : (TIMER_WIDTH-1:0)"
1648blo "36000,27800"
1649tm "WireNameMgr"
1650)
1651)
1652on &1
1653)
1654*48 (Wire
1655uid 125,0
1656shape (OrthoPolyLine
1657uid 126,0
1658va (VaSet
1659vasetType 3
1660)
1661xt "34750,29000,48000,29000"
1662pts [
1663"34750,29000"
1664"48000,29000"
1665]
1666)
1667start &31
1668sat 32
1669eat 16
1670st 0
1671sf 1
1672si 0
1673tg (WTG
1674uid 131,0
1675ps "ConnStartEndStrategy"
1676stg "STSignalDisplayStrategy"
1677f (Text
1678uid 132,0
1679va (VaSet
1680)
1681xt "36000,28000,39900,29000"
1682st "synched_o"
1683blo "36000,28800"
1684tm "WireNameMgr"
1685)
1686)
1687on &2
1688)
1689*49 (Wire
1690uid 546,0
1691shape (OrthoPolyLine
1692uid 547,0
1693va (VaSet
1694vasetType 3
1695)
1696xt "5000,14000,8250,14000"
1697pts [
1698"5000,14000"
1699"8250,14000"
1700]
1701)
1702end &17
1703sat 16
1704eat 32
1705st 0
1706sf 1
1707si 0
1708tg (WTG
1709uid 550,0
1710ps "ConnStartEndStrategy"
1711stg "STSignalDisplayStrategy"
1712f (Text
1713uid 551,0
1714va (VaSet
1715)
1716xt "6000,13000,7300,14000"
1717st "clk"
1718blo "6000,13800"
1719tm "WireNameMgr"
1720)
1721)
1722on &26
1723)
1724*50 (Wire
1725uid 552,0
1726shape (OrthoPolyLine
1727uid 553,0
1728va (VaSet
1729vasetType 3
1730)
1731xt "3000,15000,8250,15000"
1732pts [
1733"3000,15000"
1734"8250,15000"
1735]
1736)
1737end &19
1738sat 16
1739eat 32
1740st 0
1741sf 1
1742si 0
1743tg (WTG
1744uid 556,0
1745ps "ConnStartEndStrategy"
1746stg "STSignalDisplayStrategy"
1747f (Text
1748uid 557,0
1749va (VaSet
1750)
1751xt "4000,14000,6900,15000"
1752st "synch_i"
1753blo "4000,14800"
1754tm "WireNameMgr"
1755)
1756)
1757on &3
1758)
1759*51 (Wire
1760uid 560,0
1761shape (OrthoPolyLine
1762uid 561,0
1763va (VaSet
1764vasetType 3
1765)
1766xt "1000,16000,8250,16000"
1767pts [
1768"1000,16000"
1769"8250,16000"
1770]
1771)
1772end &21
1773sat 16
1774eat 32
1775st 0
1776sf 1
1777si 0
1778tg (WTG
1779uid 564,0
1780ps "ConnStartEndStrategy"
1781stg "STSignalDisplayStrategy"
1782f (Text
1783uid 565,0
1784va (VaSet
1785)
1786xt "2000,15000,7400,16000"
1787st "reset_synch_i"
1788blo "2000,15800"
1789tm "WireNameMgr"
1790)
1791)
1792on &27
1793)
1794*52 (Wire
1795uid 566,0
1796shape (OrthoPolyLine
1797uid 567,0
1798va (VaSet
1799vasetType 3
1800)
1801xt "3000,17000,8250,17000"
1802pts [
1803"3000,17000"
1804"8250,17000"
1805]
1806)
1807end &22
1808sat 16
1809eat 32
1810st 0
1811sf 1
1812si 0
1813tg (WTG
1814uid 570,0
1815ps "ConnStartEndStrategy"
1816stg "STSignalDisplayStrategy"
1817f (Text
1818uid 571,0
1819va (VaSet
1820)
1821xt "4000,16000,7200,17000"
1822st "enable_i"
1823blo "4000,16800"
1824tm "WireNameMgr"
1825)
1826)
1827on &4
1828)
1829*53 (Wire
1830uid 572,0
1831shape (OrthoPolyLine
1832uid 573,0
1833va (VaSet
1834vasetType 3
1835lineWidth 2
1836)
1837xt "29750,14000,43000,14000"
1838pts [
1839"29750,14000"
1840"43000,14000"
1841]
1842)
1843start &18
1844sat 32
1845eat 16
1846sty 1
1847st 0
1848sf 1
1849si 0
1850tg (WTG
1851uid 576,0
1852ps "ConnStartEndStrategy"
1853stg "STSignalDisplayStrategy"
1854f (Text
1855uid 577,0
1856va (VaSet
1857)
1858xt "31000,13000,42400,14000"
1859st "time_o : (TIMER_WIDTH-1:0)"
1860blo "31000,13800"
1861tm "WireNameMgr"
1862)
1863)
1864on &1
1865)
1866*54 (Wire
1867uid 578,0
1868shape (OrthoPolyLine
1869uid 579,0
1870va (VaSet
1871vasetType 3
1872)
1873xt "29750,15000,36000,15000"
1874pts [
1875"29750,15000"
1876"36000,15000"
1877]
1878)
1879start &20
1880sat 32
1881eat 16
1882st 0
1883sf 1
1884si 0
1885tg (WTG
1886uid 582,0
1887ps "ConnStartEndStrategy"
1888stg "STSignalDisplayStrategy"
1889f (Text
1890uid 583,0
1891va (VaSet
1892)
1893xt "31000,14000,34900,15000"
1894st "synched_o"
1895blo "31000,14800"
1896tm "WireNameMgr"
1897)
1898)
1899on &2
1900)
1901*55 (Wire
1902uid 622,0
1903shape (OrthoPolyLine
1904uid 623,0
1905va (VaSet
1906vasetType 3
1907)
1908xt "34750,30000,38000,30000"
1909pts [
1910"34750,30000"
1911"38000,30000"
1912]
1913)
1914start &33
1915sat 32
1916eat 16
1917stc 0
1918st 0
1919si 0
1920tg (WTG
1921uid 626,0
1922ps "ConnStartEndStrategy"
1923stg "STSignalDisplayStrategy"
1924f (Text
1925uid 627,0
1926va (VaSet
1927)
1928xt "36000,29000,37300,30000"
1929st "clk"
1930blo "36000,29800"
1931tm "WireNameMgr"
1932)
1933)
1934on &26
1935)
1936*56 (Wire
1937uid 628,0
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2889xt "14100,20000,22000,21000"
2890st "Frame Declarations"
2891blo "14100,20800"
2892)
2893*85 (MLText
2894va (VaSet
2895)
2896xt "14100,21000,14100,21000"
2897tm "BdFrameDeclTextMgr"
2898)
2899]
2900)
2901)
2902defaultBlockFrame (Frame
2903shape (RectFrame
2904va (VaSet
2905vasetType 1
2906fg "65535,65535,65535"
2907lineColor "26368,26368,26368"
2908lineStyle 1
2909lineWidth 3
2910)
2911xt "0,0,20000,20000"
2912)
2913title (TextAssociate
2914ps "TopLeftStrategy"
2915text (MLText
2916va (VaSet
2917)
2918xt "0,-1100,7400,-100"
2919st "b0: BLOCK (guard)"
2920tm "FrameTitleTextMgr"
2921)
2922)
2923seqNum (FrameSequenceNumber
2924ps "TopLeftStrategy"
2925shape (Rectangle
2926va (VaSet
2927vasetType 1
2928fg "65535,65535,65535"
2929)
2930xt "50,50,1250,1450"
2931)
2932num (Text
2933va (VaSet
2934)
2935xt "250,250,1050,1250"
2936st "1"
2937blo "250,1050"
2938tm "FrameSeqNumMgr"
2939)
2940)
2941decls (MlTextGroup
2942ps "BottomRightOffsetStrategy"
2943stg "VerticalLayoutStrategy"
2944textVec [
2945*86 (Text
2946va (VaSet
2947font "Arial,8,1"
2948)
2949xt "14100,20000,22000,21000"
2950st "Frame Declarations"
2951blo "14100,20800"
2952)
2953*87 (MLText
2954va (VaSet
2955)
2956xt "14100,21000,14100,21000"
2957tm "BdFrameDeclTextMgr"
2958)
2959]
2960)
2961style 3
2962)
2963defaultSaCptPort (CptPort
2964ps "OnEdgeStrategy"
2965shape (Triangle
2966ro 90
2967va (VaSet
2968vasetType 1
2969fg "0,65535,0"
2970)
2971xt "0,0,750,750"
2972)
2973tg (CPTG
2974ps "CptPortTextPlaceStrategy"
2975stg "VerticalLayoutStrategy"
2976f (Text
2977va (VaSet
2978)
2979xt "0,750,1800,1750"
2980st "Port"
2981blo "0,1550"
2982)
2983)
2984thePort (LogicalPort
2985decl (Decl
2986n "Port"
2987t ""
2988o 0
2989)
2990)
2991)
2992defaultSaCptPortBuffer (CptPort
2993ps "OnEdgeStrategy"
2994shape (Diamond
2995va (VaSet
2996vasetType 1
2997fg "65535,65535,65535"
2998)
2999xt "0,0,750,750"
3000)
3001tg (CPTG
3002ps "CptPortTextPlaceStrategy"
3003stg "VerticalLayoutStrategy"
3004f (Text
3005va (VaSet
3006)
3007xt "0,750,1800,1750"
3008st "Port"
3009blo "0,1550"
3010)
3011)
3012thePort (LogicalPort
3013m 3
3014decl (Decl
3015n "Port"
3016t ""
3017o 0
3018)
3019)
3020)
3021defaultDeclText (MLText
3022va (VaSet
3023font "Courier New,8,0"
3024)
3025)
3026archDeclarativeBlock (BdArchDeclBlock
3027uid 1,0
3028stg "BdArchDeclBlockLS"
3029declLabel (Text
3030uid 2,0
3031va (VaSet
3032font "Arial,8,1"
3033)
3034xt "20000,0,25400,1000"
3035st "Declarations"
3036blo "20000,800"
3037)
3038portLabel (Text
3039uid 3,0
3040va (VaSet
3041font "Arial,8,1"
3042)
3043xt "20000,1000,22700,2000"
3044st "Ports:"
3045blo "20000,1800"
3046)
3047preUserLabel (Text
3048uid 4,0
3049va (VaSet
3050isHidden 1
3051font "Arial,8,1"
3052)
3053xt "20000,0,23800,1000"
3054st "Pre User:"
3055blo "20000,800"
3056)
3057preUserText (MLText
3058uid 5,0
3059va (VaSet
3060isHidden 1
3061font "Courier New,8,0"
3062)
3063xt "20000,0,20000,0"
3064tm "BdDeclarativeTextMgr"
3065)
3066diagSignalLabel (Text
3067uid 6,0
3068va (VaSet
3069font "Arial,8,1"
3070)
3071xt "20000,2000,27100,3000"
3072st "Diagram Signals:"
3073blo "20000,2800"
3074)
3075postUserLabel (Text
3076uid 7,0
3077va (VaSet
3078isHidden 1
3079font "Arial,8,1"
3080)
3081xt "20000,0,24700,1000"
3082st "Post User:"
3083blo "20000,800"
3084)
3085postUserText (MLText
3086uid 8,0
3087va (VaSet
3088isHidden 1
3089font "Courier New,8,0"
3090)
3091xt "20000,0,20000,0"
3092tm "BdDeclarativeTextMgr"
3093)
3094)
3095commonDM (CommonDM
3096ldm (LogicalDM
3097suid 9,0
3098usingSuid 1
3099emptyRow *88 (LEmptyRow
3100)
3101uid 188,0
3102optionalChildren [
3103*89 (RefLabelRowHdr
3104)
3105*90 (TitleRowHdr
3106)
3107*91 (FilterRowHdr
3108)
3109*92 (RefLabelColHdr
3110tm "RefLabelColHdrMgr"
3111)
3112*93 (RowExpandColHdr
3113tm "RowExpandColHdrMgr"
3114)
3115*94 (GroupColHdr
3116tm "GroupColHdrMgr"
3117)
3118*95 (NameColHdr
3119tm "BlockDiagramNameColHdrMgr"
3120)
3121*96 (ModeColHdr
3122tm "BlockDiagramModeColHdrMgr"
3123)
3124*97 (TypeColHdr
3125tm "BlockDiagramTypeColHdrMgr"
3126)
3127*98 (BoundsColHdr
3128tm "BlockDiagramBoundsColHdrMgr"
3129)
3130*99 (InitColHdr
3131tm "BlockDiagramInitColHdrMgr"
3132)
3133*100 (EolColHdr
3134tm "BlockDiagramEolColHdrMgr"
3135)
3136*101 (LeafLogPort
3137port (LogicalPort
3138m 4
3139decl (Decl
3140n "time_o"
3141t "std_logic_vector"
3142b "( TIMER_WIDTH-1 downto 0)"
3143o 1
3144suid 1,0
3145)
3146)
3147uid 165,0
3148)
3149*102 (LeafLogPort
3150port (LogicalPort
3151m 4
3152decl (Decl
3153n "synched_o"
3154t "std_logic"
3155o 2
3156suid 2,0
3157i "'0'"
3158)
3159)
3160uid 167,0
3161)
3162*103 (LeafLogPort
3163port (LogicalPort
3164m 4
3165decl (Decl
3166n "synch_i"
3167t "std_logic"
3168o 4
3169suid 4,0
3170)
3171)
3172uid 171,0
3173)
3174*104 (LeafLogPort
3175port (LogicalPort
3176m 4
3177decl (Decl
3178n "enable_i"
3179t "std_logic"
3180o 5
3181suid 5,0
3182)
3183)
3184uid 173,0
3185)
3186*105 (LeafLogPort
3187port (LogicalPort
3188m 4
3189decl (Decl
3190n "clk"
3191t "std_logic"
3192o 5
3193suid 8,0
3194)
3195)
3196uid 584,0
3197)
3198*106 (LeafLogPort
3199port (LogicalPort
3200m 4
3201decl (Decl
3202n "reset_synch_i"
3203t "std_logic"
3204o 6
3205suid 9,0
3206)
3207)
3208uid 586,0
3209)
3210]
3211)
3212pdm (PhysicalDM
3213displayShortBounds 1
3214editShortBounds 1
3215uid 201,0
3216optionalChildren [
3217*107 (Sheet
3218sheetRow (SheetRow
3219headerVa (MVa
3220cellColor "49152,49152,49152"
3221fontColor "0,0,0"
3222font "Tahoma,10,0"
3223)
3224cellVa (MVa
3225cellColor "65535,65535,65535"
3226fontColor "0,0,0"
3227font "Tahoma,10,0"
3228)
3229groupVa (MVa
3230cellColor "39936,56832,65280"
3231fontColor "0,0,0"
3232font "Tahoma,10,0"
3233)
3234emptyMRCItem *108 (MRCItem
3235litem &88
3236pos 6
3237dimension 20
3238)
3239uid 203,0
3240optionalChildren [
3241*109 (MRCItem
3242litem &89
3243pos 0
3244dimension 20
3245uid 204,0
3246)
3247*110 (MRCItem
3248litem &90
3249pos 1
3250dimension 23
3251uid 205,0
3252)
3253*111 (MRCItem
3254litem &91
3255pos 2
3256hidden 1
3257dimension 20
3258uid 206,0
3259)
3260*112 (MRCItem
3261litem &101
3262pos 0
3263dimension 20
3264uid 166,0
3265)
3266*113 (MRCItem
3267litem &102
3268pos 1
3269dimension 20
3270uid 168,0
3271)
3272*114 (MRCItem
3273litem &103
3274pos 2
3275dimension 20
3276uid 172,0
3277)
3278*115 (MRCItem
3279litem &104
3280pos 3
3281dimension 20
3282uid 174,0
3283)
3284*116 (MRCItem
3285litem &105
3286pos 4
3287dimension 20
3288uid 585,0
3289)
3290*117 (MRCItem
3291litem &106
3292pos 5
3293dimension 20
3294uid 587,0
3295)
3296]
3297)
3298sheetCol (SheetCol
3299propVa (MVa
3300cellColor "0,49152,49152"
3301fontColor "0,0,0"
3302font "Tahoma,10,0"
3303textAngle 90
3304)
3305uid 207,0
3306optionalChildren [
3307*118 (MRCItem
3308litem &92
3309pos 0
3310dimension 20
3311uid 208,0
3312)
3313*119 (MRCItem
3314litem &94
3315pos 1
3316dimension 50
3317uid 209,0
3318)
3319*120 (MRCItem
3320litem &95
3321pos 2
3322dimension 100
3323uid 210,0
3324)
3325*121 (MRCItem
3326litem &96
3327pos 3
3328dimension 50
3329uid 211,0
3330)
3331*122 (MRCItem
3332litem &97
3333pos 4
3334dimension 100
3335uid 212,0
3336)
3337*123 (MRCItem
3338litem &98
3339pos 5
3340dimension 100
3341uid 213,0
3342)
3343*124 (MRCItem
3344litem &99
3345pos 6
3346dimension 50
3347uid 214,0
3348)
3349*125 (MRCItem
3350litem &100
3351pos 7
3352dimension 80
3353uid 215,0
3354)
3355]
3356)
3357fixedCol 4
3358fixedRow 2
3359name "Ports"
3360uid 202,0
3361vaOverrides [
3362]
3363)
3364]
3365)
3366uid 187,0
3367)
3368genericsCommonDM (CommonDM
3369ldm (LogicalDM
3370emptyRow *126 (LEmptyRow
3371)
3372uid 217,0
3373optionalChildren [
3374*127 (RefLabelRowHdr
3375)
3376*128 (TitleRowHdr
3377)
3378*129 (FilterRowHdr
3379)
3380*130 (RefLabelColHdr
3381tm "RefLabelColHdrMgr"
3382)
3383*131 (RowExpandColHdr
3384tm "RowExpandColHdrMgr"
3385)
3386*132 (GroupColHdr
3387tm "GroupColHdrMgr"
3388)
3389*133 (NameColHdr
3390tm "GenericNameColHdrMgr"
3391)
3392*134 (TypeColHdr
3393tm "GenericTypeColHdrMgr"
3394)
3395*135 (InitColHdr
3396tm "GenericValueColHdrMgr"
3397)
3398*136 (PragmaColHdr
3399tm "GenericPragmaColHdrMgr"
3400)
3401*137 (EolColHdr
3402tm "GenericEolColHdrMgr"
3403)
3404*138 (LogGeneric
3405generic (GiElement
3406name "TIMER_WIDTH"
3407type "integer"
3408value "32"
3409)
3410uid 9,0
3411)
3412*139 (LogGeneric
3413generic (GiElement
3414name "PRESCALER"
3415type "integer"
3416value "2500"
3417)
3418uid 11,0
3419)
3420]
3421)
3422pdm (PhysicalDM
3423displayShortBounds 1
3424editShortBounds 1
3425uid 229,0
3426optionalChildren [
3427*140 (Sheet
3428sheetRow (SheetRow
3429headerVa (MVa
3430cellColor "49152,49152,49152"
3431fontColor "0,0,0"
3432font "Tahoma,10,0"
3433)
3434cellVa (MVa
3435cellColor "65535,65535,65535"
3436fontColor "0,0,0"
3437font "Tahoma,10,0"
3438)
3439groupVa (MVa
3440cellColor "39936,56832,65280"
3441fontColor "0,0,0"
3442font "Tahoma,10,0"
3443)
3444emptyMRCItem *141 (MRCItem
3445litem &126
3446pos 2
3447dimension 20
3448)
3449uid 231,0
3450optionalChildren [
3451*142 (MRCItem
3452litem &127
3453pos 0
3454dimension 20
3455uid 232,0
3456)
3457*143 (MRCItem
3458litem &128
3459pos 1
3460dimension 23
3461uid 233,0
3462)
3463*144 (MRCItem
3464litem &129
3465pos 2
3466hidden 1
3467dimension 20
3468uid 234,0
3469)
3470*145 (MRCItem
3471litem &138
3472pos 0
3473dimension 20
3474uid 10,0
3475)
3476*146 (MRCItem
3477litem &139
3478pos 1
3479dimension 20
3480uid 12,0
3481)
3482]
3483)
3484sheetCol (SheetCol
3485propVa (MVa
3486cellColor "0,49152,49152"
3487fontColor "0,0,0"
3488font "Tahoma,10,0"
3489textAngle 90
3490)
3491uid 235,0
3492optionalChildren [
3493*147 (MRCItem
3494litem &130
3495pos 0
3496dimension 20
3497uid 236,0
3498)
3499*148 (MRCItem
3500litem &132
3501pos 1
3502dimension 50
3503uid 237,0
3504)
3505*149 (MRCItem
3506litem &133
3507pos 2
3508dimension 100
3509uid 238,0
3510)
3511*150 (MRCItem
3512litem &134
3513pos 3
3514dimension 100
3515uid 239,0
3516)
3517*151 (MRCItem
3518litem &135
3519pos 4
3520dimension 50
3521uid 240,0
3522)
3523*152 (MRCItem
3524litem &136
3525pos 5
3526dimension 50
3527uid 241,0
3528)
3529*153 (MRCItem
3530litem &137
3531pos 6
3532dimension 80
3533uid 242,0
3534)
3535]
3536)
3537fixedCol 3
3538fixedRow 2
3539name "Ports"
3540uid 230,0
3541vaOverrides [
3542]
3543)
3544]
3545)
3546uid 216,0
3547type 1
3548)
3549activeModelName "BlockDiag"
3550)
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