source: firmware/FAD/FACT_FAD_TB_lib/hds/timer_tb/struct.bd@ 18260

DocumentHdrVersion "1.1"
Header (DocumentHdr
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unitName "std_logic_1164"
itemName "ALL"
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duName "timer"
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value "5000"
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mwi 0
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duName "timer_tester"
elements [
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libraryRefs [
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version "29.1"
appVersion "2009.2 (Build 10)"
noEmbeddedEditors 1
model (BlockDiag
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value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hdl"
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value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
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variable "appl"
value "HDL Designer"
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(vvPair
variable "arch_name"
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variable "config"
value "%(unit)_%(view)_config"
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variable "d"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\timer_tb"
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(vvPair
variable "d_logical"
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(vvPair
variable "date"
value "23.02.2011"
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(vvPair
variable "day"
value "Mi"
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(vvPair
variable "day_long"
value "Mittwoch"
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(vvPair
variable "dd"
value "23"
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(vvPair
variable "entity_name"
value "timer_tb"
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(vvPair
variable "ext"
value "<TBD>"
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(vvPair
variable "f"
value "struct.bd"
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(vvPair
variable "f_logical"
value "struct.bd"
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(vvPair
variable "f_noext"
value "struct"
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(vvPair
variable "group"
value "UNKNOWN"
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(vvPair
variable "host"
value "E5B-LABOR6"
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(vvPair
variable "language"
value "VHDL"
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(vvPair
variable "library"
value "FACT_FAD_TB_lib"
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(vvPair
variable "library_downstream_HdsLintPlugin"
value "$HDS_PROJECT_DIR\\FACT_FAD_TB_lib\\designcheck"
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(vvPair
variable "library_downstream_ISEPARInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
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(vvPair
variable "library_downstream_ImpactInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
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(vvPair
variable "library_downstream_ModelSimCompiler"
value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/work"
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(vvPair
variable "library_downstream_XSTDataPrep"
value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
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(vvPair
variable "mm"
value "02"
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variable "module_name"
value "timer_tb"
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variable "month"
value "Feb"
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(vvPair
variable "month_long"
value "Februar"
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variable "p"
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variable "package_name"
value "<Undefined Variable>"
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variable "project_name"
value "FACT_FAD"
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variable "series"
value "HDL Designer Series"
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variable "task_DesignCompilerPath"
value "<TBD>"
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variable "task_LeonardoPath"
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value "C:\\modeltech_6.6a\\win32"
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(vvPair
variable "task_NC-SimPath"
value "<TBD>"
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(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
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(vvPair
variable "task_QuestaSimPath"
value "<TBD>"
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(vvPair
variable "task_VCSPath"
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variable "this_ext"
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(vvPair
variable "this_file"
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(vvPair
variable "this_file_logical"
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(vvPair
variable "time"
value "12:23:43"
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(vvPair
variable "unit"
value "timer_tb"
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(vvPair
variable "user"
value "dneise"
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(vvPair
variable "version"
value "2009.2 (Build 10)"
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(vvPair
variable "view"
value "struct"
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(vvPair
variable "year"
value "2011"
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(vvPair
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value "11"
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)
)
thePort (LogicalPort
lang 10
decl (Decl
n "time_o"
t "std_logic_vector"
b "( 31 DOWNTO 0)"
o 2
suid 19,0
)
)
)
*33 (CptPort
uid 614,0
ps "OnEdgeStrategy"
shape (Triangle
uid 615,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "34000,29625,34750,30375"
)
tg (CPTG
uid 616,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 617,0
va (VaSet
)
xt "31700,29500,33000,30500"
st "clk"
ju 2
blo "33000,30300"
)
)
thePort (LogicalPort
lang 10
m 1
decl (Decl
n "clk"
t "std_logic"
o 5
)
)
)
*34 (CptPort
uid 618,0
ps "OnEdgeStrategy"
shape (Triangle
uid 619,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "34000,30625,34750,31375"
)
tg (CPTG
uid 620,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 621,0
va (VaSet
)
xt "27600,30500,33000,31500"
st "reset_synch_i"
ju 2
blo "33000,31300"
)
)
thePort (LogicalPort
lang 10
m 1
decl (Decl
n "reset_synch_i"
t "std_logic"
o 4
)
)
)
]
shape (Rectangle
uid 605,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "16000,27000,34000,32000"
)
oxt "15000,6000,33000,10000"
ttg (MlTextGroup
uid 606,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*35 (Text
uid 607,0
va (VaSet
font "Arial,8,1"
)
xt "21150,28000,28850,29000"
st "FACT_FAD_TB_lib"
blo "21150,28800"
tm "BdLibraryNameMgr"
)
*36 (Text
uid 608,0
va (VaSet
font "Arial,8,1"
)
xt "21150,29000,26350,30000"
st "timer_tester"
blo "21150,29800"
tm "CptNameMgr"
)
*37 (Text
uid 609,0
va (VaSet
font "Arial,8,1"
)
xt "21150,30000,22950,31000"
st "U_1"
blo "21150,30800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 610,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 611,0
text (MLText
uid 612,0
va (VaSet
font "Courier New,8,0"
)
xt "1000,25800,1000,25800"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 613,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "16250,30250,17750,31750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
sTC 0
sF 0
)
archFileType "UNKNOWN"
)
*38 (Wire
uid 93,0
shape (OrthoPolyLine
uid 94,0
va (VaSet
vasetType 3
)
xt "10000,30000,15250,30000"
pts [
"10000,30000"
"15250,30000"
]
)
end &29
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 99,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 100,0
va (VaSet
)
xt "11000,29000,14200,30000"
st "enable_i"
blo "11000,29800"
tm "WireNameMgr"
)
)
on &4
)
*39 (Wire
uid 109,0
shape (OrthoPolyLine
uid 110,0
va (VaSet
vasetType 3
)
xt "10000,29000,15250,29000"
pts [
"10000,29000"
"15250,29000"
]
)
end &30
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 115,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 116,0
va (VaSet
)
xt "11000,28000,13900,29000"
st "synch_i"
blo "11000,28800"
tm "WireNameMgr"
)
)
on &3
)
*40 (Wire
uid 117,0
shape (OrthoPolyLine
uid 118,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "34750,28000,48000,28000"
pts [
"34750,28000"
"48000,28000"
]
)
start &32
sat 32
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 123,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 124,0
va (VaSet
)
xt "36000,27000,47400,28000"
st "time_o : (TIMER_WIDTH-1:0)"
blo "36000,27800"
tm "WireNameMgr"
)
)
on &1
)
*41 (Wire
uid 125,0
shape (OrthoPolyLine
uid 126,0
va (VaSet
vasetType 3
)
xt "34750,29000,48000,29000"
pts [
"34750,29000"
"48000,29000"
]
)
start &31
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 131,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 132,0
va (VaSet
)
xt "36000,28000,39900,29000"
st "synched_o"
blo "36000,28800"
tm "WireNameMgr"
)
)
on &2
)
*42 (Wire
uid 546,0
shape (OrthoPolyLine
uid 547,0
va (VaSet
vasetType 3
)
xt "5000,14000,8250,14000"
pts [
"5000,14000"
"8250,14000"
]
)
end &17
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 550,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 551,0
va (VaSet
)
xt "6000,13000,7300,14000"
st "clk"
blo "6000,13800"
tm "WireNameMgr"
)
)
on &26
)
*43 (Wire
uid 552,0
shape (OrthoPolyLine
uid 553,0
va (VaSet
vasetType 3
)
xt "3000,15000,8250,15000"
pts [
"3000,15000"
"8250,15000"
]
)
end &19
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 556,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 557,0
va (VaSet
)
xt "4000,14000,6900,15000"
st "synch_i"
blo "4000,14800"
tm "WireNameMgr"
)
)
on &3
)
*44 (Wire
uid 560,0
shape (OrthoPolyLine
uid 561,0
va (VaSet
vasetType 3
)
xt "1000,16000,8250,16000"
pts [
"1000,16000"
"8250,16000"
]
)
end &21
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 564,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 565,0
va (VaSet
)
xt "2000,15000,7400,16000"
st "reset_synch_i"
blo "2000,15800"
tm "WireNameMgr"
)
)
on &27
)
*45 (Wire
uid 566,0
shape (OrthoPolyLine
uid 567,0
va (VaSet
vasetType 3
)
xt "3000,17000,8250,17000"
pts [
"3000,17000"
"8250,17000"
]
)
end &22
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 570,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 571,0
va (VaSet
)
xt "4000,16000,7200,17000"
st "enable_i"
blo "4000,16800"
tm "WireNameMgr"
)
)
on &4
)
*46 (Wire
uid 572,0
shape (OrthoPolyLine
uid 573,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "29750,14000,43000,14000"
pts [
"29750,14000"
"43000,14000"
]
)
start &18
sat 32
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 576,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 577,0
va (VaSet
)
xt "31000,13000,42400,14000"
st "time_o : (TIMER_WIDTH-1:0)"
blo "31000,13800"
tm "WireNameMgr"
)
)
on &1
)
*47 (Wire
uid 578,0
shape (OrthoPolyLine
uid 579,0
va (VaSet
vasetType 3
)
xt "29750,15000,36000,15000"
pts [
"29750,15000"
"36000,15000"
]
)
start &20
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 582,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 583,0
va (VaSet
)
xt "31000,14000,34900,15000"
st "synched_o"
blo "31000,14800"
tm "WireNameMgr"
)
)
on &2
)
*48 (Wire
uid 622,0
shape (OrthoPolyLine
uid 623,0
va (VaSet
vasetType 3
)
xt "34750,30000,38000,30000"
pts [
"34750,30000"
"38000,30000"
]
)
start &33
sat 32
eat 16
stc 0
st 0
si 0
tg (WTG
uid 626,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 627,0
va (VaSet
)
xt "36000,29000,37300,30000"
st "clk"
blo "36000,29800"
tm "WireNameMgr"
)
)
on &26
)
*49 (Wire
uid 628,0
shape (OrthoPolyLine
uid 629,0
va (VaSet
vasetType 3
)
xt "34750,31000,42000,31000"
pts [
"34750,31000"
"42000,31000"
]
)
start &34
sat 32
eat 16
stc 0
st 0
si 0
tg (WTG
uid 632,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 633,0
va (VaSet
)
xt "36000,30000,41400,31000"
st "reset_synch_i"
blo "36000,30800"
tm "WireNameMgr"
)
)
on &27
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 1
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *50 (PackageList
uid 175,0
stg "VerticalLayoutStrategy"
textVec [
*51 (Text
uid 176,0
va (VaSet
font "arial,8,1"
)
xt "0,0,5400,1000"
st "Package List"
blo "0,800"
)
*52 (MLText
uid 177,0
va (VaSet
)
xt "0,1000,12400,5000"
st "LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.all;"
tm "PackageList"
)
]
)
compDirBlock (MlTextGroup
uid 178,0
stg "VerticalLayoutStrategy"
textVec [
*53 (Text
uid 179,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,0,28100,1000"
st "Compiler Directives"
blo "20000,800"
)
*54 (Text
uid 180,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,1000,29600,2000"
st "Pre-module directives:"
blo "20000,1800"
)
*55 (MLText
uid 181,0
va (VaSet
isHidden 1
)
xt "20000,2000,27500,4000"
st "`resetall
`timescale 1ns/10ps"
tm "BdCompilerDirectivesTextMgr"
)
*56 (Text
uid 182,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,4000,30100,5000"
st "Post-module directives:"
blo "20000,4800"
)
*57 (MLText
uid 183,0
va (VaSet
isHidden 1
)
xt "20000,0,20000,0"
tm "BdCompilerDirectivesTextMgr"
)
*58 (Text
uid 184,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,5000,29900,6000"
st "End-module directives:"
blo "20000,5800"
)
*59 (MLText
uid 185,0
va (VaSet
isHidden 1
)
xt "20000,6000,20000,6000"
tm "BdCompilerDirectivesTextMgr"
)
]
associable 1
)
windowSize "0,22,1281,1024"
viewArea "-21800,-200,74751,77423"
cachedDiagramExtent "0,0,66000,49000"
hasePageBreakOrigin 1
pageBreakOrigin "-7000,0"
lastUid 654,0
defaultCommentText (CommentText
shape (Rectangle
layer 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
lineColor "0,0,32768"
)
xt "0,0,15000,5000"
)
text (MLText
va (VaSet
fg "0,0,32768"
)
xt "200,200,2000,1200"
st "
Text
"
tm "CommentText"
wrapOption 3
visibleHeight 4600
visibleWidth 14600
)
)
defaultPanel (Panel
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "32768,0,0"
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (Text
va (VaSet
font "Arial,8,1"
)
xt "1000,1000,3800,2000"
st "Panel0"
blo "1000,1800"
tm "PanelText"
)
)
)
defaultBlk (Blk
shape (Rectangle
va (VaSet
vasetType 1
fg "39936,56832,65280"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*60 (Text
va (VaSet
font "Arial,8,1"
)
xt "2200,3500,5800,4500"
st "<library>"
blo "2200,4300"
tm "BdLibraryNameMgr"
)
*61 (Text
va (VaSet
font "Arial,8,1"
)
xt "2200,4500,5600,5500"
st "<block>"
blo "2200,5300"
tm "BlkNameMgr"
)
*62 (Text
va (VaSet
font "Arial,8,1"
)
xt "2200,5500,4000,6500"
st "U_0"
blo "2200,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "2200,13500,2200,13500"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
)
defaultMWComponent (MWC
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*63 (Text
va (VaSet
font "Arial,8,1"
)
xt "550,3500,3450,4500"
st "Library"
blo "550,4300"
)
*64 (Text
va (VaSet
font "Arial,8,1"
)
xt "550,4500,7450,5500"
st "MWComponent"
blo "550,5300"
)
*65 (Text
va (VaSet
font "Arial,8,1"
)
xt "550,5500,2350,6500"
st "U_0"
blo "550,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-6450,1500,-6450,1500"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
visOptions (mwParamsVisibilityOptions
)
)
defaultSaComponent (SaComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*66 (Text
va (VaSet
font "Arial,8,1"
)
xt "900,3500,3800,4500"
st "Library"
blo "900,4300"
tm "BdLibraryNameMgr"
)
*67 (Text
va (VaSet
font "Arial,8,1"
)
xt "900,4500,7100,5500"
st "SaComponent"
blo "900,5300"
tm "CptNameMgr"
)
*68 (Text
va (VaSet
font "Arial,8,1"
)
xt "900,5500,2700,6500"
st "U_0"
blo "900,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-6100,1500,-6100,1500"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
defaultVhdlComponent (VhdlComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*69 (Text
va (VaSet
font "Arial,8,1"
)
xt "500,3500,3400,4500"
st "Library"
blo "500,4300"
)
*70 (Text
va (VaSet
font "Arial,8,1"
)
xt "500,4500,7500,5500"
st "VhdlComponent"
blo "500,5300"
)
*71 (Text
va (VaSet
font "Arial,8,1"
)
xt "500,5500,2300,6500"
st "U_0"
blo "500,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-6500,1500,-6500,1500"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
)
entityPath ""
archName ""
archPath ""
)
defaultVerilogComponent (VerilogComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-450,0,8450,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*72 (Text
va (VaSet
font "Arial,8,1"
)
xt "50,3500,2950,4500"
st "Library"
blo "50,4300"
)
*73 (Text
va (VaSet
font "Arial,8,1"
)
xt "50,4500,7950,5500"
st "VerilogComponent"
blo "50,5300"
)
*74 (Text
va (VaSet
font "Arial,8,1"
)
xt "50,5500,1850,6500"
st "U_0"
blo "50,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-6950,1500,-6950,1500"
)
header ""
)
elements [
]
)
entityPath ""
)
defaultHdlText (HdlText
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,37120"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*75 (Text
va (VaSet
font "Arial,8,1"
)
xt "3150,4000,4850,5000"
st "eb1"
blo "3150,4800"
tm "HdlTextNameMgr"
)
*76 (Text
va (VaSet
font "Arial,8,1"
)
xt "3150,5000,3950,6000"
st "1"
blo "3150,5800"
tm "HdlTextNumberMgr"
)
]
)
viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
)
defaultEmbeddedText (EmbeddedText
commentText (CommentText
ps "CenterOffsetStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,18000,5000"
)
text (MLText
va (VaSet
)
xt "200,200,2000,1200"
st "
Text
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 4600
visibleWidth 17600
)
)
)
defaultGlobalConnector (GlobalConnector
shape (Circle
va (VaSet
vasetType 1
fg "65535,65535,0"
)
xt "-1000,-1000,1000,1000"
radius 1000
)
name (Text
va (VaSet
font "Arial,8,1"
)
xt "-500,-500,500,500"
st "G"
blo "-500,300"
)
)
defaultRipper (Ripper
ps "OnConnectorStrategy"
shape (Line2D
pts [
"0,0"
"1000,1000"
]
va (VaSet
vasetType 1
)
xt "0,0,1000,1000"
)
)
defaultBdJunction (BdJunction
ps "OnConnectorStrategy"
shape (Circle
va (VaSet
vasetType 1
)
xt "-400,-400,400,400"
radius 400
)
)
defaultPortIoIn (PortIoIn
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "-2000,-375,-500,375"
)
(Line
sl 0
ro 270
xt "-500,0,0,0"
pts [
"-500,0"
"0,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "-1375,-1000,-1375,-1000"
ju 2
blo "-1375,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoOut (PortIoOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "500,-375,2000,375"
)
(Line
sl 0
ro 270
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "625,-1000,625,-1000"
blo "625,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoInOut (PortIoInOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultPortIoBuffer (PortIoBuffer
shape (CompositeShape
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultSignal (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,0,1900,1000"
st "sig0"
blo "0,800"
tm "WireNameMgr"
)
)
)
defaultBus (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineWidth 2
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,0,2400,1000"
st "dbus0"
blo "0,800"
tm "WireNameMgr"
)
)
)
defaultBundle (Bundle
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineColor "32768,0,0"
lineWidth 2
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
textGroup (BiTextGroup
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
first (Text
va (VaSet
)
xt "0,0,3000,1000"
st "bundle0"
blo "0,800"
tm "BundleNameMgr"
)
second (MLText
va (VaSet
)
xt "0,1000,1000,2000"
st "()"
tm "BundleContentsMgr"
)
)
bundleNet &0
)
defaultPortMapFrame (PortMapFrame
ps "PortMapFrameStrategy"
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,10000,12000"
)
portMapText (BiTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
first (MLText
va (VaSet
)
)
second (MLText
va (VaSet
)
tm "PortMapTextMgr"
)
)
)
defaultGenFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "26368,26368,26368"
lineStyle 2
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1100,12600,-100"
st "g0: FOR i IN 0 TO n GENERATE"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1250,1450"
)
num (Text
va (VaSet
)
xt "250,250,1050,1250"
st "1"
blo "250,1050"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*77 (Text
va (VaSet
font "Arial,8,1"
)
xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*78 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
)
]
)
)
defaultBlockFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "26368,26368,26368"
lineStyle 1
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1100,7400,-100"
st "b0: BLOCK (guard)"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1250,1450"
)
num (Text
va (VaSet
)
xt "250,250,1050,1250"
st "1"
blo "250,1050"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*79 (Text
va (VaSet
font "Arial,8,1"
)
xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*80 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
)
]
)
style 3
)
defaultSaCptPort (CptPort
ps "OnEdgeStrategy"
shape (Triangle
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1800,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultSaCptPortBuffer (CptPort
ps "OnEdgeStrategy"
shape (Diamond
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1800,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
m 3
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultDeclText (MLText
va (VaSet
font "Courier New,8,0"
)
)
archDeclarativeBlock (BdArchDeclBlock
uid 1,0
stg "BdArchDeclBlockLS"
declLabel (Text
uid 2,0
va (VaSet
font "Arial,8,1"
)
xt "20000,0,25400,1000"
st "Declarations"
blo "20000,800"
)
portLabel (Text
uid 3,0
va (VaSet
font "Arial,8,1"
)
xt "20000,1000,22700,2000"
st "Ports:"
blo "20000,1800"
)
preUserLabel (Text
uid 4,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,0,23800,1000"
st "Pre User:"
blo "20000,800"
)
preUserText (MLText
uid 5,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "20000,0,20000,0"
tm "BdDeclarativeTextMgr"
)
diagSignalLabel (Text
uid 6,0
va (VaSet
font "Arial,8,1"
)
xt "20000,2000,27100,3000"
st "Diagram Signals:"
blo "20000,2800"
)
postUserLabel (Text
uid 7,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,0,24700,1000"
st "Post User:"
blo "20000,800"
)
postUserText (MLText
uid 8,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "20000,0,20000,0"
tm "BdDeclarativeTextMgr"
)
)
commonDM (CommonDM
ldm (LogicalDM
suid 9,0
usingSuid 1
emptyRow *81 (LEmptyRow
)
uid 188,0
optionalChildren [
*82 (RefLabelRowHdr
)
*83 (TitleRowHdr
)
*84 (FilterRowHdr
)
*85 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*86 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*87 (GroupColHdr
tm "GroupColHdrMgr"
)
*88 (NameColHdr
tm "BlockDiagramNameColHdrMgr"
)
*89 (ModeColHdr
tm "BlockDiagramModeColHdrMgr"
)
*90 (TypeColHdr
tm "BlockDiagramTypeColHdrMgr"
)
*91 (BoundsColHdr
tm "BlockDiagramBoundsColHdrMgr"
)
*92 (InitColHdr
tm "BlockDiagramInitColHdrMgr"
)
*93 (EolColHdr
tm "BlockDiagramEolColHdrMgr"
)
*94 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "time_o"
t "std_logic_vector"
b "( TIMER_WIDTH-1 downto 0)"
o 1
suid 1,0
)
)
uid 165,0
)
*95 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "synched_o"
t "std_logic"
o 2
suid 2,0
i "'0'"
)
)
uid 167,0
)
*96 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "synch_i"
t "std_logic"
o 4
suid 4,0
)
)
uid 171,0
)
*97 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "enable_i"
t "std_logic"
o 5
suid 5,0
)
)
uid 173,0
)
*98 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "clk"
t "std_logic"
o 5
suid 8,0
)
)
uid 584,0
)
*99 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "reset_synch_i"
t "std_logic"
o 6
suid 9,0
)
)
uid 586,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 201,0
optionalChildren [
*100 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *101 (MRCItem
litem &81
pos 6
dimension 20
)
uid 203,0
optionalChildren [
*102 (MRCItem
litem &82
pos 0
dimension 20
uid 204,0
)
*103 (MRCItem
litem &83
pos 1
dimension 23
uid 205,0
)
*104 (MRCItem
litem &84
pos 2
hidden 1
dimension 20
uid 206,0
)
*105 (MRCItem
litem &94
pos 0
dimension 20
uid 166,0
)
*106 (MRCItem
litem &95
pos 1
dimension 20
uid 168,0
)
*107 (MRCItem
litem &96
pos 2
dimension 20
uid 172,0
)
*108 (MRCItem
litem &97
pos 3
dimension 20
uid 174,0
)
*109 (MRCItem
litem &98
pos 4
dimension 20
uid 585,0
)
*110 (MRCItem
litem &99
pos 5
dimension 20
uid 587,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 207,0
optionalChildren [
*111 (MRCItem
litem &85
pos 0
dimension 20
uid 208,0
)
*112 (MRCItem
litem &87
pos 1
dimension 50
uid 209,0
)
*113 (MRCItem
litem &88
pos 2
dimension 100
uid 210,0
)
*114 (MRCItem
litem &89
pos 3
dimension 50
uid 211,0
)
*115 (MRCItem
litem &90
pos 4
dimension 100
uid 212,0
)
*116 (MRCItem
litem &91
pos 5
dimension 100
uid 213,0
)
*117 (MRCItem
litem &92
pos 6
dimension 50
uid 214,0
)
*118 (MRCItem
litem &93
pos 7
dimension 80
uid 215,0
)
]
)
fixedCol 4
fixedRow 2
name "Ports"
uid 202,0
vaOverrides [
]
)
]
)
uid 187,0
)
genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *119 (LEmptyRow
)
uid 217,0
optionalChildren [
*120 (RefLabelRowHdr
)
*121 (TitleRowHdr
)
*122 (FilterRowHdr
)
*123 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*124 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*125 (GroupColHdr
tm "GroupColHdrMgr"
)
*126 (NameColHdr
tm "GenericNameColHdrMgr"
)
*127 (TypeColHdr
tm "GenericTypeColHdrMgr"
)
*128 (InitColHdr
tm "GenericValueColHdrMgr"
)
*129 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
)
*130 (EolColHdr
tm "GenericEolColHdrMgr"
)
*131 (LogGeneric
generic (GiElement
name "TIMER_WIDTH"
type "integer"
value "32"
)
uid 9,0
)
*132 (LogGeneric
generic (GiElement
name "PRESCALER"
type "integer"
value "2500"
)
uid 11,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 229,0
optionalChildren [
*133 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *134 (MRCItem
litem &119
pos 2
dimension 20
)
uid 231,0
optionalChildren [
*135 (MRCItem
litem &120
pos 0
dimension 20
uid 232,0
)
*136 (MRCItem
litem &121
pos 1
dimension 23
uid 233,0
)
*137 (MRCItem
litem &122
pos 2
hidden 1
dimension 20
uid 234,0
)
*138 (MRCItem
litem &131
pos 0
dimension 20
uid 10,0
)
*139 (MRCItem
litem &132
pos 1
dimension 20
uid 12,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 235,0
optionalChildren [
*140 (MRCItem
litem &123
pos 0
dimension 20
uid 236,0
)
*141 (MRCItem
litem &125
pos 1
dimension 50
uid 237,0
)
*142 (MRCItem
litem &126
pos 2
dimension 100
uid 238,0
)
*143 (MRCItem
litem &127
pos 3
dimension 100
uid 239,0
)
*144 (MRCItem
litem &128
pos 4
dimension 50
uid 240,0
)
*145 (MRCItem
litem &129
pos 5
dimension 50
uid 241,0
)
*146 (MRCItem
litem &130
pos 6
dimension 80
uid 242,0
)
]
)
fixedCol 3
fixedRow 2
name "Ports"
uid 230,0
vaOverrides [
]
)
]
)
uid 216,0
type 1
)
activeModelName "BlockDiag"
)