source: firmware/FAD/FACT_FAD_TB_lib/hds/timer_tb/struct.bd@ 20115

Last change on this file since 20115 was 11755, checked in by neise, 13 years ago
reinit of this svn repos .... it was all too messy deleted the old folders and restarted with FACT_FAD_lib only. (well and the testbenches)
File size: 43.1 KB
Line 
1DocumentHdrVersion "1.1"
2Header (DocumentHdr
3version 2
4dmPackageRefs [
5(DmPackageRef
6library "ieee"
7unitName "std_logic_1164"
8itemName "ALL"
9)
10(DmPackageRef
11library "ieee"
12unitName "std_logic_arith"
13itemName "ALL"
14)
15(DmPackageRef
16library "ieee"
17unitName "std_logic_unsigned"
18)
19]
20instances [
21(Instance
22name "U_0"
23duLibraryName "FACT_FAD_lib"
24duName "timer"
25elements [
26(GiElement
27name "TIMER_WIDTH"
28type "integer"
29value "32"
30)
31(GiElement
32name "PRESCALER"
33type "integer"
34value "5000"
35)
36]
37mwi 0
38uid 534,0
39)
40(Instance
41name "U_1"
42duLibraryName "FACT_FAD_TB_lib"
43duName "timer_tester"
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45]
46mwi 0
47uid 604,0
48)
49]
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53)
54version "29.1"
55appVersion "2009.2 (Build 10)"
56noEmbeddedEditors 1
57model (BlockDiag
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62value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hdl"
63)
64(vvPair
65variable "HDSDir"
66value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
67)
68(vvPair
69variable "SideDataDesignDir"
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71)
72(vvPair
73variable "SideDataUserDir"
74value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\timer_tb\\struct.bd.user"
75)
76(vvPair
77variable "SourceDir"
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79)
80(vvPair
81variable "appl"
82value "HDL Designer"
83)
84(vvPair
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86value "struct"
87)
88(vvPair
89variable "config"
90value "%(unit)_%(view)_config"
91)
92(vvPair
93variable "d"
94value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\timer_tb"
95)
96(vvPair
97variable "d_logical"
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100(vvPair
101variable "date"
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103)
104(vvPair
105variable "day"
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108(vvPair
109variable "day_long"
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112(vvPair
113variable "dd"
114value "23"
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196(vvPair
197variable "package_name"
198value "<Undefined Variable>"
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200(vvPair
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204(vvPair
205variable "series"
206value "HDL Designer Series"
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208(vvPair
209variable "task_DesignCompilerPath"
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213variable "task_LeonardoPath"
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216(vvPair
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218value "C:\\modeltech_6.6a\\win32"
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220(vvPair
221variable "task_NC-SimPath"
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252(vvPair
253variable "unit"
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255)
256(vvPair
257variable "user"
258value "dneise"
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979portVis (PortSigDisplay
980)
981archFileType "UNKNOWN"
982)
983*26 (Net
984uid 544,0
985decl (Decl
986n "clk"
987t "std_logic"
988o 5
989suid 8,0
990)
991declText (MLText
992uid 545,0
993va (VaSet
994font "Courier New,8,0"
995)
996xt "22000,3000,39500,3800"
997st "SIGNAL clk : std_logic
998"
999)
1000)
1001*27 (Net
1002uid 558,0
1003decl (Decl
1004n "reset_synch_i"
1005t "std_logic"
1006o 6
1007suid 9,0
1008)
1009declText (MLText
1010uid 559,0
1011va (VaSet
1012font "Courier New,8,0"
1013)
1014xt "22000,4600,39500,5400"
1015st "SIGNAL reset_synch_i : std_logic
1016"
1017)
1018)
1019*28 (SaComponent
1020uid 604,0
1021optionalChildren [
1022*29 (CptPort
1023uid 588,0
1024ps "OnEdgeStrategy"
1025shape (Triangle
1026uid 589,0
1027ro 270
1028va (VaSet
1029vasetType 1
1030fg "0,65535,0"
1031)
1032xt "15250,29625,16000,30375"
1033)
1034tg (CPTG
1035uid 590,0
1036ps "CptPortTextPlaceStrategy"
1037stg "VerticalLayoutStrategy"
1038f (Text
1039uid 591,0
1040va (VaSet
1041)
1042xt "17000,29500,20200,30500"
1043st "enable_i"
1044blo "17000,30300"
1045)
1046)
1047thePort (LogicalPort
1048lang 10
1049m 1
1050decl (Decl
1051n "enable_i"
1052t "std_logic"
1053o 3
1054suid 16,0
1055)
1056)
1057)
1058*30 (CptPort
1059uid 592,0
1060ps "OnEdgeStrategy"
1061shape (Triangle
1062uid 593,0
1063ro 270
1064va (VaSet
1065vasetType 1
1066fg "0,65535,0"
1067)
1068xt "15250,28625,16000,29375"
1069)
1070tg (CPTG
1071uid 594,0
1072ps "CptPortTextPlaceStrategy"
1073stg "VerticalLayoutStrategy"
1074f (Text
1075uid 595,0
1076va (VaSet
1077)
1078xt "17000,28500,19900,29500"
1079st "synch_i"
1080blo "17000,29300"
1081)
1082)
1083thePort (LogicalPort
1084lang 10
1085m 1
1086decl (Decl
1087n "synch_i"
1088t "std_logic"
1089o 6
1090suid 17,0
1091)
1092)
1093)
1094*31 (CptPort
1095uid 596,0
1096ps "OnEdgeStrategy"
1097shape (Triangle
1098uid 597,0
1099ro 270
1100va (VaSet
1101vasetType 1
1102fg "0,65535,0"
1103)
1104xt "34000,28625,34750,29375"
1105)
1106tg (CPTG
1107uid 598,0
1108ps "CptPortTextPlaceStrategy"
1109stg "RightVerticalLayoutStrategy"
1110f (Text
1111uid 599,0
1112va (VaSet
1113)
1114xt "29100,28500,33000,29500"
1115st "synched_o"
1116ju 2
1117blo "33000,29300"
1118)
1119)
1120thePort (LogicalPort
1121lang 10
1122decl (Decl
1123n "synched_o"
1124t "std_logic"
1125o 1
1126suid 18,0
1127)
1128)
1129)
1130*32 (CptPort
1131uid 600,0
1132ps "OnEdgeStrategy"
1133shape (Triangle
1134uid 601,0
1135ro 270
1136va (VaSet
1137vasetType 1
1138fg "0,65535,0"
1139)
1140xt "34000,27625,34750,28375"
1141)
1142tg (CPTG
1143uid 602,0
1144ps "CptPortTextPlaceStrategy"
1145stg "RightVerticalLayoutStrategy"
1146f (Text
1147uid 603,0
1148va (VaSet
1149)
1150xt "30400,27500,33000,28500"
1151st "time_o"
1152ju 2
1153blo "33000,28300"
1154)
1155)
1156thePort (LogicalPort
1157lang 10
1158decl (Decl
1159n "time_o"
1160t "std_logic_vector"
1161b "( 31 DOWNTO 0)"
1162o 2
1163suid 19,0
1164)
1165)
1166)
1167*33 (CptPort
1168uid 614,0
1169ps "OnEdgeStrategy"
1170shape (Triangle
1171uid 615,0
1172ro 90
1173va (VaSet
1174vasetType 1
1175fg "0,65535,0"
1176)
1177xt "34000,29625,34750,30375"
1178)
1179tg (CPTG
1180uid 616,0
1181ps "CptPortTextPlaceStrategy"
1182stg "RightVerticalLayoutStrategy"
1183f (Text
1184uid 617,0
1185va (VaSet
1186)
1187xt "31700,29500,33000,30500"
1188st "clk"
1189ju 2
1190blo "33000,30300"
1191)
1192)
1193thePort (LogicalPort
1194lang 10
1195m 1
1196decl (Decl
1197n "clk"
1198t "std_logic"
1199o 5
1200)
1201)
1202)
1203*34 (CptPort
1204uid 618,0
1205ps "OnEdgeStrategy"
1206shape (Triangle
1207uid 619,0
1208ro 90
1209va (VaSet
1210vasetType 1
1211fg "0,65535,0"
1212)
1213xt "34000,30625,34750,31375"
1214)
1215tg (CPTG
1216uid 620,0
1217ps "CptPortTextPlaceStrategy"
1218stg "RightVerticalLayoutStrategy"
1219f (Text
1220uid 621,0
1221va (VaSet
1222)
1223xt "27600,30500,33000,31500"
1224st "reset_synch_i"
1225ju 2
1226blo "33000,31300"
1227)
1228)
1229thePort (LogicalPort
1230lang 10
1231m 1
1232decl (Decl
1233n "reset_synch_i"
1234t "std_logic"
1235o 4
1236)
1237)
1238)
1239]
1240shape (Rectangle
1241uid 605,0
1242va (VaSet
1243vasetType 1
1244fg "0,65535,0"
1245lineColor "0,32896,0"
1246lineWidth 2
1247)
1248xt "16000,27000,34000,32000"
1249)
1250oxt "15000,6000,33000,10000"
1251ttg (MlTextGroup
1252uid 606,0
1253ps "CenterOffsetStrategy"
1254stg "VerticalLayoutStrategy"
1255textVec [
1256*35 (Text
1257uid 607,0
1258va (VaSet
1259font "Arial,8,1"
1260)
1261xt "21150,28000,28850,29000"
1262st "FACT_FAD_TB_lib"
1263blo "21150,28800"
1264tm "BdLibraryNameMgr"
1265)
1266*36 (Text
1267uid 608,0
1268va (VaSet
1269font "Arial,8,1"
1270)
1271xt "21150,29000,26350,30000"
1272st "timer_tester"
1273blo "21150,29800"
1274tm "CptNameMgr"
1275)
1276*37 (Text
1277uid 609,0
1278va (VaSet
1279font "Arial,8,1"
1280)
1281xt "21150,30000,22950,31000"
1282st "U_1"
1283blo "21150,30800"
1284tm "InstanceNameMgr"
1285)
1286]
1287)
1288ga (GenericAssociation
1289uid 610,0
1290ps "EdgeToEdgeStrategy"
1291matrix (Matrix
1292uid 611,0
1293text (MLText
1294uid 612,0
1295va (VaSet
1296font "Courier New,8,0"
1297)
1298xt "1000,25800,1000,25800"
1299)
1300header ""
1301)
1302elements [
1303]
1304)
1305viewicon (ZoomableIcon
1306uid 613,0
1307sl 0
1308va (VaSet
1309vasetType 1
1310fg "49152,49152,49152"
1311)
1312xt "16250,30250,17750,31750"
1313iconName "VhdlFileViewIcon.png"
1314iconMaskName "VhdlFileViewIcon.msk"
1315ftype 10
1316)
1317ordering 1
1318viewiconposition 0
1319portVis (PortSigDisplay
1320sTC 0
1321sF 0
1322)
1323archFileType "UNKNOWN"
1324)
1325*38 (Wire
1326uid 93,0
1327shape (OrthoPolyLine
1328uid 94,0
1329va (VaSet
1330vasetType 3
1331)
1332xt "10000,30000,15250,30000"
1333pts [
1334"10000,30000"
1335"15250,30000"
1336]
1337)
1338end &29
1339sat 16
1340eat 32
1341st 0
1342sf 1
1343si 0
1344tg (WTG
1345uid 99,0
1346ps "ConnStartEndStrategy"
1347stg "STSignalDisplayStrategy"
1348f (Text
1349uid 100,0
1350va (VaSet
1351)
1352xt "11000,29000,14200,30000"
1353st "enable_i"
1354blo "11000,29800"
1355tm "WireNameMgr"
1356)
1357)
1358on &4
1359)
1360*39 (Wire
1361uid 109,0
1362shape (OrthoPolyLine
1363uid 110,0
1364va (VaSet
1365vasetType 3
1366)
1367xt "10000,29000,15250,29000"
1368pts [
1369"10000,29000"
1370"15250,29000"
1371]
1372)
1373end &30
1374sat 16
1375eat 32
1376st 0
1377sf 1
1378si 0
1379tg (WTG
1380uid 115,0
1381ps "ConnStartEndStrategy"
1382stg "STSignalDisplayStrategy"
1383f (Text
1384uid 116,0
1385va (VaSet
1386)
1387xt "11000,28000,13900,29000"
1388st "synch_i"
1389blo "11000,28800"
1390tm "WireNameMgr"
1391)
1392)
1393on &3
1394)
1395*40 (Wire
1396uid 117,0
1397shape (OrthoPolyLine
1398uid 118,0
1399va (VaSet
1400vasetType 3
1401lineWidth 2
1402)
1403xt "34750,28000,48000,28000"
1404pts [
1405"34750,28000"
1406"48000,28000"
1407]
1408)
1409start &32
1410sat 32
1411eat 16
1412sty 1
1413st 0
1414sf 1
1415si 0
1416tg (WTG
1417uid 123,0
1418ps "ConnStartEndStrategy"
1419stg "STSignalDisplayStrategy"
1420f (Text
1421uid 124,0
1422va (VaSet
1423)
1424xt "36000,27000,47400,28000"
1425st "time_o : (TIMER_WIDTH-1:0)"
1426blo "36000,27800"
1427tm "WireNameMgr"
1428)
1429)
1430on &1
1431)
1432*41 (Wire
1433uid 125,0
1434shape (OrthoPolyLine
1435uid 126,0
1436va (VaSet
1437vasetType 3
1438)
1439xt "34750,29000,48000,29000"
1440pts [
1441"34750,29000"
1442"48000,29000"
1443]
1444)
1445start &31
1446sat 32
1447eat 16
1448st 0
1449sf 1
1450si 0
1451tg (WTG
1452uid 131,0
1453ps "ConnStartEndStrategy"
1454stg "STSignalDisplayStrategy"
1455f (Text
1456uid 132,0
1457va (VaSet
1458)
1459xt "36000,28000,39900,29000"
1460st "synched_o"
1461blo "36000,28800"
1462tm "WireNameMgr"
1463)
1464)
1465on &2
1466)
1467*42 (Wire
1468uid 546,0
1469shape (OrthoPolyLine
1470uid 547,0
1471va (VaSet
1472vasetType 3
1473)
1474xt "5000,14000,8250,14000"
1475pts [
1476"5000,14000"
1477"8250,14000"
1478]
1479)
1480end &17
1481sat 16
1482eat 32
1483st 0
1484sf 1
1485si 0
1486tg (WTG
1487uid 550,0
1488ps "ConnStartEndStrategy"
1489stg "STSignalDisplayStrategy"
1490f (Text
1491uid 551,0
1492va (VaSet
1493)
1494xt "6000,13000,7300,14000"
1495st "clk"
1496blo "6000,13800"
1497tm "WireNameMgr"
1498)
1499)
1500on &26
1501)
1502*43 (Wire
1503uid 552,0
1504shape (OrthoPolyLine
1505uid 553,0
1506va (VaSet
1507vasetType 3
1508)
1509xt "3000,15000,8250,15000"
1510pts [
1511"3000,15000"
1512"8250,15000"
1513]
1514)
1515end &19
1516sat 16
1517eat 32
1518st 0
1519sf 1
1520si 0
1521tg (WTG
1522uid 556,0
1523ps "ConnStartEndStrategy"
1524stg "STSignalDisplayStrategy"
1525f (Text
1526uid 557,0
1527va (VaSet
1528)
1529xt "4000,14000,6900,15000"
1530st "synch_i"
1531blo "4000,14800"
1532tm "WireNameMgr"
1533)
1534)
1535on &3
1536)
1537*44 (Wire
1538uid 560,0
1539shape (OrthoPolyLine
1540uid 561,0
1541va (VaSet
1542vasetType 3
1543)
1544xt "1000,16000,8250,16000"
1545pts [
1546"1000,16000"
1547"8250,16000"
1548]
1549)
1550end &21
1551sat 16
1552eat 32
1553st 0
1554sf 1
1555si 0
1556tg (WTG
1557uid 564,0
1558ps "ConnStartEndStrategy"
1559stg "STSignalDisplayStrategy"
1560f (Text
1561uid 565,0
1562va (VaSet
1563)
1564xt "2000,15000,7400,16000"
1565st "reset_synch_i"
1566blo "2000,15800"
1567tm "WireNameMgr"
1568)
1569)
1570on &27
1571)
1572*45 (Wire
1573uid 566,0
1574shape (OrthoPolyLine
1575uid 567,0
1576va (VaSet
1577vasetType 3
1578)
1579xt "3000,17000,8250,17000"
1580pts [
1581"3000,17000"
1582"8250,17000"
1583]
1584)
1585end &22
1586sat 16
1587eat 32
1588st 0
1589sf 1
1590si 0
1591tg (WTG
1592uid 570,0
1593ps "ConnStartEndStrategy"
1594stg "STSignalDisplayStrategy"
1595f (Text
1596uid 571,0
1597va (VaSet
1598)
1599xt "4000,16000,7200,17000"
1600st "enable_i"
1601blo "4000,16800"
1602tm "WireNameMgr"
1603)
1604)
1605on &4
1606)
1607*46 (Wire
1608uid 572,0
1609shape (OrthoPolyLine
1610uid 573,0
1611va (VaSet
1612vasetType 3
1613lineWidth 2
1614)
1615xt "29750,14000,43000,14000"
1616pts [
1617"29750,14000"
1618"43000,14000"
1619]
1620)
1621start &18
1622sat 32
1623eat 16
1624sty 1
1625st 0
1626sf 1
1627si 0
1628tg (WTG
1629uid 576,0
1630ps "ConnStartEndStrategy"
1631stg "STSignalDisplayStrategy"
1632f (Text
1633uid 577,0
1634va (VaSet
1635)
1636xt "31000,13000,42400,14000"
1637st "time_o : (TIMER_WIDTH-1:0)"
1638blo "31000,13800"
1639tm "WireNameMgr"
1640)
1641)
1642on &1
1643)
1644*47 (Wire
1645uid 578,0
1646shape (OrthoPolyLine
1647uid 579,0
1648va (VaSet
1649vasetType 3
1650)
1651xt "29750,15000,36000,15000"
1652pts [
1653"29750,15000"
1654"36000,15000"
1655]
1656)
1657start &20
1658sat 32
1659eat 16
1660st 0
1661sf 1
1662si 0
1663tg (WTG
1664uid 582,0
1665ps "ConnStartEndStrategy"
1666stg "STSignalDisplayStrategy"
1667f (Text
1668uid 583,0
1669va (VaSet
1670)
1671xt "31000,14000,34900,15000"
1672st "synched_o"
1673blo "31000,14800"
1674tm "WireNameMgr"
1675)
1676)
1677on &2
1678)
1679*48 (Wire
1680uid 622,0
1681shape (OrthoPolyLine
1682uid 623,0
1683va (VaSet
1684vasetType 3
1685)
1686xt "34750,30000,38000,30000"
1687pts [
1688"34750,30000"
1689"38000,30000"
1690]
1691)
1692start &33
1693sat 32
1694eat 16
1695stc 0
1696st 0
1697si 0
1698tg (WTG
1699uid 626,0
1700ps "ConnStartEndStrategy"
1701stg "STSignalDisplayStrategy"
1702f (Text
1703uid 627,0
1704va (VaSet
1705)
1706xt "36000,29000,37300,30000"
1707st "clk"
1708blo "36000,29800"
1709tm "WireNameMgr"
1710)
1711)
1712on &26
1713)
1714*49 (Wire
1715uid 628,0
1716shape (OrthoPolyLine
1717uid 629,0
1718va (VaSet
1719vasetType 3
1720)
1721xt "34750,31000,42000,31000"
1722pts [
1723"34750,31000"
1724"42000,31000"
1725]
1726)
1727start &34
1728sat 32
1729eat 16
1730stc 0
1731st 0
1732si 0
1733tg (WTG
1734uid 632,0
1735ps "ConnStartEndStrategy"
1736stg "STSignalDisplayStrategy"
1737f (Text
1738uid 633,0
1739va (VaSet
1740)
1741xt "36000,30000,41400,31000"
1742st "reset_synch_i"
1743blo "36000,30800"
1744tm "WireNameMgr"
1745)
1746)
1747on &27
1748)
1749]
1750bg "65535,65535,65535"
1751grid (Grid
1752origin "0,0"
1753isVisible 1
1754isActive 1
1755xSpacing 1000
1756xySpacing 1000
1757xShown 1
1758yShown 1
1759color "26368,26368,26368"
1760)
1761packageList *50 (PackageList
1762uid 175,0
1763stg "VerticalLayoutStrategy"
1764textVec [
1765*51 (Text
1766uid 176,0
1767va (VaSet
1768font "arial,8,1"
1769)
1770xt "0,0,5400,1000"
1771st "Package List"
1772blo "0,800"
1773)
1774*52 (MLText
1775uid 177,0
1776va (VaSet
1777)
1778xt "0,1000,12400,5000"
1779st "LIBRARY ieee;
1780USE ieee.std_logic_1164.ALL;
1781USE ieee.std_logic_arith.ALL;
1782USE ieee.std_logic_unsigned.all;"
1783tm "PackageList"
1784)
1785]
1786)
1787compDirBlock (MlTextGroup
1788uid 178,0
1789stg "VerticalLayoutStrategy"
1790textVec [
1791*53 (Text
1792uid 179,0
1793va (VaSet
1794isHidden 1
1795font "Arial,8,1"
1796)
1797xt "20000,0,28100,1000"
1798st "Compiler Directives"
1799blo "20000,800"
1800)
1801*54 (Text
1802uid 180,0
1803va (VaSet
1804isHidden 1
1805font "Arial,8,1"
1806)
1807xt "20000,1000,29600,2000"
1808st "Pre-module directives:"
1809blo "20000,1800"
1810)
1811*55 (MLText
1812uid 181,0
1813va (VaSet
1814isHidden 1
1815)
1816xt "20000,2000,27500,4000"
1817st "`resetall
1818`timescale 1ns/10ps"
1819tm "BdCompilerDirectivesTextMgr"
1820)
1821*56 (Text
1822uid 182,0
1823va (VaSet
1824isHidden 1
1825font "Arial,8,1"
1826)
1827xt "20000,4000,30100,5000"
1828st "Post-module directives:"
1829blo "20000,4800"
1830)
1831*57 (MLText
1832uid 183,0
1833va (VaSet
1834isHidden 1
1835)
1836xt "20000,0,20000,0"
1837tm "BdCompilerDirectivesTextMgr"
1838)
1839*58 (Text
1840uid 184,0
1841va (VaSet
1842isHidden 1
1843font "Arial,8,1"
1844)
1845xt "20000,5000,29900,6000"
1846st "End-module directives:"
1847blo "20000,5800"
1848)
1849*59 (MLText
1850uid 185,0
1851va (VaSet
1852isHidden 1
1853)
1854xt "20000,6000,20000,6000"
1855tm "BdCompilerDirectivesTextMgr"
1856)
1857]
1858associable 1
1859)
1860windowSize "0,22,1281,1024"
1861viewArea "-21800,-200,74751,77423"
1862cachedDiagramExtent "0,0,66000,49000"
1863hasePageBreakOrigin 1
1864pageBreakOrigin "-7000,0"
1865lastUid 654,0
1866defaultCommentText (CommentText
1867shape (Rectangle
1868layer 0
1869va (VaSet
1870vasetType 1
1871fg "65280,65280,46080"
1872lineColor "0,0,32768"
1873)
1874xt "0,0,15000,5000"
1875)
1876text (MLText
1877va (VaSet
1878fg "0,0,32768"
1879)
1880xt "200,200,2000,1200"
1881st "
1882Text
1883"
1884tm "CommentText"
1885wrapOption 3
1886visibleHeight 4600
1887visibleWidth 14600
1888)
1889)
1890defaultPanel (Panel
1891shape (RectFrame
1892va (VaSet
1893vasetType 1
1894fg "65535,65535,65535"
1895lineColor "32768,0,0"
1896lineWidth 3
1897)
1898xt "0,0,20000,20000"
1899)
1900title (TextAssociate
1901ps "TopLeftStrategy"
1902text (Text
1903va (VaSet
1904font "Arial,8,1"
1905)
1906xt "1000,1000,3800,2000"
1907st "Panel0"
1908blo "1000,1800"
1909tm "PanelText"
1910)
1911)
1912)
1913defaultBlk (Blk
1914shape (Rectangle
1915va (VaSet
1916vasetType 1
1917fg "39936,56832,65280"
1918lineColor "0,0,32768"
1919lineWidth 2
1920)
1921xt "0,0,8000,10000"
1922)
1923ttg (MlTextGroup
1924ps "CenterOffsetStrategy"
1925stg "VerticalLayoutStrategy"
1926textVec [
1927*60 (Text
1928va (VaSet
1929font "Arial,8,1"
1930)
1931xt "2200,3500,5800,4500"
1932st "<library>"
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2501pts [
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2613second (MLText
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2762thePort (LogicalPort
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2765t ""
2766o 0
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2790thePort (LogicalPort
2791m 3
2792decl (Decl
2793n "Port"
2794t ""
2795o 0
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2798)
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2808uid 2,0
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2825preUserLabel (Text
2826uid 4,0
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2835preUserText (MLText
2836uid 5,0
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2844diagSignalLabel (Text
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2853postUserLabel (Text
2854uid 7,0
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2859xt "20000,0,24700,1000"
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2863postUserText (MLText
2864uid 8,0
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2873commonDM (CommonDM
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2883*83 (TitleRowHdr
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2885*84 (FilterRowHdr
2886)
2887*85 (RefLabelColHdr
2888tm "RefLabelColHdrMgr"
2889)
2890*86 (RowExpandColHdr
2891tm "RowExpandColHdrMgr"
2892)
2893*87 (GroupColHdr
2894tm "GroupColHdrMgr"
2895)
2896*88 (NameColHdr
2897tm "BlockDiagramNameColHdrMgr"
2898)
2899*89 (ModeColHdr
2900tm "BlockDiagramModeColHdrMgr"
2901)
2902*90 (TypeColHdr
2903tm "BlockDiagramTypeColHdrMgr"
2904)
2905*91 (BoundsColHdr
2906tm "BlockDiagramBoundsColHdrMgr"
2907)
2908*92 (InitColHdr
2909tm "BlockDiagramInitColHdrMgr"
2910)
2911*93 (EolColHdr
2912tm "BlockDiagramEolColHdrMgr"
2913)
2914*94 (LeafLogPort
2915port (LogicalPort
2916m 4
2917decl (Decl
2918n "time_o"
2919t "std_logic_vector"
2920b "( TIMER_WIDTH-1 downto 0)"
2921o 1
2922suid 1,0
2923)
2924)
2925uid 165,0
2926)
2927*95 (LeafLogPort
2928port (LogicalPort
2929m 4
2930decl (Decl
2931n "synched_o"
2932t "std_logic"
2933o 2
2934suid 2,0
2935i "'0'"
2936)
2937)
2938uid 167,0
2939)
2940*96 (LeafLogPort
2941port (LogicalPort
2942m 4
2943decl (Decl
2944n "synch_i"
2945t "std_logic"
2946o 4
2947suid 4,0
2948)
2949)
2950uid 171,0
2951)
2952*97 (LeafLogPort
2953port (LogicalPort
2954m 4
2955decl (Decl
2956n "enable_i"
2957t "std_logic"
2958o 5
2959suid 5,0
2960)
2961)
2962uid 173,0
2963)
2964*98 (LeafLogPort
2965port (LogicalPort
2966m 4
2967decl (Decl
2968n "clk"
2969t "std_logic"
2970o 5
2971suid 8,0
2972)
2973)
2974uid 584,0
2975)
2976*99 (LeafLogPort
2977port (LogicalPort
2978m 4
2979decl (Decl
2980n "reset_synch_i"
2981t "std_logic"
2982o 6
2983suid 9,0
2984)
2985)
2986uid 586,0
2987)
2988]
2989)
2990pdm (PhysicalDM
2991displayShortBounds 1
2992editShortBounds 1
2993uid 201,0
2994optionalChildren [
2995*100 (Sheet
2996sheetRow (SheetRow
2997headerVa (MVa
2998cellColor "49152,49152,49152"
2999fontColor "0,0,0"
3000font "Tahoma,10,0"
3001)
3002cellVa (MVa
3003cellColor "65535,65535,65535"
3004fontColor "0,0,0"
3005font "Tahoma,10,0"
3006)
3007groupVa (MVa
3008cellColor "39936,56832,65280"
3009fontColor "0,0,0"
3010font "Tahoma,10,0"
3011)
3012emptyMRCItem *101 (MRCItem
3013litem &81
3014pos 6
3015dimension 20
3016)
3017uid 203,0
3018optionalChildren [
3019*102 (MRCItem
3020litem &82
3021pos 0
3022dimension 20
3023uid 204,0
3024)
3025*103 (MRCItem
3026litem &83
3027pos 1
3028dimension 23
3029uid 205,0
3030)
3031*104 (MRCItem
3032litem &84
3033pos 2
3034hidden 1
3035dimension 20
3036uid 206,0
3037)
3038*105 (MRCItem
3039litem &94
3040pos 0
3041dimension 20
3042uid 166,0
3043)
3044*106 (MRCItem
3045litem &95
3046pos 1
3047dimension 20
3048uid 168,0
3049)
3050*107 (MRCItem
3051litem &96
3052pos 2
3053dimension 20
3054uid 172,0
3055)
3056*108 (MRCItem
3057litem &97
3058pos 3
3059dimension 20
3060uid 174,0
3061)
3062*109 (MRCItem
3063litem &98
3064pos 4
3065dimension 20
3066uid 585,0
3067)
3068*110 (MRCItem
3069litem &99
3070pos 5
3071dimension 20
3072uid 587,0
3073)
3074]
3075)
3076sheetCol (SheetCol
3077propVa (MVa
3078cellColor "0,49152,49152"
3079fontColor "0,0,0"
3080font "Tahoma,10,0"
3081textAngle 90
3082)
3083uid 207,0
3084optionalChildren [
3085*111 (MRCItem
3086litem &85
3087pos 0
3088dimension 20
3089uid 208,0
3090)
3091*112 (MRCItem
3092litem &87
3093pos 1
3094dimension 50
3095uid 209,0
3096)
3097*113 (MRCItem
3098litem &88
3099pos 2
3100dimension 100
3101uid 210,0
3102)
3103*114 (MRCItem
3104litem &89
3105pos 3
3106dimension 50
3107uid 211,0
3108)
3109*115 (MRCItem
3110litem &90
3111pos 4
3112dimension 100
3113uid 212,0
3114)
3115*116 (MRCItem
3116litem &91
3117pos 5
3118dimension 100
3119uid 213,0
3120)
3121*117 (MRCItem
3122litem &92
3123pos 6
3124dimension 50
3125uid 214,0
3126)
3127*118 (MRCItem
3128litem &93
3129pos 7
3130dimension 80
3131uid 215,0
3132)
3133]
3134)
3135fixedCol 4
3136fixedRow 2
3137name "Ports"
3138uid 202,0
3139vaOverrides [
3140]
3141)
3142]
3143)
3144uid 187,0
3145)
3146genericsCommonDM (CommonDM
3147ldm (LogicalDM
3148emptyRow *119 (LEmptyRow
3149)
3150uid 217,0
3151optionalChildren [
3152*120 (RefLabelRowHdr
3153)
3154*121 (TitleRowHdr
3155)
3156*122 (FilterRowHdr
3157)
3158*123 (RefLabelColHdr
3159tm "RefLabelColHdrMgr"
3160)
3161*124 (RowExpandColHdr
3162tm "RowExpandColHdrMgr"
3163)
3164*125 (GroupColHdr
3165tm "GroupColHdrMgr"
3166)
3167*126 (NameColHdr
3168tm "GenericNameColHdrMgr"
3169)
3170*127 (TypeColHdr
3171tm "GenericTypeColHdrMgr"
3172)
3173*128 (InitColHdr
3174tm "GenericValueColHdrMgr"
3175)
3176*129 (PragmaColHdr
3177tm "GenericPragmaColHdrMgr"
3178)
3179*130 (EolColHdr
3180tm "GenericEolColHdrMgr"
3181)
3182*131 (LogGeneric
3183generic (GiElement
3184name "TIMER_WIDTH"
3185type "integer"
3186value "32"
3187)
3188uid 9,0
3189)
3190*132 (LogGeneric
3191generic (GiElement
3192name "PRESCALER"
3193type "integer"
3194value "2500"
3195)
3196uid 11,0
3197)
3198]
3199)
3200pdm (PhysicalDM
3201displayShortBounds 1
3202editShortBounds 1
3203uid 229,0
3204optionalChildren [
3205*133 (Sheet
3206sheetRow (SheetRow
3207headerVa (MVa
3208cellColor "49152,49152,49152"
3209fontColor "0,0,0"
3210font "Tahoma,10,0"
3211)
3212cellVa (MVa
3213cellColor "65535,65535,65535"
3214fontColor "0,0,0"
3215font "Tahoma,10,0"
3216)
3217groupVa (MVa
3218cellColor "39936,56832,65280"
3219fontColor "0,0,0"
3220font "Tahoma,10,0"
3221)
3222emptyMRCItem *134 (MRCItem
3223litem &119
3224pos 2
3225dimension 20
3226)
3227uid 231,0
3228optionalChildren [
3229*135 (MRCItem
3230litem &120
3231pos 0
3232dimension 20
3233uid 232,0
3234)
3235*136 (MRCItem
3236litem &121
3237pos 1
3238dimension 23
3239uid 233,0
3240)
3241*137 (MRCItem
3242litem &122
3243pos 2
3244hidden 1
3245dimension 20
3246uid 234,0
3247)
3248*138 (MRCItem
3249litem &131
3250pos 0
3251dimension 20
3252uid 10,0
3253)
3254*139 (MRCItem
3255litem &132
3256pos 1
3257dimension 20
3258uid 12,0
3259)
3260]
3261)
3262sheetCol (SheetCol
3263propVa (MVa
3264cellColor "0,49152,49152"
3265fontColor "0,0,0"
3266font "Tahoma,10,0"
3267textAngle 90
3268)
3269uid 235,0
3270optionalChildren [
3271*140 (MRCItem
3272litem &123
3273pos 0
3274dimension 20
3275uid 236,0
3276)
3277*141 (MRCItem
3278litem &125
3279pos 1
3280dimension 50
3281uid 237,0
3282)
3283*142 (MRCItem
3284litem &126
3285pos 2
3286dimension 100
3287uid 238,0
3288)
3289*143 (MRCItem
3290litem &127
3291pos 3
3292dimension 100
3293uid 239,0
3294)
3295*144 (MRCItem
3296litem &128
3297pos 4
3298dimension 50
3299uid 240,0
3300)
3301*145 (MRCItem
3302litem &129
3303pos 5
3304dimension 50
3305uid 241,0
3306)
3307*146 (MRCItem
3308litem &130
3309pos 6
3310dimension 80
3311uid 242,0
3312)
3313]
3314)
3315fixedCol 3
3316fixedRow 2
3317name "Ports"
3318uid 230,0
3319vaOverrides [
3320]
3321)
3322]
3323)
3324uid 216,0
3325type 1
3326)
3327activeModelName "BlockDiag"
3328)
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