source: firmware/FAD/FACT_FAD_TB_lib/hds/w5300_interface_tb/struct.bd@ 13408

Last change on this file since 13408 was 11755, checked in by neise, 13 years ago
reinit of this svn repos .... it was all too messy deleted the old folders and restarted with FACT_FAD_lib only. (well and the testbenches)
File size: 56.7 KB
Line 
1DocumentHdrVersion "1.1"
2Header (DocumentHdr
3version 2
4dmPackageRefs [
5(DmPackageRef
6library "IEEE"
7unitName "STD_LOGIC_1164"
8itemName "ALL"
9)
10(DmPackageRef
11library "IEEE"
12unitName "NUMERIC_STD"
13itemName "ALL"
14)
15(DmPackageRef
16library "ieee"
17unitName "std_logic_unsigned"
18)
19]
20instances [
21(Instance
22name "Inst_W5300_Interface"
23duLibraryName "FACT_FAD_lib"
24duName "w5300_interface"
25elements [
26]
27mwi 0
28uid 65,0
29)
30(Instance
31name "U_1"
32duLibraryName "FACT_FAD_TB_lib"
33duName "w5300_interface_tester"
34elements [
35]
36mwi 0
37uid 179,0
38)
39(Instance
40name "U_2"
41duLibraryName "FACT_FAD_TB_lib"
42duName "clock_generator"
43elements [
44(GiElement
45name "clock_period"
46type "time"
47value "20 ns"
48)
49(GiElement
50name "reset_time"
51type "time"
52value "50 ns"
53)
54]
55mwi 0
56uid 617,0
57)
58]
59libraryRefs [
60"IEEE"
61]
62)
63version "29.1"
64appVersion "2009.2 (Build 10)"
65noEmbeddedEditors 1
66model (BlockDiag
67VExpander (VariableExpander
68vvMap [
69(vvPair
70variable "HDLDir"
71value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hdl"
72)
73(vvPair
74variable "HDSDir"
75value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
76)
77(vvPair
78variable "SideDataDesignDir"
79value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_interface_tb\\struct.bd.info"
80)
81(vvPair
82variable "SideDataUserDir"
83value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_interface_tb\\struct.bd.user"
84)
85(vvPair
86variable "SourceDir"
87value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
88)
89(vvPair
90variable "appl"
91value "HDL Designer"
92)
93(vvPair
94variable "arch_name"
95value "struct"
96)
97(vvPair
98variable "config"
99value "%(unit)_%(view)_config"
100)
101(vvPair
102variable "d"
103value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_interface_tb"
104)
105(vvPair
106variable "d_logical"
107value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_interface_tb"
108)
109(vvPair
110variable "date"
111value "31.05.2011"
112)
113(vvPair
114variable "day"
115value "Di"
116)
117(vvPair
118variable "day_long"
119value "Dienstag"
120)
121(vvPair
122variable "dd"
123value "31"
124)
125(vvPair
126variable "entity_name"
127value "w5300_interface_tb"
128)
129(vvPair
130variable "ext"
131value "<TBD>"
132)
133(vvPair
134variable "f"
135value "struct.bd"
136)
137(vvPair
138variable "f_logical"
139value "struct.bd"
140)
141(vvPair
142variable "f_noext"
143value "struct"
144)
145(vvPair
146variable "group"
147value "UNKNOWN"
148)
149(vvPair
150variable "host"
151value "E5B-LABOR6"
152)
153(vvPair
154variable "language"
155value "VHDL"
156)
157(vvPair
158variable "library"
159value "FACT_FAD_TB_lib"
160)
161(vvPair
162variable "library_downstream_HdsLintPlugin"
163value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/designcheck"
164)
165(vvPair
166variable "library_downstream_ISEPARInvoke"
167value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
168)
169(vvPair
170variable "library_downstream_ImpactInvoke"
171value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
172)
173(vvPair
174variable "library_downstream_ModelSimCompiler"
175value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/work"
176)
177(vvPair
178variable "library_downstream_XSTDataPrep"
179value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
180)
181(vvPair
182variable "mm"
183value "05"
184)
185(vvPair
186variable "module_name"
187value "w5300_interface_tb"
188)
189(vvPair
190variable "month"
191value "Mai"
192)
193(vvPair
194variable "month_long"
195value "Mai"
196)
197(vvPair
198variable "p"
199value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_interface_tb\\struct.bd"
200)
201(vvPair
202variable "p_logical"
203value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_interface_tb\\struct.bd"
204)
205(vvPair
206variable "package_name"
207value "<Undefined Variable>"
208)
209(vvPair
210variable "project_name"
211value "FACT_FAD"
212)
213(vvPair
214variable "series"
215value "HDL Designer Series"
216)
217(vvPair
218variable "task_DesignCompilerPath"
219value "<TBD>"
220)
221(vvPair
222variable "task_LeonardoPath"
223value "<TBD>"
224)
225(vvPair
226variable "task_ModelSimPath"
227value "C:\\modeltech_6.6a\\win32"
228)
229(vvPair
230variable "task_NC-SimPath"
231value "<TBD>"
232)
233(vvPair
234variable "task_PrecisionRTLPath"
235value "<TBD>"
236)
237(vvPair
238variable "task_QuestaSimPath"
239value "<TBD>"
240)
241(vvPair
242variable "task_VCSPath"
243value "<TBD>"
244)
245(vvPair
246variable "this_ext"
247value "bd"
248)
249(vvPair
250variable "this_file"
251value "struct"
252)
253(vvPair
254variable "this_file_logical"
255value "struct"
256)
257(vvPair
258variable "time"
259value "13:38:18"
260)
261(vvPair
262variable "unit"
263value "w5300_interface_tb"
264)
265(vvPair
266variable "user"
267value "dneise"
268)
269(vvPair
270variable "version"
271value "2009.2 (Build 10)"
272)
273(vvPair
274variable "view"
275value "struct"
276)
277(vvPair
278variable "year"
279value "2011"
280)
281(vvPair
282variable "yy"
283value "11"
284)
285]
286)
287LanguageMgr "VhdlLangMgr"
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1306tm "CommentText"
1307wrapOption 3
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1312ignorePrefs 1
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1342ignorePrefs 1
1343titleBlock 1
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1368wrapOption 3
1369visibleHeight 1000
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1373ignorePrefs 1
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1397ju 0
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1399wrapOption 3
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1401visibleWidth 21000
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1404ignorePrefs 1
1405titleBlock 1
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1435ignorePrefs 1
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1466ignorePrefs 1
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1549o 1
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1553)
1554)
1555*49 (CptPort
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1579)
1580)
1581thePort (LogicalPort
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1617tm "CommentText"
1618wrapOption 3
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1622included 1
1623excludeCommentLeader 1
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1696(GiElement
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1700)
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1702)
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1721*54 (Net
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1749"24000,21000"
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1752start &3
1753sat 32
1754eat 16
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1756sf 1
1757si 0
1758tg (WTG
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1764va (VaSet
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1766xt "17000,20000,20600,21000"
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1769tm "WireNameMgr"
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1772on &19
1773)
1774*56 (Wire
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1789eat 16
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1791sf 1
1792si 0
1793tg (WTG
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1801xt "17000,21000,18200,22000"
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1804tm "WireNameMgr"
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1806)
1807on &20
1808)
1809*57 (Wire
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1819"24000,23000"
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1822start &5
1823sat 32
1824eat 16
1825st 0
1826sf 1
1827si 0
1828tg (WTG
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1834va (VaSet
1835)
1836xt "17000,22000,18200,23000"
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1839tm "WireNameMgr"
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1841)
1842on &21
1843)
1844*58 (Wire
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1848va (VaSet
1849vasetType 3
1850)
1851xt "15750,24000,24000,24000"
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1853"15750,24000"
1854"24000,24000"
1855]
1856)
1857start &6
1858sat 32
1859eat 16
1860st 0
1861sf 1
1862si 0
1863tg (WTG
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1870)
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1875)
1876)
1877on &22
1878)
1879*59 (Wire
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1886)
1887xt "15750,25000,24000,25000"
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1889"15750,25000"
1890"24000,25000"
1891]
1892)
1893start &8
1894sat 32
1895eat 16
1896sty 1
1897st 0
1898sf 1
1899si 0
1900tg (WTG
1901uid 113,0
1902ps "ConnStartEndStrategy"
1903stg "STSignalDisplayStrategy"
1904f (Text
1905uid 114,0
1906va (VaSet
1907)
1908xt "17000,24000,23300,25000"
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1911tm "WireNameMgr"
1912)
1913)
1914on &23
1915)
1916*60 (Wire
1917uid 117,0
1918shape (OrthoPolyLine
1919uid 118,0
1920va (VaSet
1921vasetType 3
1922lineWidth 2
1923)
1924xt "15750,26000,24000,26000"
1925pts [
1926"15750,26000"
1927"24000,26000"
1928]
1929)
1930start &9
1931sat 32
1932eat 16
1933sty 1
1934st 0
1935sf 1
1936si 0
1937tg (WTG
1938uid 121,0
1939ps "ConnStartEndStrategy"
1940stg "STSignalDisplayStrategy"
1941f (Text
1942uid 122,0
1943va (VaSet
1944)
1945xt "17000,25000,23000,26000"
1946st "wiz_addr : (9:0)"
1947blo "17000,25800"
1948tm "WireNameMgr"
1949)
1950)
1951on &24
1952)
1953*61 (Wire
1954uid 125,0
1955shape (OrthoPolyLine
1956uid 126,0
1957va (VaSet
1958vasetType 3
1959lineWidth 2
1960)
1961xt "15750,27000,24000,27000"
1962pts [
1963"15750,27000"
1964"24000,27000"
1965]
1966)
1967start &13
1968sat 32
1969eat 16
1970sty 1
1971st 0
1972sf 1
1973si 0
1974tg (WTG
1975uid 129,0
1976ps "ConnStartEndStrategy"
1977stg "STSignalDisplayStrategy"
1978f (Text
1979uid 130,0
1980va (VaSet
1981)
1982xt "17000,26000,22600,27000"
1983st "data_o : (15:0)"
1984blo "17000,26800"
1985tm "WireNameMgr"
1986)
1987)
1988on &25
1989)
1990*62 (Wire
1991uid 133,0
1992shape (OrthoPolyLine
1993uid 134,0
1994va (VaSet
1995vasetType 3
1996)
1997xt "-14250,5000,-750,21000"
1998pts [
1999"-14250,5000"
2000"-4000,5000"
2001"-4000,21000"
2002"-750,21000"
2003]
2004)
2005start &48
2006end &2
2007sat 32
2008eat 32
2009st 0
2010sf 1
2011si 0
2012tg (WTG
2013uid 137,0
2014ps "ConnStartEndStrategy"
2015stg "STSignalDisplayStrategy"
2016f (Text
2017uid 138,0
2018va (VaSet
2019)
2020xt "-12250,4000,-10950,5000"
2021st "clk"
2022blo "-12250,4800"
2023tm "WireNameMgr"
2024)
2025)
2026on &26
2027)
2028*63 (Wire
2029uid 141,0
2030shape (OrthoPolyLine
2031uid 142,0
2032va (VaSet
2033vasetType 3
2034)
2035xt "-8000,22000,-750,22000"
2036pts [
2037"-8000,22000"
2038"-750,22000"
2039]
2040)
2041end &7
2042sat 16
2043eat 32
2044st 0
2045sf 1
2046si 0
2047tg (WTG
2048uid 145,0
2049ps "ConnStartEndStrategy"
2050stg "STSignalDisplayStrategy"
2051f (Text
2052uid 146,0
2053va (VaSet
2054)
2055xt "-7000,21000,-5800,22000"
2056st "int"
2057blo "-7000,21800"
2058tm "WireNameMgr"
2059)
2060)
2061on &27
2062)
2063*64 (Wire
2064uid 149,0
2065shape (OrthoPolyLine
2066uid 150,0
2067va (VaSet
2068vasetType 3
2069)
2070xt "-8000,23000,-750,23000"
2071pts [
2072"-8000,23000"
2073"-750,23000"
2074]
2075)
2076end &10
2077sat 16
2078eat 32
2079st 0
2080sf 1
2081si 0
2082tg (WTG
2083uid 153,0
2084ps "ConnStartEndStrategy"
2085stg "STSignalDisplayStrategy"
2086f (Text
2087uid 154,0
2088va (VaSet
2089)
2090xt "-7000,22000,-4500,23000"
2091st "read_i"
2092blo "-7000,22800"
2093tm "WireNameMgr"
2094)
2095)
2096on &28
2097)
2098*65 (Wire
2099uid 157,0
2100shape (OrthoPolyLine
2101uid 158,0
2102va (VaSet
2103vasetType 3
2104)
2105xt "-8000,24000,-750,24000"
2106pts [
2107"-8000,24000"
2108"-750,24000"
2109]
2110)
2111end &11
2112sat 16
2113eat 32
2114st 0
2115sf 1
2116si 0
2117tg (WTG
2118uid 161,0
2119ps "ConnStartEndStrategy"
2120stg "STSignalDisplayStrategy"
2121f (Text
2122uid 162,0
2123va (VaSet
2124)
2125xt "-7000,23000,-4400,24000"
2126st "write_i"
2127blo "-7000,23800"
2128tm "WireNameMgr"
2129)
2130)
2131on &29
2132)
2133*66 (Wire
2134uid 165,0
2135shape (OrthoPolyLine
2136uid 166,0
2137va (VaSet
2138vasetType 3
2139lineWidth 2
2140)
2141xt "-8000,25000,-750,25000"
2142pts [
2143"-8000,25000"
2144"-750,25000"
2145]
2146)
2147end &12
2148sat 16
2149eat 32
2150sty 1
2151st 0
2152sf 1
2153si 0
2154tg (WTG
2155uid 169,0
2156ps "ConnStartEndStrategy"
2157stg "STSignalDisplayStrategy"
2158f (Text
2159uid 170,0
2160va (VaSet
2161)
2162xt "-7000,24000,-1900,25000"
2163st "addr_i : (9:0)"
2164blo "-7000,24800"
2165tm "WireNameMgr"
2166)
2167)
2168on &30
2169)
2170*67 (Wire
2171uid 173,0
2172shape (OrthoPolyLine
2173uid 174,0
2174va (VaSet
2175vasetType 3
2176lineWidth 2
2177)
2178xt "-8000,26000,-750,26000"
2179pts [
2180"-8000,26000"
2181"-750,26000"
2182]
2183)
2184end &14
2185sat 16
2186eat 32
2187sty 1
2188st 0
2189sf 1
2190si 0
2191tg (WTG
2192uid 177,0
2193ps "ConnStartEndStrategy"
2194stg "STSignalDisplayStrategy"
2195f (Text
2196uid 178,0
2197va (VaSet
2198)
2199xt "-7000,25000,-1600,26000"
2200st "data_i : (15:0)"
2201blo "-7000,25800"
2202tm "WireNameMgr"
2203)
2204)
2205on &31
2206)
2207*68 (Wire
2208uid 189,0
2209shape (OrthoPolyLine
2210uid 190,0
2211va (VaSet
2212vasetType 3
2213)
2214xt "51000,18000,60000,18000"
2215pts [
2216"51000,18000"
2217"60000,18000"
2218]
2219)
2220start &32
2221sat 1
2222eat 16
2223st 0
2224sf 1
2225si 0
2226tg (WTG
2227uid 195,0
2228ps "ConnStartEndStrategy"
2229stg "STSignalDisplayStrategy"
2230f (Text
2231uid 196,0
2232va (VaSet
2233)
2234xt "52000,17000,53200,18000"
2235st "cs"
2236blo "52000,17800"
2237tm "WireNameMgr"
2238)
2239)
2240on &20
2241)
2242*69 (Wire
2243uid 197,0
2244shape (OrthoPolyLine
2245uid 198,0
2246va (VaSet
2247vasetType 3
2248)
2249xt "51000,17000,60000,17000"
2250pts [
2251"51000,17000"
2252"60000,17000"
2253]
2254)
2255start &32
2256sat 1
2257eat 16
2258st 0
2259sf 1
2260si 0
2261tg (WTG
2262uid 203,0
2263ps "ConnStartEndStrategy"
2264stg "STSignalDisplayStrategy"
2265f (Text
2266uid 204,0
2267va (VaSet
2268)
2269xt "52000,16000,55600,17000"
2270st "wiz_reset"
2271blo "52000,16800"
2272tm "WireNameMgr"
2273)
2274)
2275on &19
2276)
2277*70 (Wire
2278uid 205,0
2279shape (OrthoPolyLine
2280uid 206,0
2281va (VaSet
2282vasetType 3
2283)
2284xt "51000,19000,60000,19000"
2285pts [
2286"51000,19000"
2287"60000,19000"
2288]
2289)
2290start &32
2291sat 1
2292eat 16
2293st 0
2294sf 1
2295si 0
2296tg (WTG
2297uid 211,0
2298ps "ConnStartEndStrategy"
2299stg "STSignalDisplayStrategy"
2300f (Text
2301uid 212,0
2302va (VaSet
2303)
2304xt "52000,18000,53200,19000"
2305st "wr"
2306blo "52000,18800"
2307tm "WireNameMgr"
2308)
2309)
2310on &21
2311)
2312*71 (Wire
2313uid 213,0
2314shape (OrthoPolyLine
2315uid 214,0
2316va (VaSet
2317vasetType 3
2318)
2319xt "51000,20000,60000,20000"
2320pts [
2321"51000,20000"
2322"60000,20000"
2323]
2324)
2325start &32
2326sat 1
2327eat 16
2328st 0
2329sf 1
2330si 0
2331tg (WTG
2332uid 219,0
2333ps "ConnStartEndStrategy"
2334stg "STSignalDisplayStrategy"
2335f (Text
2336uid 220,0
2337va (VaSet
2338)
2339xt "52000,19000,53100,20000"
2340st "rd"
2341blo "52000,19800"
2342tm "WireNameMgr"
2343)
2344)
2345on &22
2346)
2347*72 (Wire
2348uid 221,0
2349shape (OrthoPolyLine
2350uid 222,0
2351va (VaSet
2352vasetType 3
2353lineWidth 2
2354)
2355xt "51000,21000,60000,21000"
2356pts [
2357"51000,21000"
2358"60000,21000"
2359]
2360)
2361start &32
2362sat 4
2363eat 16
2364sty 1
2365st 0
2366sf 1
2367si 0
2368tg (WTG
2369uid 227,0
2370ps "ConnStartEndStrategy"
2371stg "STSignalDisplayStrategy"
2372f (Text
2373uid 228,0
2374va (VaSet
2375)
2376xt "53000,20000,59300,21000"
2377st "wiz_data : (15:0)"
2378blo "53000,20800"
2379tm "WireNameMgr"
2380)
2381)
2382on &23
2383)
2384*73 (Wire
2385uid 229,0
2386shape (OrthoPolyLine
2387uid 230,0
2388va (VaSet
2389vasetType 3
2390lineWidth 2
2391)
2392xt "51000,22000,60000,22000"
2393pts [
2394"51000,22000"
2395"60000,22000"
2396]
2397)
2398start &32
2399sat 1
2400eat 16
2401sty 1
2402st 0
2403sf 1
2404si 0
2405tg (WTG
2406uid 235,0
2407ps "ConnStartEndStrategy"
2408stg "STSignalDisplayStrategy"
2409f (Text
2410uid 236,0
2411va (VaSet
2412)
2413xt "53000,21000,59000,22000"
2414st "wiz_addr : (9:0)"
2415blo "53000,21800"
2416tm "WireNameMgr"
2417)
2418)
2419on &24
2420)
2421*74 (Wire
2422uid 237,0
2423shape (OrthoPolyLine
2424uid 238,0
2425va (VaSet
2426vasetType 3
2427)
2428xt "28000,18000,36000,18000"
2429pts [
2430"28000,18000"
2431"36000,18000"
2432]
2433)
2434end &32
2435sat 16
2436eat 2
2437st 0
2438sf 1
2439si 0
2440tg (WTG
2441uid 243,0
2442ps "ConnStartEndStrategy"
2443stg "STSignalDisplayStrategy"
2444f (Text
2445uid 244,0
2446va (VaSet
2447)
2448xt "29000,17000,30200,18000"
2449st "int"
2450blo "29000,17800"
2451tm "WireNameMgr"
2452)
2453)
2454on &27
2455)
2456*75 (Wire
2457uid 253,0
2458shape (OrthoPolyLine
2459uid 254,0
2460va (VaSet
2461vasetType 3
2462lineWidth 2
2463)
2464xt "51000,23000,60000,23000"
2465pts [
2466"51000,23000"
2467"60000,23000"
2468]
2469)
2470start &32
2471sat 1
2472eat 16
2473sty 1
2474st 0
2475sf 1
2476si 0
2477tg (WTG
2478uid 259,0
2479ps "ConnStartEndStrategy"
2480stg "STSignalDisplayStrategy"
2481f (Text
2482uid 260,0
2483va (VaSet
2484)
2485xt "52000,22000,57600,23000"
2486st "data_o : (15:0)"
2487blo "52000,22800"
2488tm "WireNameMgr"
2489)
2490)
2491on &25
2492)
2493*76 (Wire
2494uid 261,0
2495shape (OrthoPolyLine
2496uid 262,0
2497va (VaSet
2498vasetType 3
2499)
2500xt "28000,19000,36000,19000"
2501pts [
2502"28000,19000"
2503"36000,19000"
2504]
2505)
2506end &32
2507sat 16
2508eat 2
2509st 0
2510sf 1
2511si 0
2512tg (WTG
2513uid 267,0
2514ps "ConnStartEndStrategy"
2515stg "STSignalDisplayStrategy"
2516f (Text
2517uid 268,0
2518va (VaSet
2519)
2520xt "29000,18000,31500,19000"
2521st "read_i"
2522blo "29000,18800"
2523tm "WireNameMgr"
2524)
2525)
2526on &28
2527)
2528*77 (Wire
2529uid 269,0
2530shape (OrthoPolyLine
2531uid 270,0
2532va (VaSet
2533vasetType 3
2534)
2535xt "28000,20000,36000,20000"
2536pts [
2537"28000,20000"
2538"36000,20000"
2539]
2540)
2541end &32
2542sat 16
2543eat 2
2544st 0
2545sf 1
2546si 0
2547tg (WTG
2548uid 275,0
2549ps "ConnStartEndStrategy"
2550stg "STSignalDisplayStrategy"
2551f (Text
2552uid 276,0
2553va (VaSet
2554)
2555xt "29000,19000,31600,20000"
2556st "write_i"
2557blo "29000,19800"
2558tm "WireNameMgr"
2559)
2560)
2561on &29
2562)
2563*78 (Wire
2564uid 277,0
2565shape (OrthoPolyLine
2566uid 278,0
2567va (VaSet
2568vasetType 3
2569lineWidth 2
2570)
2571xt "28000,21000,36000,21000"
2572pts [
2573"28000,21000"
2574"36000,21000"
2575]
2576)
2577end &32
2578sat 16
2579eat 2
2580sty 1
2581st 0
2582sf 1
2583si 0
2584tg (WTG
2585uid 283,0
2586ps "ConnStartEndStrategy"
2587stg "STSignalDisplayStrategy"
2588f (Text
2589uid 284,0
2590va (VaSet
2591)
2592xt "29000,20000,34100,21000"
2593st "addr_i : (9:0)"
2594blo "29000,20800"
2595tm "WireNameMgr"
2596)
2597)
2598on &30
2599)
2600*79 (Wire
2601uid 285,0
2602shape (OrthoPolyLine
2603uid 286,0
2604va (VaSet
2605vasetType 3
2606lineWidth 2
2607)
2608xt "28000,22000,36000,22000"
2609pts [
2610"28000,22000"
2611"36000,22000"
2612]
2613)
2614end &32
2615sat 16
2616eat 2
2617sty 1
2618st 0
2619sf 1
2620si 0
2621tg (WTG
2622uid 291,0
2623ps "ConnStartEndStrategy"
2624stg "STSignalDisplayStrategy"
2625f (Text
2626uid 292,0
2627va (VaSet
2628)
2629xt "30000,21000,35400,22000"
2630st "data_i : (15:0)"
2631blo "30000,21800"
2632tm "WireNameMgr"
2633)
2634)
2635on &31
2636)
2637*80 (Wire
2638uid 742,0
2639shape (OrthoPolyLine
2640uid 743,0
2641va (VaSet
2642vasetType 3
2643)
2644xt "15750,28000,24000,28000"
2645pts [
2646"15750,28000"
2647"24000,28000"
2648]
2649)
2650start &15
2651sat 32
2652eat 16
2653st 0
2654sf 1
2655si 0
2656tg (WTG
2657uid 746,0
2658ps "ConnStartEndStrategy"
2659stg "STSignalDisplayStrategy"
2660f (Text
2661uid 747,0
2662va (VaSet
2663)
2664xt "20000,27000,23000,28000"
2665st "ready_o"
2666blo "20000,27800"
2667tm "WireNameMgr"
2668)
2669)
2670on &54
2671)
2672*81 (Wire
2673uid 748,0
2674shape (OrthoPolyLine
2675uid 749,0
2676va (VaSet
2677vasetType 3
2678)
2679xt "28000,23000,36000,23000"
2680pts [
2681"28000,23000"
2682"36000,23000"
2683]
2684)
2685end &32
2686sat 16
2687eat 1
2688st 0
2689sf 1
2690si 0
2691tg (WTG
2692uid 754,0
2693ps "ConnStartEndStrategy"
2694stg "STSignalDisplayStrategy"
2695f (Text
2696uid 755,0
2697va (VaSet
2698)
2699xt "30000,22000,33000,23000"
2700st "ready_o"
2701blo "30000,22800"
2702tm "WireNameMgr"
2703)
2704)
2705on &54
2706)
2707*82 (Wire
2708uid 1940,0
2709shape (OrthoPolyLine
2710uid 1941,0
2711va (VaSet
2712vasetType 3
2713)
2714xt "28000,24000,36000,24000"
2715pts [
2716"28000,24000"
2717"36000,24000"
2718]
2719)
2720end &32
2721sat 16
2722eat 1
2723st 0
2724sf 1
2725si 0
2726tg (WTG
2727uid 1946,0
2728ps "ConnStartEndStrategy"
2729stg "STSignalDisplayStrategy"
2730f (Text
2731uid 1947,0
2732va (VaSet
2733)
2734xt "30000,23000,31300,24000"
2735st "clk"
2736blo "30000,23800"
2737tm "WireNameMgr"
2738)
2739)
2740on &26
2741)
2742]
2743bg "65535,65535,65535"
2744grid (Grid
2745origin "0,0"
2746isVisible 1
2747isActive 1
2748xSpacing 1000
2749xySpacing 1000
2750xShown 1
2751yShown 1
2752color "26368,26368,26368"
2753)
2754packageList *83 (PackageList
2755uid 351,0
2756stg "VerticalLayoutStrategy"
2757textVec [
2758*84 (Text
2759uid 352,0
2760va (VaSet
2761font "arial,8,1"
2762)
2763xt "0,0,5400,1000"
2764st "Package List"
2765blo "0,800"
2766)
2767*85 (MLText
2768uid 353,0
2769va (VaSet
2770)
2771xt "0,1000,13000,5000"
2772st "LIBRARY IEEE;
2773USE IEEE.STD_LOGIC_1164.ALL;
2774USE IEEE.NUMERIC_STD.ALL;
2775USE ieee.std_logic_unsigned.all;"
2776tm "PackageList"
2777)
2778]
2779)
2780compDirBlock (MlTextGroup
2781uid 354,0
2782stg "VerticalLayoutStrategy"
2783textVec [
2784*86 (Text
2785uid 355,0
2786va (VaSet
2787isHidden 1
2788font "Arial,8,1"
2789)
2790xt "20000,0,28100,1000"
2791st "Compiler Directives"
2792blo "20000,800"
2793)
2794*87 (Text
2795uid 356,0
2796va (VaSet
2797isHidden 1
2798font "Arial,8,1"
2799)
2800xt "20000,1000,29600,2000"
2801st "Pre-module directives:"
2802blo "20000,1800"
2803)
2804*88 (MLText
2805uid 357,0
2806va (VaSet
2807isHidden 1
2808)
2809xt "20000,2000,27500,4000"
2810st "`resetall
2811`timescale 1ns/10ps"
2812tm "BdCompilerDirectivesTextMgr"
2813)
2814*89 (Text
2815uid 358,0
2816va (VaSet
2817isHidden 1
2818font "Arial,8,1"
2819)
2820xt "20000,4000,30100,5000"
2821st "Post-module directives:"
2822blo "20000,4800"
2823)
2824*90 (MLText
2825uid 359,0
2826va (VaSet
2827isHidden 1
2828)
2829xt "20000,0,20000,0"
2830tm "BdCompilerDirectivesTextMgr"
2831)
2832*91 (Text
2833uid 360,0
2834va (VaSet
2835isHidden 1
2836font "Arial,8,1"
2837)
2838xt "20000,5000,29900,6000"
2839st "End-module directives:"
2840blo "20000,5800"
2841)
2842*92 (MLText
2843uid 361,0
2844va (VaSet
2845isHidden 1
2846)
2847xt "20000,6000,20000,6000"
2848tm "BdCompilerDirectivesTextMgr"
2849)
2850]
2851associable 1
2852)
2853windowSize "0,22,1281,1024"
2854viewArea "-29100,-23500,67451,51575"
2855cachedDiagramExtent "-23500,-7000,64000,49000"
2856hasePageBreakOrigin 1
2857pageBreakOrigin "-82000,-49000"
2858lastUid 1947,0
2859defaultCommentText (CommentText
2860shape (Rectangle
2861layer 0
2862va (VaSet
2863vasetType 1
2864fg "65280,65280,46080"
2865lineColor "0,0,32768"
2866)
2867xt "0,0,15000,5000"
2868)
2869text (MLText
2870va (VaSet
2871fg "0,0,32768"
2872)
2873xt "200,200,2000,1200"
2874st "
2875Text
2876"
2877tm "CommentText"
2878wrapOption 3
2879visibleHeight 4600
2880visibleWidth 14600
2881)
2882)
2883defaultPanel (Panel
2884shape (RectFrame
2885va (VaSet
2886vasetType 1
2887fg "65535,65535,65535"
2888lineColor "32768,0,0"
2889lineWidth 3
2890)
2891xt "0,0,20000,20000"
2892)
2893title (TextAssociate
2894ps "TopLeftStrategy"
2895text (Text
2896va (VaSet
2897font "Arial,8,1"
2898)
2899xt "1000,1000,3800,2000"
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3501sat 32
3502eat 32
3503st 0
3504sf 1
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3526"0,0"
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3532sat 32
3533eat 32
3534sty 1
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3566eat 32
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3606second (MLText
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3645)
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3684title (TextAssociate
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3701xt "50,50,1250,1450"
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3744tg (CPTG
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3755thePort (LogicalPort
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3759o 0
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3783thePort (LogicalPort
3784m 3
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3787t ""
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3828preUserText (MLText
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3846postUserLabel (Text
3847uid 7,0
3848va (VaSet
3849isHidden 1
3850font "Arial,8,1"
3851)
3852xt "20000,0,24700,1000"
3853st "Post User:"
3854blo "20000,800"
3855)
3856postUserText (MLText
3857uid 8,0
3858va (VaSet
3859isHidden 1
3860font "Courier New,8,0"
3861)
3862xt "20000,0,20000,0"
3863tm "BdDeclarativeTextMgr"
3864)
3865)
3866commonDM (CommonDM
3867ldm (LogicalDM
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3869usingSuid 1
3870emptyRow *114 (LEmptyRow
3871)
3872uid 364,0
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3875)
3876*116 (TitleRowHdr
3877)
3878*117 (FilterRowHdr
3879)
3880*118 (RefLabelColHdr
3881tm "RefLabelColHdrMgr"
3882)
3883*119 (RowExpandColHdr
3884tm "RowExpandColHdrMgr"
3885)
3886*120 (GroupColHdr
3887tm "GroupColHdrMgr"
3888)
3889*121 (NameColHdr
3890tm "BlockDiagramNameColHdrMgr"
3891)
3892*122 (ModeColHdr
3893tm "BlockDiagramModeColHdrMgr"
3894)
3895*123 (TypeColHdr
3896tm "BlockDiagramTypeColHdrMgr"
3897)
3898*124 (BoundsColHdr
3899tm "BlockDiagramBoundsColHdrMgr"
3900)
3901*125 (InitColHdr
3902tm "BlockDiagramInitColHdrMgr"
3903)
3904*126 (EolColHdr
3905tm "BlockDiagramEolColHdrMgr"
3906)
3907*127 (LeafLogPort
3908port (LogicalPort
3909m 4
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3911n "wiz_reset"
3912t "std_logic"
3913o 1
3914suid 1,0
3915)
3916)
3917uid 325,0
3918)
3919*128 (LeafLogPort
3920port (LogicalPort
3921m 4
3922decl (Decl
3923n "cs"
3924t "std_logic"
3925o 2
3926suid 2,0
3927)
3928)
3929uid 327,0
3930)
3931*129 (LeafLogPort
3932port (LogicalPort
3933m 4
3934decl (Decl
3935n "wr"
3936t "std_logic"
3937o 3
3938suid 3,0
3939)
3940)
3941uid 329,0
3942)
3943*130 (LeafLogPort
3944port (LogicalPort
3945m 4
3946decl (Decl
3947n "rd"
3948t "std_logic"
3949o 4
3950suid 4,0
3951)
3952)
3953uid 331,0
3954)
3955*131 (LeafLogPort
3956port (LogicalPort
3957m 4
3958decl (Decl
3959n "wiz_data"
3960t "std_logic_vector"
3961b "(15 DOWNTO 0)"
3962o 5
3963suid 5,0
3964)
3965)
3966uid 333,0
3967)
3968*132 (LeafLogPort
3969port (LogicalPort
3970m 4
3971decl (Decl
3972n "wiz_addr"
3973t "std_logic_vector"
3974b "(9 DOWNTO 0)"
3975o 6
3976suid 6,0
3977)
3978)
3979uid 335,0
3980)
3981*133 (LeafLogPort
3982port (LogicalPort
3983lang 10
3984m 4
3985decl (Decl
3986n "data_o"
3987t "std_logic_vector"
3988b "(15 DOWNTO 0)"
3989o 7
3990suid 7,0
3991)
3992)
3993uid 337,0
3994)
3995*134 (LeafLogPort
3996port (LogicalPort
3997m 4
3998decl (Decl
3999n "clk"
4000t "std_logic"
4001o 8
4002suid 8,0
4003)
4004)
4005uid 339,0
4006)
4007*135 (LeafLogPort
4008port (LogicalPort
4009m 4
4010decl (Decl
4011n "int"
4012t "std_logic"
4013o 9
4014suid 9,0
4015)
4016)
4017uid 341,0
4018)
4019*136 (LeafLogPort
4020port (LogicalPort
4021m 4
4022decl (Decl
4023n "read_i"
4024t "std_logic"
4025o 10
4026suid 10,0
4027)
4028)
4029uid 343,0
4030)
4031*137 (LeafLogPort
4032port (LogicalPort
4033m 4
4034decl (Decl
4035n "write_i"
4036t "std_logic"
4037o 11
4038suid 11,0
4039)
4040)
4041uid 345,0
4042)
4043*138 (LeafLogPort
4044port (LogicalPort
4045m 4
4046decl (Decl
4047n "addr_i"
4048t "std_logic_vector"
4049b "(9 DOWNTO 0)"
4050o 12
4051suid 12,0
4052)
4053)
4054uid 347,0
4055)
4056*139 (LeafLogPort
4057port (LogicalPort
4058m 4
4059decl (Decl
4060n "data_i"
4061t "std_logic_vector"
4062b "(15 DOWNTO 0)"
4063o 13
4064suid 13,0
4065)
4066)
4067uid 349,0
4068)
4069*140 (LeafLogPort
4070port (LogicalPort
4071lang 10
4072m 4
4073decl (Decl
4074n "ready_o"
4075t "std_logic"
4076o 14
4077suid 14,0
4078)
4079)
4080uid 756,0
4081)
4082]
4083)
4084pdm (PhysicalDM
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4086editShortBounds 1
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4088optionalChildren [
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4093fontColor "0,0,0"
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4095)
4096cellVa (MVa
4097cellColor "65535,65535,65535"
4098fontColor "0,0,0"
4099font "Tahoma,10,0"
4100)
4101groupVa (MVa
4102cellColor "39936,56832,65280"
4103fontColor "0,0,0"
4104font "Tahoma,10,0"
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4107litem &114
4108pos 14
4109dimension 20
4110)
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4117uid 380,0
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4119*144 (MRCItem
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4123uid 381,0
4124)
4125*145 (MRCItem
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4130uid 382,0
4131)
4132*146 (MRCItem
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4136uid 326,0
4137)
4138*147 (MRCItem
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4141dimension 20
4142uid 328,0
4143)
4144*148 (MRCItem
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4147dimension 20
4148uid 330,0
4149)
4150*149 (MRCItem
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4152pos 3
4153dimension 20
4154uid 332,0
4155)
4156*150 (MRCItem
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4158pos 4
4159dimension 20
4160uid 334,0
4161)
4162*151 (MRCItem
4163litem &132
4164pos 5
4165dimension 20
4166uid 336,0
4167)
4168*152 (MRCItem
4169litem &133
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4171dimension 20
4172uid 338,0
4173)
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4175litem &134
4176pos 7
4177dimension 20
4178uid 340,0
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4182pos 8
4183dimension 20
4184uid 342,0
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4187litem &136
4188pos 9
4189dimension 20
4190uid 344,0
4191)
4192*156 (MRCItem
4193litem &137
4194pos 10
4195dimension 20
4196uid 346,0
4197)
4198*157 (MRCItem
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4200pos 11
4201dimension 20
4202uid 348,0
4203)
4204*158 (MRCItem
4205litem &139
4206pos 12
4207dimension 20
4208uid 350,0
4209)
4210*159 (MRCItem
4211litem &140
4212pos 13
4213dimension 20
4214uid 757,0
4215)
4216]
4217)
4218sheetCol (SheetCol
4219propVa (MVa
4220cellColor "0,49152,49152"
4221fontColor "0,0,0"
4222font "Tahoma,10,0"
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4224)
4225uid 383,0
4226optionalChildren [
4227*160 (MRCItem
4228litem &118
4229pos 0
4230dimension 20
4231uid 384,0
4232)
4233*161 (MRCItem
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4235pos 1
4236dimension 50
4237uid 385,0
4238)
4239*162 (MRCItem
4240litem &121
4241pos 2
4242dimension 100
4243uid 386,0
4244)
4245*163 (MRCItem
4246litem &122
4247pos 3
4248dimension 50
4249uid 387,0
4250)
4251*164 (MRCItem
4252litem &123
4253pos 4
4254dimension 100
4255uid 388,0
4256)
4257*165 (MRCItem
4258litem &124
4259pos 5
4260dimension 100
4261uid 389,0
4262)
4263*166 (MRCItem
4264litem &125
4265pos 6
4266dimension 50
4267uid 390,0
4268)
4269*167 (MRCItem
4270litem &126
4271pos 7
4272dimension 80
4273uid 391,0
4274)
4275]
4276)
4277fixedCol 4
4278fixedRow 2
4279name "Ports"
4280uid 378,0
4281vaOverrides [
4282]
4283)
4284]
4285)
4286uid 363,0
4287)
4288genericsCommonDM (CommonDM
4289ldm (LogicalDM
4290emptyRow *168 (LEmptyRow
4291)
4292uid 393,0
4293optionalChildren [
4294*169 (RefLabelRowHdr
4295)
4296*170 (TitleRowHdr
4297)
4298*171 (FilterRowHdr
4299)
4300*172 (RefLabelColHdr
4301tm "RefLabelColHdrMgr"
4302)
4303*173 (RowExpandColHdr
4304tm "RowExpandColHdrMgr"
4305)
4306*174 (GroupColHdr
4307tm "GroupColHdrMgr"
4308)
4309*175 (NameColHdr
4310tm "GenericNameColHdrMgr"
4311)
4312*176 (TypeColHdr
4313tm "GenericTypeColHdrMgr"
4314)
4315*177 (InitColHdr
4316tm "GenericValueColHdrMgr"
4317)
4318*178 (PragmaColHdr
4319tm "GenericPragmaColHdrMgr"
4320)
4321*179 (EolColHdr
4322tm "GenericEolColHdrMgr"
4323)
4324*180 (LogGeneric
4325generic (GiElement
4326name "TIME_UNTIL_READ_READY"
4327type "integer"
4328value "4"
4329)
4330uid 9,0
4331)
4332*181 (LogGeneric
4333generic (GiElement
4334name "TIME_UNTIL_READ_READY"
4335type "integer"
4336value "4"
4337)
4338uid 11,0
4339)
4340]
4341)
4342pdm (PhysicalDM
4343displayShortBounds 1
4344editShortBounds 1
4345uid 405,0
4346optionalChildren [
4347*182 (Sheet
4348sheetRow (SheetRow
4349headerVa (MVa
4350cellColor "49152,49152,49152"
4351fontColor "0,0,0"
4352font "Tahoma,10,0"
4353)
4354cellVa (MVa
4355cellColor "65535,65535,65535"
4356fontColor "0,0,0"
4357font "Tahoma,10,0"
4358)
4359groupVa (MVa
4360cellColor "39936,56832,65280"
4361fontColor "0,0,0"
4362font "Tahoma,10,0"
4363)
4364emptyMRCItem *183 (MRCItem
4365litem &168
4366pos 2
4367dimension 20
4368)
4369uid 407,0
4370optionalChildren [
4371*184 (MRCItem
4372litem &169
4373pos 0
4374dimension 20
4375uid 408,0
4376)
4377*185 (MRCItem
4378litem &170
4379pos 1
4380dimension 23
4381uid 409,0
4382)
4383*186 (MRCItem
4384litem &171
4385pos 2
4386hidden 1
4387dimension 20
4388uid 410,0
4389)
4390*187 (MRCItem
4391litem &180
4392pos 0
4393dimension 20
4394uid 10,0
4395)
4396*188 (MRCItem
4397litem &181
4398pos 1
4399dimension 20
4400uid 12,0
4401)
4402]
4403)
4404sheetCol (SheetCol
4405propVa (MVa
4406cellColor "0,49152,49152"
4407fontColor "0,0,0"
4408font "Tahoma,10,0"
4409textAngle 90
4410)
4411uid 411,0
4412optionalChildren [
4413*189 (MRCItem
4414litem &172
4415pos 0
4416dimension 20
4417uid 412,0
4418)
4419*190 (MRCItem
4420litem &174
4421pos 1
4422dimension 50
4423uid 413,0
4424)
4425*191 (MRCItem
4426litem &175
4427pos 2
4428dimension 100
4429uid 414,0
4430)
4431*192 (MRCItem
4432litem &176
4433pos 3
4434dimension 100
4435uid 415,0
4436)
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4438litem &177
4439pos 4
4440dimension 50
4441uid 416,0
4442)
4443*194 (MRCItem
4444litem &178
4445pos 5
4446dimension 50
4447uid 417,0
4448)
4449*195 (MRCItem
4450litem &179
4451pos 6
4452dimension 80
4453uid 418,0
4454)
4455]
4456)
4457fixedCol 3
4458fixedRow 2
4459name "Ports"
4460uid 406,0
4461vaOverrides [
4462]
4463)
4464]
4465)
4466uid 392,0
4467type 1
4468)
4469activeModelName "BlockDiag"
4470)
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