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VExpander (VariableExpander
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(vvPair
variable "HDLDir"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hdl"
)
(vvPair
variable "HDSDir"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_interface_tester\\interface.info"
)
(vvPair
variable "SideDataUserDir"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_interface_tester\\interface.user"
)
(vvPair
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value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "interface"
)
(vvPair
variable "config"
value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_interface_tester"
)
(vvPair
variable "d_logical"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_interface_tester"
)
(vvPair
variable "date"
value "31.05.2011"
)
(vvPair
variable "day"
value "Di"
)
(vvPair
variable "day_long"
value "Dienstag"
)
(vvPair
variable "dd"
value "31"
)
(vvPair
variable "entity_name"
value "w5300_interface_tester"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "interface"
)
(vvPair
variable "f_logical"
value "interface"
)
(vvPair
variable "f_noext"
value "interface"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "E5B-LABOR6"
)
(vvPair
variable "language"
value "VHDL"
)
(vvPair
variable "library"
value "FACT_FAD_TB_lib"
)
(vvPair
variable "library_downstream_HdsLintPlugin"
value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/designcheck"
)
(vvPair
variable "library_downstream_ISEPARInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
)
(vvPair
variable "library_downstream_ImpactInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/work"
)
(vvPair
variable "library_downstream_XSTDataPrep"
value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
)
(vvPair
variable "mm"
value "05"
)
(vvPair
variable "module_name"
value "w5300_interface_tester"
)
(vvPair
variable "month"
value "Mai"
)
(vvPair
variable "month_long"
value "Mai"
)
(vvPair
variable "p"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_interface_tester\\interface"
)
(vvPair
variable "p_logical"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_interface_tester\\interface"
)
(vvPair
variable "package_name"
value "<Undefined Variable>"
)
(vvPair
variable "project_name"
value "FACT_FAD"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "C:\\modeltech_6.6a\\win32"
)
(vvPair
variable "task_NC-SimPath"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
)
(vvPair
variable "task_QuestaSimPath"
value "<TBD>"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "this_ext"
value "<TBD>"
)
(vvPair
variable "this_file"
value "interface"
)
(vvPair
variable "this_file_logical"
value "interface"
)
(vvPair
variable "time"
value "13:38:06"
)
(vvPair
variable "unit"
value "w5300_interface_tester"
)
(vvPair
variable "user"
value "dneise"
)
(vvPair
variable "version"
value "2009.2 (Build 10)"
)
(vvPair
variable "view"
value "interface"
)
(vvPair
variable "year"
value "2011"
)
(vvPair
variable "yy"
value "11"
)
]
)
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tm "CptPortNameMgr"
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ro 270
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va (VaSet
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st "int"
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)
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va (VaSet
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ro 270
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xt "30000,9625,30750,10375"
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stg "RightVerticalLayoutStrategy"
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uid 3310,0
va (VaSet
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xt "27900,9500,29000,10500"
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blo "29000,10300"
tm "CptPortNameMgr"
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)
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va (VaSet
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)
)
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decl (Decl
n "rd"
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ps "OnEdgeStrategy"
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ro 270
va (VaSet
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xt "14250,8625,15000,9375"
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stg "VerticalLayoutStrategy"
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va (VaSet
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xt "16000,8500,18500,9500"
st "read_i"
blo "16000,9300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 3316,0
va (VaSet
font "Courier New,8,0"
)
)
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m 1
decl (Decl
n "read_i"
t "std_logic"
o 12
suid 372,0
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ps "OnEdgeStrategy"
shape (Triangle
uid 3318,0
ro 90
va (VaSet
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fg "0,65535,0"
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xt "14250,12625,15000,13375"
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tg (CPTG
uid 3319,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
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uid 3320,0
va (VaSet
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xt "16000,12500,19000,13500"
st "ready_o"
blo "16000,13300"
tm "CptPortNameMgr"
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dt (MLText
uid 3321,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "ready_o"
t "std_logic"
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suid 373,0
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ps "OnEdgeStrategy"
shape (Triangle
uid 3323,0
ro 270
va (VaSet
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fg "0,65535,0"
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xt "30000,11625,30750,12375"
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tg (CPTG
uid 3324,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3325,0
va (VaSet
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xt "25600,11500,29000,12500"
st "wiz_addr"
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