source: firmware/FAD/FACT_FAD_TB_lib/hds/w5300_modul2_tester/interface

DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
dmPackageRefs [
(DmPackageRef
library "IEEE"
unitName "STD_LOGIC_1164"
itemName "ALL"
)
(DmPackageRef
library "IEEE"
unitName "STD_LOGIC_ARITH"
itemName "ALL"
)
(DmPackageRef
library "IEEE"
unitName "STD_LOGIC_UNSIGNED"
itemName "ALL"
)
(DmPackageRef
library "FACT_FAD_lib"
unitName "fad_definitions"
itemName "ALL"
)
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"FACT_FAD_lib"
]
)
version "24.1"
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(vvPair
variable "HDLDir"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hdl"
)
(vvPair
variable "HDSDir"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_modul2_tester\\interface.info"
)
(vvPair
variable "SideDataUserDir"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_modul2_tester\\interface.user"
)
(vvPair
variable "SourceDir"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "interface"
)
(vvPair
variable "config"
value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_modul2_tester"
)
(vvPair
variable "d_logical"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_modul2_tester"
)
(vvPair
variable "date"
value "01.06.2011"
)
(vvPair
variable "day"
value "Mi"
)
(vvPair
variable "day_long"
value "Mittwoch"
)
(vvPair
variable "dd"
value "01"
)
(vvPair
variable "entity_name"
value "w5300_modul2_tester"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "interface"
)
(vvPair
variable "f_logical"
value "interface"
)
(vvPair
variable "f_noext"
value "interface"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "E5B-LABOR6"
)
(vvPair
variable "language"
value "VHDL"
)
(vvPair
variable "library"
value "FACT_FAD_TB_lib"
)
(vvPair
variable "library_downstream_HdsLintPlugin"
value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/designcheck"
)
(vvPair
variable "library_downstream_ISEPARInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
)
(vvPair
variable "library_downstream_ImpactInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/work"
)
(vvPair
variable "library_downstream_XSTDataPrep"
value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
)
(vvPair
variable "mm"
value "06"
)
(vvPair
variable "module_name"
value "w5300_modul2_tester"
)
(vvPair
variable "month"
value "Jun"
)
(vvPair
variable "month_long"
value "Juni"
)
(vvPair
variable "p"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_modul2_tester\\interface"
)
(vvPair
variable "p_logical"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_modul2_tester\\interface"
)
(vvPair
variable "package_name"
value "<Undefined Variable>"
)
(vvPair
variable "project_name"
value "FACT_FAD"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "C:\\modeltech_6.6a\\win32"
)
(vvPair
variable "task_NC-SimPath"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
)
(vvPair
variable "task_QuestaSimPath"
value "<TBD>"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "this_ext"
value "<TBD>"
)
(vvPair
variable "this_file"
value "interface"
)
(vvPair
variable "this_file_logical"
value "interface"
)
(vvPair
variable "time"
value "09:26:48"
)
(vvPair
variable "unit"
value "w5300_modul2_tester"
)
(vvPair
variable "user"
value "dneise"
)
(vvPair
variable "version"
value "2009.2 (Build 10)"
)
(vvPair
variable "view"
value "interface"
)
(vvPair
variable "year"
value "2011"
)
(vvPair
variable "yy"
value "11"
)
]
)
LanguageMgr "VhdlLangMgr"
uid 401,0
optionalChildren [
*135 (SymbolBody
uid 8,0
optionalChildren [
*136 (CptPort
uid 2304,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2305,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,20625,15000,21375"
)
tg (CPTG
uid 2306,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2307,0
va (VaSet
)
xt "16000,20500,19200,21500"
st "BoardID"
blo "16000,21300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2308,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
m 1
decl (Decl
n "BoardID"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 28
suid 295,0
)
)
)
*137 (CptPort
uid 2309,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2310,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,19625,49750,20375"
)
tg (CPTG
uid 2311,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2312,0
va (VaSet
)
xt "46100,19500,48000,20500"
st "busy"
ju 2
blo "48000,20300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2313,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "busy"
t "std_logic"
o 2
suid 296,0
)
)
)
*138 (CptPort
uid 2314,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2315,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,21625,49750,22375"
)
tg (CPTG
uid 2316,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2317,0
va (VaSet
)
xt "41400,21500,48000,22500"
st "c_trigger_enable"
ju 2
blo "48000,22300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2318,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "c_trigger_enable"
t "std_logic"
o 3
suid 297,0
)
)
)
*139 (CptPort
uid 2319,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2320,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,22625,49750,23375"
)
tg (CPTG
uid 2321,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2322,0
va (VaSet
)
xt "42200,22500,48000,23500"
st "c_trigger_mult"
ju 2
blo "48000,23300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2323,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "c_trigger_mult"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 4
suid 298,0
)
)
)
*140 (CptPort
uid 2324,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2325,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,7625,15000,8375"
)
tg (CPTG
uid 2326,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2327,0
va (VaSet
)
xt "16000,7500,17300,8500"
st "clk"
blo "16000,8300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2328,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
decl (Decl
n "clk"
t "std_logic"
o 1
suid 299,0
)
)
)
*141 (CptPort
uid 2329,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2330,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,21625,15000,22375"
)
tg (CPTG
uid 2331,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2332,0
va (VaSet
)
xt "16000,21500,19100,22500"
st "CrateID"
blo "16000,22300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2333,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
m 1
decl (Decl
n "CrateID"
t "std_logic_vector"
b "(1 DOWNTO 0)"
o 29
suid 300,0
)
)
)
*142 (CptPort
uid 2334,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2335,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,25625,49750,26375"
)
tg (CPTG
uid 2336,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2337,0
va (VaSet
)
xt "43300,25500,48000,26500"
st "dac_setting"
ju 2
blo "48000,26300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2338,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "dac_setting"
t "dac_array_type"
o 5
suid 301,0
)
)
)
*143 (CptPort
uid 2339,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2340,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,6625,15000,7375"
)
tg (CPTG
uid 2341,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2342,0
va (VaSet
)
xt "16000,6500,24500,7500"
st "data_generator_idle_i"
blo "16000,7300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2343,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "data_generator_idle_i"
t "std_logic"
o 31
suid 302,0
)
)
)
*144 (CptPort
uid 2344,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2345,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,18625,15000,19375"
)
tg (CPTG
uid 2346,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2347,0
va (VaSet
)
xt "16000,18500,22200,19500"
st "data_ram_empty"
blo "16000,19300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2348,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "data_ram_empty"
t "std_logic"
o 32
suid 303,0
)
)
)
*145 (CptPort
uid 2349,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2350,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,12625,15000,13375"
)
tg (CPTG
uid 2351,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2352,0
va (VaSet
)
xt "16000,12500,20100,13500"
st "data_valid"
blo "16000,13300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2353,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "data_valid"
t "std_logic"
o 33
suid 304,0
)
)
)
*146 (CptPort
uid 2354,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2355,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,18625,49750,19375"
)
tg (CPTG
uid 2356,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2357,0
va (VaSet
)
xt "42400,18500,48000,19500"
st "data_valid_ack"
ju 2
blo "48000,19300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2358,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "data_valid_ack"
t "std_logic"
o 6
suid 305,0
)
)
)
*147 (CptPort
uid 2359,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2360,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,7625,49750,8375"
)
tg (CPTG
uid 2361,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2362,0
va (VaSet
)
xt "38900,7500,48000,8500"
st "debug_data_ram_empty"
ju 2
blo "48000,8300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2363,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
decl (Decl
n "debug_data_ram_empty"
t "std_logic"
o 7
suid 306,0
)
)
)
*148 (CptPort
uid 2364,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2365,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,8625,49750,9375"
)
tg (CPTG
uid 2366,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2367,0
va (VaSet
)
xt "41400,8500,48000,9500"
st "debug_data_valid"
ju 2
blo "48000,9300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2368,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
decl (Decl
n "debug_data_valid"
t "std_logic"
o 8
suid 307,0
)
)
)
*149 (CptPort
uid 2369,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2370,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,30625,49750,31375"
)
tg (CPTG
uid 2371,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2372,0
va (VaSet
)
xt "45000,30500,48000,31500"
st "denable"
ju 2
blo "48000,31300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2373,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "denable"
t "std_logic"
o 9
suid 308,0
)
)
)
*150 (CptPort
uid 2374,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2375,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,31625,49750,32375"
)
tg (CPTG
uid 2376,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2377,0
va (VaSet
)
xt "42600,31500,48000,32500"
st "dwrite_enable"
ju 2
blo "48000,32300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2378,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "dwrite_enable"
t "std_logic"
o 10
suid 309,0
)
)
)
*151 (CptPort
uid 2379,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2380,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,15625,15000,16375"
)
tg (CPTG
uid 2381,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2382,0
va (VaSet
)
xt "16000,15500,21200,16500"
st "fifo_channels"
blo "16000,16300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2383,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
m 1
decl (Decl
n "fifo_channels"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 34
suid 310,0
)
)
)
*152 (CptPort
uid 2384,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2385,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,19625,15000,20375"
)
tg (CPTG
uid 2386,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2387,0
va (VaSet
)
xt "16000,19500,21300,20500"
st "MAC_jumper"
blo "16000,20300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2388,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
m 1
decl (Decl
n "MAC_jumper"
t "std_logic_vector"
b "(1 DOWNTO 0)"
o 30
suid 311,0
)
)
)
*153 (CptPort
uid 2389,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2390,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,23625,49750,24375"
)
tg (CPTG
uid 2391,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2392,0
va (VaSet
)
xt "35600,23500,48000,24500"
st "memory_manager_config_start_o"
ju 2
blo "48000,24300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2393,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "memory_manager_config_start_o"
t "std_logic"
o 11
suid 312,0
)
)
)
*154 (CptPort
uid 2394,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2395,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,16625,15000,17375"
)
tg (CPTG
uid 2396,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2397,0
va (VaSet
)
xt "16000,16500,28200,17500"
st "memory_manager_config_valid_i"
blo "16000,17300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2398,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "memory_manager_config_valid_i"
t "std_logic"
o 35
suid 313,0
)
)
)
*155 (CptPort
uid 2399,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2400,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,34625,49750,35375"
)
tg (CPTG
uid 2401,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2402,0
va (VaSet
)
xt "43100,34500,48000,35500"
st "ps_direction"
ju 2
blo "48000,35300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2403,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "ps_direction"
t "std_logic"
o 12
suid 314,0
)
)
)
*156 (CptPort
uid 2404,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2405,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,35625,49750,36375"
)
tg (CPTG
uid 2406,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2407,0
va (VaSet
)
xt "41000,35500,48000,36500"
st "ps_do_phase_shift"
ju 2
blo "48000,36300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2408,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "ps_do_phase_shift"
t "std_logic"
o 13
suid 315,0
)
)
)
*157 (CptPort
uid 2409,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2410,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,22625,15000,23375"
)
tg (CPTG
uid 2411,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2412,0
va (VaSet
)
xt "16000,22500,19400,23500"
st "ps_ready"
blo "16000,23300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2413,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ps_ready"
t "std_logic"
o 36
suid 316,0
)
)
)
*158 (CptPort
uid 2414,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2415,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,36625,49750,37375"
)
tg (CPTG
uid 2416,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2417,0
va (VaSet
)
xt "44700,36500,48000,37500"
st "ps_reset"
ju 2
blo "48000,37300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2418,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "ps_reset"
t "std_logic"
o 14
suid 317,0
)
)
)
*159 (CptPort
uid 2419,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2420,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,17625,49750,18375"
)
tg (CPTG
uid 2421,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2422,0
va (VaSet
)
xt "44400,17500,48000,18500"
st "ram_addr"
ju 2
blo "48000,18300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2423,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "ram_addr"
t "std_logic_vector"
b "(13 DOWNTO 0)"
o 15
suid 318,0
)
)
)
*160 (CptPort
uid 2424,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2425,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,11625,15000,12375"
)
tg (CPTG
uid 2426,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2427,0
va (VaSet
)
xt "16000,11500,19500,12500"
st "ram_data"
blo "16000,12300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2428,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ram_data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 37
suid 319,0
)
)
)
*161 (CptPort
uid 2429,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2430,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,10625,15000,11375"
)
tg (CPTG
uid 2431,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2432,0
va (VaSet
)
xt "16000,10500,21900,11500"
st "ram_start_addr"
blo "16000,11300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2433,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
m 1
decl (Decl
n "ram_start_addr"
t "std_logic_vector"
b "(13 DOWNTO 0)"
o 38
suid 320,0
)
)
)
*162 (CptPort
uid 2434,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2435,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,28625,49750,29375"
)
tg (CPTG
uid 2436,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2437,0
va (VaSet
)
xt "41700,28500,48000,29500"
st "reset_trigger_id"
ju 2
blo "48000,29300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2438,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "reset_trigger_id"
t "std_logic"
o 16
suid 321,0
)
)
)
*163 (CptPort
uid 2439,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2440,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,26625,49750,27375"
)
tg (CPTG
uid 2441,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2442,0
va (VaSet
)
xt "43600,26500,48000,27500"
st "roi_setting"
ju 2
blo "48000,27300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2443,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "roi_setting"
t "roi_array_type"
o 17
suid 322,0
)
)
)
*164 (CptPort
uid 2444,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2445,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,27625,49750,28375"
)
tg (CPTG
uid 2446,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2447,0
va (VaSet
)
xt "44000,27500,48000,28500"
st "runnumber"
ju 2
blo "48000,28300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2448,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "runnumber"
t "std_logic_vector"
b "(31 DOWNTO 0)"
o 18
suid 323,0
)
)
)
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uid 2449,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2450,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,20625,49750,21375"
)
tg (CPTG
uid 2451,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2452,0
va (VaSet
)
xt "44400,20500,48000,21500"
st "s_trigger"
ju 2
blo "48000,21300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2453,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "s_trigger"
t "std_logic"
o 19
suid 324,0
)
)
)
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uid 2454,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2455,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "49000,32625,49750,33375"
)
tg (CPTG
uid 2456,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2457,0
va (VaSet
)
xt "43300,32500,48000,33500"
st "sclk_enable"
ju 2
blo "48000,33300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2458,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "sclk_enable"
t "std_logic"
o 20
suid 325,0
)
)
)
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uid 2459,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2460,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "49000,38625,49750,39375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2462,0
va (VaSet
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xt "41500,38500,48000,39500"
st "socks_connected"
ju 2
blo "48000,39300"
tm "CptPortNameMgr"
)
)
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uid 2463,0
va (VaSet
font "Courier New,8,0"
)
)
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decl (Decl
n "socks_connected"
t "std_logic"
o 21
suid 326,0
)
)
)
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uid 2464,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2465,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,37625,49750,38375"
)
tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
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va (VaSet
)
xt "42500,37500,48000,38500"
st "socks_waiting"
ju 2
blo "48000,38300"
tm "CptPortNameMgr"
)
)
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uid 2468,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
decl (Decl
n "socks_waiting"
t "std_logic"
o 22
suid 327,0
)
)
)
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uid 2469,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2470,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,24625,49750,25375"
)
tg (CPTG
uid 2471,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2472,0
va (VaSet
)
xt "37300,24500,48000,25500"
st "spi_interface_config_start_o"
ju 2
blo "48000,25300"
tm "CptPortNameMgr"
)
)
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uid 2473,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "spi_interface_config_start_o"
t "std_logic"
o 23
suid 328,0
)
)
)
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uid 2474,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2475,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "14250,17625,15000,18375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
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va (VaSet
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xt "16000,17500,26500,18500"
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blo "16000,18300"
tm "CptPortNameMgr"
)
)
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uid 2478,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "spi_interface_config_valid_i"
t "std_logic"
o 39
suid 329,0
)
)
)
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uid 2479,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2480,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "49000,33625,49750,34375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
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va (VaSet
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xt "43000,33500,48000,34500"
st "srclk_enable"
ju 2
blo "48000,34300"
tm "CptPortNameMgr"
)
)
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uid 2483,0
va (VaSet
font "Courier New,8,0"
)
)
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lang 10
decl (Decl
n "srclk_enable"
t "std_logic"
o 24
suid 330,0
)
)
)
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uid 2484,0
ps "OnEdgeStrategy"
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uid 2485,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "49000,6625,49750,7375"
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2487,0
va (VaSet
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xt "46000,6500,48000,7500"
st "state"
ju 2
blo "48000,7300"
tm "CptPortNameMgr"
)
)
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va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
decl (Decl
n "state"
t "std_logic_vector"
b "(7 DOWNTO 0)"
o 25
suid 331,0
)
)
)
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uid 2489,0
ps "OnEdgeStrategy"
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uid 2490,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "49000,29625,49750,30375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2492,0
va (VaSet
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xt "42200,29500,48000,30500"
st "trigger_enable"
ju 2
blo "48000,30300"
tm "CptPortNameMgr"
)
)
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uid 2493,0
va (VaSet
font "Courier New,8,0"
)
)
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t "std_logic"
o 26
suid 332,0
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)
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uid 2494,0
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ro 270
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xt "49000,10625,49750,11375"
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uid 2496,0
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stg "RightVerticalLayoutStrategy"
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uid 2497,0
va (VaSet
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xt "44400,10500,48000,11500"
st "wiz_reset"
ju 2
blo "48000,11300"
tm "CptPortNameMgr"
)
)
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uid 2498,0
va (VaSet
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lang 10
decl (Decl
n "wiz_reset"
t "std_logic"
o 27
suid 333,0
)
)
)
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uid 2499,0
ps "OnEdgeStrategy"
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uid 2500,0
ro 270
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fg "0,65535,0"
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xt "14250,14625,15000,15375"
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tg (CPTG
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blo "16000,15300"
tm "CptPortNameMgr"
)
)
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va (VaSet
font "Courier New,8,0"
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m 1
decl (Decl
n "write_end_flag"
t "std_logic"
o 40
suid 334,0
)
)
)
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uid 2504,0
ps "OnEdgeStrategy"
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uid 2505,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "14250,13625,15000,14375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
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uid 2507,0
va (VaSet
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xt "16000,13500,22800,14500"
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blo "16000,14300"
tm "CptPortNameMgr"
)
)
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va (VaSet
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m 1
decl (Decl
n "write_header_flag"
t "std_logic"
o 41
suid 335,0
)
)
)
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uid 2509,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2510,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "14250,9625,15000,10375"
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tg (CPTG
uid 2511,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
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uid 2512,0
va (VaSet
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blo "16000,10300"
tm "CptPortNameMgr"
)
)
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uid 2513,0
va (VaSet
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)
thePort (LogicalPort
m 1
decl (Decl
n "write_length"
t "std_logic_vector"
b "(16 DOWNTO 0)"
o 42
suid 336,0
)
)
)
]
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uid 9,0
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lineColor "0,32896,0"
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xt "15000,6000,49000,40000"
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biTextGroup (BiTextGroup
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ps "CenterOffsetStrategy"
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va (VaSet
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uid 14,0
text (MLText
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tm "CommentText"
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va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
decl (Decl
n "In0"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 0
)
)
)
defaultCptPortBuffer (CptPort
ps "OnEdgeStrategy"
shape (Diamond
va (VaSet
vasetType 1
fg "65535,65535,65535"
bg "0,0,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,2800,1750"
st "Buffer0"
blo "0,1550"
tm "CptPortNameMgr"
)
)
dt (MLText
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
m 3
decl (Decl
n "Buffer0"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 0
)
)
)
DeclarativeBlock *194 (SymDeclBlock
uid 1,0
stg "SymDeclLayoutStrategy"
declLabel (Text
uid 2,0
va (VaSet
font "Arial,8,1"
)
xt "42000,0,47400,1000"
st "Declarations"
blo "42000,800"
)
portLabel (Text
uid 3,0
va (VaSet
font "Arial,8,1"
)
xt "42000,1000,44700,2000"
st "Ports:"
blo "42000,1800"
)
externalLabel (Text
uid 4,0
va (VaSet
font "Arial,8,1"
)
xt "42000,42000,44400,43000"
st "User:"
blo "42000,42800"
)
internalLabel (Text
uid 6,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "42000,0,47800,1000"
st "Internal User:"
blo "42000,800"
)
externalText (MLText
uid 5,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,43000,44000,43000"
tm "SyDeclarativeTextMgr"
)
internalText (MLText
uid 7,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "42000,0,42000,0"
tm "SyDeclarativeTextMgr"
)
)
lastUid 2597,0
activeModelName "Symbol:CDM"
)