source: firmware/FAD/FACT_FAD_lib/hdl/adc_buffer_beha.vhd@ 14342

Last change on this file since 14342 was 11755, checked in by neise, 13 years ago
reinit of this svn repos .... it was all too messy deleted the old folders and restarted with FACT_FAD_lib only. (well and the testbenches)
File size: 1.1 KB
Line 
1--
2-- VHDL Architecture FACT_FAD_lib.adc_buffer.beha
3--
4-- Created:
5-- by - kai.UNKNOWN (E5PCXX)
6-- at - 14:57:55 04.05.2010
7--
8-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12)
9--
10library ieee;
11use ieee.std_logic_1164.all;
12use IEEE.STD_LOGIC_ARITH.all;
13use ieee.STD_LOGIC_UNSIGNED.all;
14
15library fact_fad_lib;
16use fact_fad_lib.fad_definitions.all;
17
18library UNISIM;
19use UNISIM.VComponents.all;
20USE IEEE.NUMERIC_STD.all;
21USE IEEE.std_logic_signed.all;
22
23ENTITY adc_buffer IS
24 PORT(
25 clk_ps : IN std_logic;
26 adc_data_array : IN adc_data_array_type;
27 adc_otr_array : IN std_logic_vector (3 DOWNTO 0);
28 adc_data_array_int : OUT adc_data_array_type;
29 adc_otr : OUT std_logic_vector (3 DOWNTO 0)
30 );
31
32-- Declarations
33
34END adc_buffer ;
35
36--
37ARCHITECTURE beha OF adc_buffer IS
38BEGIN
39 adc_buf : process (clk_ps)
40 begin
41 if rising_edge (clk_ps) then
42 adc_data_array_int <= adc_data_array;
43 adc_otr <= adc_otr_array;
44 end if;
45 end process adc_buf;
46END ARCHITECTURE beha;
47
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