source: firmware/FAD/FACT_FAD_lib/hdl/clk_divider.vhd@ 12105

Last change on this file since 12105 was 11755, checked in by neise, 13 years ago
reinit of this svn repos .... it was all too messy deleted the old folders and restarted with FACT_FAD_lib only. (well and the testbenches)
File size: 725 bytes
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1
2LIBRARY ieee;
3USE ieee.std_logic_1164.all;
4USE ieee.std_logic_arith.all;
5USE ieee.std_logic_unsigned.all;
6
7ENTITY clk_divider IS
8 GENERIC(
9 DIVIDER : integer := 25
10 );
11 PORT(
12 clk : IN std_logic;
13 sclk : OUT std_logic := '0'
14 );
15END clk_divider ;
16
17ARCHITECTURE beha OF clk_divider IS
18
19BEGIN
20
21 clk_proc: process (clk)
22 variable Z: integer range 0 to DIVIDER - 1;
23 begin
24 if rising_edge(clk) then
25 if (Z < DIVIDER - 1) then
26 Z := Z + 1;
27 else
28 Z := 0;
29 end if;
30 if (Z = 0) then
31 sclk <= '1';
32 end if;
33 if (Z = DIVIDER / 2) then
34 sclk <= '0';
35 end if;
36 end if;
37 end process clk_proc;
38
39END ARCHITECTURE beha;
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