1 | -- VHDL Entity FACT_FAD_lib.clock_generator_var_ps.symbol
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2 | --
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3 | -- Created:
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4 | -- by - dneise.UNKNOWN (E5B-LABOR6)
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5 | -- at - 14:45:32 02.08.2011
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6 | --
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7 | -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
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8 | --
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9 | LIBRARY ieee;
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10 | USE ieee.std_logic_1164.all;
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11 | USE ieee.std_logic_arith.all;
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12 |
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13 | ENTITY clock_generator_var_ps IS
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14 | PORT(
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15 | CLK : IN std_logic;
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16 | RST_IN : IN std_logic;
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17 | direction : IN std_logic;
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18 | do_shift : IN std_logic;
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19 | CLK_25 : OUT std_logic;
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20 | CLK_25_PS : OUT std_logic;
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21 | CLK_50 : OUT std_logic;
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22 | locked_status_o : OUT std_logic;
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23 | offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
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24 | ready_status_o : OUT std_logic
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25 | );
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26 |
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27 | -- Declarations
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28 |
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29 | END clock_generator_var_ps ;
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30 |
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31 | --
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32 | -- VHDL Architecture FACT_FAD_lib.clock_generator_var_ps.struct
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33 | --
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34 | -- Created:
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35 | -- by - dneise.UNKNOWN (E5B-LABOR6)
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36 | -- at - 14:45:32 02.08.2011
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37 | --
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38 | -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
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39 | --
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40 | LIBRARY ieee;
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41 | USE ieee.std_logic_1164.all;
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42 | USE ieee.std_logic_arith.all;
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43 | USE ieee.numeric_std.all;
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44 | LIBRARY UNISIM;
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45 | --USE UNISIM.Vcomponents.all;
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46 | LIBRARY FACT_FAD_lib;
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47 | USE FACT_FAD_lib.fad_definitions.all;
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48 |
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49 | LIBRARY FACT_FAD_lib;
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50 |
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51 | ARCHITECTURE struct OF clock_generator_var_ps IS
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52 |
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53 | -- Architecture declarations
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54 |
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55 | -- Internal signal declarations
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56 | SIGNAL CLK0_OUT : std_logic;
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57 | SIGNAL LOCKED_OUT : std_logic;
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58 | SIGNAL PSCLK_IN : std_logic;
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59 | SIGNAL PSDONE_OUT : std_logic;
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60 | SIGNAL PSEN_IN : std_logic;
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61 | SIGNAL PSINCDEC_IN : std_logic;
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62 | SIGNAL rst : std_logic := '0'; --asynch in of DCM
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63 |
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64 | -- Implicit buffer signal declarations
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65 | SIGNAL CLK_25_internal : std_logic;
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66 |
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67 |
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68 | -- Component Declarations
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69 | COMPONENT dcm_50_to_25
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70 | PORT (
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71 | CLKIN_IN : IN std_logic;
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72 | CLK0_OUT : OUT std_logic;
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73 | CLKFX_OUT : OUT std_logic;
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74 | CLKIN_IBUFG_OUT : OUT std_logic
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75 | );
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76 | END COMPONENT;
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77 | COMPONENT dcm_ps_38ns
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78 | PORT (
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79 | CLKIN_IN : IN std_logic;
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80 | CLK0_OUT : OUT std_logic
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81 | );
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82 | END COMPONENT;
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83 | COMPONENT dcm_var_ps_38ns
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84 | PORT (
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85 | CLKIN_IN : IN std_logic;
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86 | PSCLK_IN : IN std_logic;
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87 | PSEN_IN : IN std_logic;
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88 | PSINCDEC_IN : IN std_logic;
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89 | RST_IN : IN std_logic;
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90 | CLK0_OUT : OUT std_logic;
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91 | LOCKED_OUT : OUT std_logic;
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92 | PSDONE_OUT : OUT std_logic
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93 | );
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94 | END COMPONENT;
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95 | COMPONENT phase_shifter
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96 | PORT (
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97 | CLK : IN std_logic ;
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98 | rst : OUT std_logic := '0'; --asynch in of DCM
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99 | -- interface to: clock_generator_variable_PS_struct.vhd
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100 | PSCLK : OUT std_logic ;
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101 | PSEN : OUT std_logic := '0';
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102 | PSINCDEC : OUT std_logic := '1'; -- default is 'incrementing'
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103 | PSDONE : IN std_logic ; -- will pulse once, if phase shifting was done.
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104 | LOCKED : IN std_logic ; -- when is this going high?
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105 | -- interface to: w5300_modul.vhd
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106 | shift_phase : IN std_logic ;
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107 | direction : IN std_logic ; -- corresponds TO 'PSINCDEC'
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108 | reset_DCM : IN std_logic ; -- asynch in: orders us, TO reset the DCM
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109 | -- status:
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110 | shifting : OUT std_logic := '0';
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111 | ready : OUT std_logic := '0';
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112 | locked_status_o : OUT std_logic ;
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113 | ready_status_o : OUT std_logic ;
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114 | offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0')
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115 | );
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116 | END COMPONENT;
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117 |
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118 | -- Optional embedded configurations
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119 | -- pragma synthesis_off
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120 | FOR ALL : dcm_50_to_25 USE ENTITY FACT_FAD_lib.dcm_50_to_25;
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121 | FOR ALL : dcm_ps_38ns USE ENTITY FACT_FAD_lib.dcm_ps_38ns;
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122 | FOR ALL : dcm_var_ps_38ns USE ENTITY FACT_FAD_lib.dcm_var_ps_38ns;
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123 | FOR ALL : phase_shifter USE ENTITY FACT_FAD_lib.phase_shifter;
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124 | -- pragma synthesis_on
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125 |
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126 |
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127 | BEGIN
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128 |
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129 | -- Instance port mappings.
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130 | dcm_50_t0_25_inst : dcm_50_to_25
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131 | PORT MAP (
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132 | CLKIN_IN => CLK,
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133 | CLKFX_OUT => CLK_25_internal,
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134 | CLKIN_IBUFG_OUT => OPEN,
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135 | CLK0_OUT => CLK_50
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136 | );
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137 | dcm_25MHz_38ns_const_ps_inst : dcm_ps_38ns
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138 | PORT MAP (
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139 | CLKIN_IN => CLK_25_internal,
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140 | CLK0_OUT => CLK0_OUT
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141 | );
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142 | dcm_var_ps_inst : dcm_var_ps_38ns
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143 | PORT MAP (
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144 | CLKIN_IN => CLK0_OUT,
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145 | PSCLK_IN => PSCLK_IN,
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146 | PSEN_IN => PSEN_IN,
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147 | PSINCDEC_IN => PSINCDEC_IN,
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148 | RST_IN => rst,
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149 | CLK0_OUT => CLK_25_PS,
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150 | LOCKED_OUT => LOCKED_OUT,
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151 | PSDONE_OUT => PSDONE_OUT
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152 | );
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153 | ps_controller_inst : phase_shifter
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154 | PORT MAP (
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155 | CLK => CLK0_OUT,
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156 | rst => rst,
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157 | PSCLK => PSCLK_IN,
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158 | PSEN => PSEN_IN,
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159 | PSINCDEC => PSINCDEC_IN,
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160 | PSDONE => PSDONE_OUT,
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161 | LOCKED => LOCKED_OUT,
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162 | shift_phase => do_shift,
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163 | direction => direction,
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164 | reset_DCM => RST_IN,
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165 | shifting => OPEN,
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166 | ready => OPEN,
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167 | locked_status_o => locked_status_o,
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168 | ready_status_o => ready_status_o,
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169 | offset => offset
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170 | );
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171 |
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172 | -- Implicit buffered output assignments
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173 | CLK_25 <= CLK_25_internal;
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174 |
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175 | END struct;
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