source: firmware/FAD/FACT_FAD_lib/hdl/data_generator.vhd@ 19366

Last change on this file since 19366 was 11755, checked in by neise, 14 years ago
reinit of this svn repos .... it was all too messy deleted the old folders and restarted with FACT_FAD_lib only. (well and the testbenches)
File size: 22.6 KB
Line 
1library IEEE;
2use IEEE.STD_LOGIC_1164.ALL;
3use IEEE.STD_LOGIC_ARITH.ALL;
4use IEEE.STD_LOGIC_UNSIGNED.ALL;
5library fact_fad_lib;
6use fact_fad_lib.fad_definitions.all;
7
8-- -- Uncomment the following library declaration if instantiating
9-- -- any Xilinx primitives in this code.
10-- library UNISIM;
11-- use UNISIM.VComponents.all;
12
13entity data_generator is
14generic(
15 RAM_ADDR_WIDTH : integer := 12
16);
17port(
18 -- for debugging
19 state : out std_logic_vector(7 downto 0);
20 is_idle : out std_logic;
21
22 clk : in std_logic; -- CLK_25.
23 data_out : out std_logic_vector (63 downto 0);
24 addr_out : out std_logic_vector (RAM_ADDR_WIDTH-1 downto 0);
25 dataRAM_write_ea_o : out std_logic_vector (0 downto 0) := "0";
26 ram_start_addr : in std_logic_vector (RAM_ADDR_WIDTH-1 downto 0);
27 ram_write_ea : in std_logic;
28 ram_write_ready : out std_logic := '0';
29
30 roi_array : in roi_array_type;
31 roi_max : in roi_max_type;
32 sensor_array : in sensor_array_type;
33 sensor_ready : in std_logic;
34 dac_array : in dac_array_type;
35
36 config_start : in std_logic;
37 config_done : out std_logic := '0';
38
39-- EVT HEADER - part 1
40 package_length : in std_logic_vector (15 downto 0);
41 pll_lock : in std_logic_vector ( 3 downto 0);
42 dwrite_enable_in : in std_logic;
43 denable_enable_in : in std_logic;
44 busy_enable_in : in std_logic;
45 trigger_enable_in : in std_logic;
46 cont_trigger_en_in : in std_logic;
47 socket_send_mode_in : in std_logic;
48 busy_manual_in : in std_logic;
49
50
51-- EVT HEADER - part 2 --> FTM trigger informaton, comes in late ...
52-- during EVT header wrinting, this field is left out ... and only written into event header,
53-- when the DRS chip were read out already.
54 FTM_RS485_ready : in std_logic;
55 FTM_trigger_info : in std_logic_vector (55 downto 0); --7 byte
56 FTM_receiver_status : in std_logic;
57
58-- EVT HEADER - part 3
59 fad_event_counter : in std_logic_vector (31 downto 0);
60 refclk_counter : in std_logic_vector (11 downto 0);
61 refclk_too_high : in std_logic;
62 refclk_too_low : in std_logic;
63
64-- EVT HEADER - part 4
65 board_id : in std_logic_vector (3 downto 0);
66 crate_id : in std_logic_vector (1 downto 0);
67 DCM_PS_status : in std_logic_vector (7 downto 0);
68 DCM_locked_status : in std_logic;
69 DCM_ready_status : in std_logic;
70 SPI_SCLK_enable_status : in std_logic;
71 TRG_GEN_div : in std_logic_vector (15 downto 0);
72
73-- EVT HEADER - part 5
74 dna : in std_logic_vector (63 downto 0);
75
76-- EVT HEADER - part 6
77 runnumber : in std_logic_vector (31 downto 0);
78 timer_value : in std_logic_vector (31 downto 0); -- time in units of 100us
79
80 hardware_trigger_in : in std_logic;
81 software_trigger_in : in std_logic;
82
83 adc_data_array : in adc_data_array_type;
84 adc_output_enable_inverted : out std_logic := '1';
85 adc_clk_en : out std_logic := '0';
86 adc_otr : in std_logic_vector (3 downto 0);
87 drs_channel_id : out std_logic_vector (3 downto 0) := (others => '0');
88
89--drs_dwrite : out std_logic := '1';
90 drs_readout_ready : out std_logic := '0';
91 drs_readout_ready_ack : in std_logic;
92 drs_clk_en : out std_logic := '0';
93 start_read_drs_stop_cell: out std_logic := '0';
94
95 drs_srin_write_8b : out std_logic := '0';
96 drs_srin_write_ack : in std_logic;
97 drs_srin_data : out std_logic_vector (7 downto 0) := (others => '0');
98 drs_srin_write_ready : in std_logic;
99
100 drs_read_s_cell_ready : in std_logic;
101 drs_s_cell_array : in drs_s_cell_array_type;
102
103 drs_readout_started : out std_logic := '0';
104 trigger_veto : out std_logic := '1'
105);
106end data_generator ;
107
108architecture Behavioral of data_generator is
109
110type state_generate_type is (
111 CONFIG, -- IDLE branches into this state, if needed.
112 CONFIG_DRS_01, -- these four states configure the DRS shift registers,
113 CONFIG_DRS_02, -- the make great use of the drs_pulser entity.
114 CONFIG_DRS_03, -- maybe they should be moved into the drs_pulser entity.
115 WAIT_FOR_DRS_CONFIG_READY,
116
117 IDLE,
118 WRITE_HEADER, WRITE_FTM_INFO, WRITE_EVENTCOUNTER_AND_REFCLK_COUNTER, WRITE_BOARD_ID,
119 WRITE_DNA, WRITE_TIMER, WRITE_TEMPERATURES,
120 WRITE_DAC1, WRITE_DAC2,
121 WAIT_FOR_STOP_CELL,
122 START_DRS_READING,
123 WRITE_CHANNEL_ID, WRITE_START_CELL, WRITE_ROI, WRITE_FILLING,
124 WAIT_FOR_ADC, WRITE_ADC_DATA,
125 WAIT_FOR_EXTERNAL_TRIGGER_READY, WRITE_EXTERNAL_TRIGGER,
126 WRITE_END_FLAG,
127 WRITE_DATA_END, WRITE_DATA_END_WAIT,
128 WRITE_DATA_STOP, WRITE_DATA_STOP1
129);
130
131-- configuration stuff:
132 -- this flag is set, when ever a rising edge on 'config_start' is detected.
133 -- this flag is cleared only, when a configuration was successfully processed
134
135signal state_sig : std_logic_vector(7 downto 0) := (others => '0');
136
137signal state_generate : state_generate_type := CONFIG;
138signal start_addr : std_logic_vector (RAM_ADDR_WIDTH-1 downto 0) := (others => '0');
139
140signal data_cntr : integer range 0 to 1024 := 0;
141signal addr_cntr : integer range 0 to RAM_SIZE_64B := 0; -- counts 64 bit words
142signal channel_id : integer range 0 to 9 := 0;
143signal adc_wait_cnt : integer range 0 to 7 := 0;
144
145signal hardware_trigger_sr :std_logic_vector(1 downto 0) := "00";
146signal software_trigger_sr :std_logic_vector(1 downto 0) := "00";
147
148signal ram_write_ea_flag : std_logic := '0';
149signal new_config_int : std_logic := '0';
150
151-- internal signal: to be sampled once and used instead of inputs!
152signal roi_max_int : roi_max_type;
153signal package_length_sig : std_logic_vector (15 downto 0);
154signal sig_drs_readout_started : std_logic := '0';
155
156signal FTM_trigger_info_local_copy : std_logic_vector (55 downto 0) := (others => '0'); --7 byte
157signal runnumber_local_copy : std_logic_vector (31 downto 0);
158
159-- self configuration signals:
160signal internal_roi_array : roi_array_type;
161signal internal_roi_max : roi_max_type;
162
163signal config_start_sr : std_logic_vector(1 downto 0) := "00";
164
165signal adc_data_sig : adc_data_array_type;
166signal adc_otr_sig : std_logic_vector(3 downto 0) ;
167type adc_data_16bit_t is array (3 downto 0) of std_logic_vector(15 downto 0);
168signal data_16bit : adc_data_16bit_t;
169
170begin
171drs_readout_started <= sig_drs_readout_started;
172state <= state_sig;
173generate_data : process (clk)
174begin
175 if rising_edge (clk) then
176 is_idle <= '0';
177 -- synch
178 config_start_sr <= config_start_sr(0) & config_start;
179
180
181 hardware_trigger_sr <= hardware_trigger_sr(0) & hardware_trigger_in; --synching in of asynchrounous trigger signal.
182 software_trigger_sr <= software_trigger_sr(0) & software_trigger_in; --synching in of asynchrounous trigger signal.
183 addr_out <= start_addr + conv_std_logic_vector(addr_cntr, RAM_ADDR_WIDTH);
184
185 case state_generate is
186
187
188 when CONFIG =>
189 state_sig <= X"01";
190 internal_roi_array <= roi_array;
191 package_length_sig <= package_length;
192 internal_roi_max <= roi_max;
193 state_generate <= CONFIG_DRS_01;
194 -- configure DRS
195 -- all this might be done in the drs_pulser entity
196 when CONFIG_DRS_01 => -- BEGIN CONFIG DRS
197 state_sig <= X"02";
198 drs_channel_id <= DRS_WRITE_SHIFT_REG;
199 drs_srin_data <= "11111111";
200 drs_srin_write_8b <= '1';
201 if (drs_srin_write_ack = '1') then
202 drs_srin_write_8b <= '0';
203 state_generate <= CONFIG_DRS_02;
204 end if;
205 when CONFIG_DRS_02 =>
206 state_sig <= X"03";
207 if (drs_srin_write_ready = '1') then
208 state_generate <= CONFIG_DRS_03;
209 end if;
210 when CONFIG_DRS_03 =>
211 state_sig <= X"04";
212 drs_channel_id <= DRS_WRITE_CONFIG_REG;
213 drs_srin_data <= "11111111";
214 drs_srin_write_8b <= '1';
215 if (drs_srin_write_ack = '1') then
216 drs_srin_write_8b <= '0';
217 state_generate <= WAIT_FOR_DRS_CONFIG_READY;
218 end if;
219
220 -- last state of CONFIG:
221 -- here the input roi_max is sampled
222 -- all other interesting input signals should be sampled here as well!
223 when WAIT_FOR_DRS_CONFIG_READY => -- END OF CONFIG
224 state_sig <= X"05";
225 if (drs_srin_write_ready = '1') then
226 drs_channel_id <= DRS_ADDR_IDLE; -- to make sure not to write accidentally into DRS shift registers
227 roi_max_int <= internal_roi_max;
228 config_done <= '1';
229 state_generate <= IDLE;
230 end if;
231 -- end configure DRS
232
233
234 when IDLE =>
235 is_idle <= '1';
236 state_sig <= X"10";
237 state_generate <= IDLE;
238 trigger_veto <= '0';
239 if (config_start_sr(1) = '1') then
240 state_generate <= CONFIG;
241 config_done <= '0';
242 end if;
243
244
245 if (ram_write_ea = '1' and ( hardware_trigger_sr(1) = '1' or software_trigger_sr(1) = '1') ) then
246 sig_drs_readout_started <= '1'; -- is set to '0' in next state ... just a pulse.
247 runnumber_local_copy <= runnumber;
248 trigger_veto <= '1';
249 start_read_drs_stop_cell <= '1';
250 adc_output_enable_inverted <= '0';
251 -- at this moment the ADC ist beeing clocked.
252 -- this is not the start of the readout.
253 -- the DRS needs to be clocked as well.
254 adc_clk_en <= '1';
255 start_addr <= ram_start_addr;
256 state_generate <= WRITE_HEADER;
257 end if;
258
259
260 when WRITE_HEADER =>
261 state_sig <= X"11";
262 sig_drs_readout_started <= '0'; -- is set to '1' in state IDLE
263 dataRAM_write_ea_o <= "1";
264 data_out <=
265 -- the first word contains a lot of single status bits.
266 pll_lock & -- 4 bits
267 denable_enable_in & -- 1 bit
268 dwrite_enable_in & -- 1 bit
269 '0' & -- 1 bit
270 refclk_too_low & -- 1 bit
271 DCM_locked_status & -- 1 bit
272 DCM_ready_status & -- 1 bit
273 SPI_SCLK_enable_status &-- 1 bit
274 busy_enable_in &
275 trigger_enable_in &
276 cont_trigger_en_in &
277 socket_send_mode_in&
278 busy_manual_in &
279 PACKAGE_VERSION & PACKAGE_SUB_VERSION &
280 package_length_sig &
281 X"FB01";
282 addr_cntr <= addr_cntr + 1;
283 state_generate <= WRITE_FTM_INFO;
284
285 when WRITE_FTM_INFO =>
286 state_sig <= X"12";
287 -- THIS is just a dummy STATE just to make reading easier.
288 -- at this point normally the FTM RS485 data would be written .. but we do not know it
289 -- so here we do not write the FTM info ... just jump over it.
290 addr_cntr <= addr_cntr + 1;
291 state_generate <= WRITE_EVENTCOUNTER_AND_REFCLK_COUNTER;
292
293 when WRITE_EVENTCOUNTER_AND_REFCLK_COUNTER =>
294 state_sig <= X"13";
295 data_out <=
296 "0000" & refclk_counter &
297 X"0000" &
298 fad_event_counter(15 downto 0) &
299 fad_event_counter(31 downto 16) ;
300 addr_cntr <= addr_cntr + 1;
301 state_generate <= WRITE_BOARD_ID;
302
303 when WRITE_BOARD_ID =>
304 state_sig <= X"14";
305 data_out <= TRG_GEN_div & -- this is a kind of prescaler for the continouus trigger generator
306 X"0000" & -- this might be the number of soft triggers beeing generated in a 'burst' not implemented yet
307 X"00" & DCM_PS_status & -- number of steps, the phase shifter was shifted...
308 "000000" & crate_id & "0000" & board_id; -- position of the board inside the camera
309 addr_cntr <= addr_cntr + 1;
310 state_generate <= WRITE_DNA;
311
312 when WRITE_DNA =>
313 state_sig <= X"15";
314 data_out <=
315 dna(55 downto 48) & dna(63 downto 56) &
316 dna(39 downto 32) & dna(47 downto 40) &
317 dna(23 downto 16) & dna(31 downto 24) &
318 dna(7 downto 0) & dna(15 downto 8);
319 addr_cntr <= addr_cntr + 1;
320 state_generate <= WRITE_TIMER;
321
322 when WRITE_TIMER =>
323 state_sig <= X"16";
324 data_out <=
325 runnumber_local_copy(15 downto 0) & -- 2times 16bit reserved for additional status info
326 runnumber_local_copy(31 downto 16) &
327 timer_value(15 downto 0) &
328 timer_value(31 downto 16);
329 addr_cntr <= addr_cntr + 1;
330 state_generate <= WRITE_TEMPERATURES;
331
332 -- DANGER: thist state can wait endlessly, if somethings wrong.
333 when WRITE_TEMPERATURES => -- temperatures
334 state_sig <= X"17";
335 if (sensor_ready = '1') then
336 data_out <=
337 conv_std_logic_vector(sensor_array (3), 16)(15) &
338 conv_std_logic_vector(sensor_array (3), 16)(15) &
339 conv_std_logic_vector(sensor_array (3), 16)(15) &
340 conv_std_logic_vector(sensor_array (3), 16)(15 downto 3) &
341 conv_std_logic_vector(sensor_array (2), 16)(15) &
342 conv_std_logic_vector(sensor_array (2), 16)(15) &
343 conv_std_logic_vector(sensor_array (2), 16)(15) &
344 conv_std_logic_vector(sensor_array (2), 16)(15 downto 3) &
345 conv_std_logic_vector(sensor_array (1), 16)(15) &
346 conv_std_logic_vector(sensor_array (1), 16)(15) &
347 conv_std_logic_vector(sensor_array (1), 16)(15) &
348 conv_std_logic_vector(sensor_array (1), 16)(15 downto 3) &
349 conv_std_logic_vector(sensor_array (0), 16)(15) &
350 conv_std_logic_vector(sensor_array (0), 16)(15) &
351 conv_std_logic_vector(sensor_array (0), 16)(15) &
352 conv_std_logic_vector(sensor_array (0), 16)(15 downto 3) ;
353-- conv_std_logic_vector (sensor_array (2), 16) &
354-- conv_std_logic_vector (sensor_array (1), 16) &
355-- conv_std_logic_vector (sensor_array (0), 16);
356 addr_cntr <= addr_cntr + 1;
357 state_generate <= WRITE_DAC1;
358 end if;
359
360 when WRITE_DAC1 =>
361 state_sig <= X"18";
362 data_out <= conv_std_logic_vector (dac_array (3), 16) &
363 conv_std_logic_vector (dac_array (2), 16) &
364 conv_std_logic_vector (dac_array (1), 16) &
365 conv_std_logic_vector (dac_array (0), 16);
366 addr_cntr <= addr_cntr + 1;
367 state_generate <= WRITE_DAC2;
368 when WRITE_DAC2 =>
369 state_sig <= X"19";
370 data_out <= conv_std_logic_vector (dac_array (7), 16) &
371 conv_std_logic_vector (dac_array (6), 16) &
372 conv_std_logic_vector (dac_array (5), 16) &
373 conv_std_logic_vector (dac_array (4), 16);
374 addr_cntr <= addr_cntr + 1;
375 state_generate <= WAIT_FOR_STOP_CELL;
376
377 when WAIT_FOR_STOP_CELL =>
378 state_sig <= X"1A";
379 start_read_drs_stop_cell <= '0';
380 if (drs_read_s_cell_ready = '1') then
381 state_generate <= START_DRS_READING;
382 end if;
383
384 when START_DRS_READING =>
385 --drs channel number
386 drs_channel_id <= conv_std_logic_vector (channel_id, 4);
387
388 --adc_output_enable_inverted <= '0'; -- nur für Emulator ??????????????????
389 -- this has been done earlier already ... why does it need to be repeated?
390
391 --starte drs-clocking
392 -- this is an interesting point:
393 -- here the DRS clock starts to tick. but only some states later
394 -- the ADC data is actually read out.
395 -- the reason is, that the ADC has a latency of 7 clock cycles, which means,
396 -- when the next rising edge of the DRS clock is produced.
397 -- an analog value is put out.
398 -- when the next rising edge of the ADC clock is produced.
399 -- this very analog value is sampled.
400 -- but only seven clock ticks later, the degital result is available.
401 -- from that point on, every clock tick produces a valid digital result.
402 drs_clk_en <= '1';
403 adc_wait_cnt <= 0;
404 state_generate <= WRITE_CHANNEL_ID;
405
406 when WRITE_CHANNEL_ID => -- write DRS and Channel IDs
407 state_sig <= X"1B";
408 data_out <= conv_std_logic_vector(3,12) & conv_std_logic_vector(channel_id,4) &
409 conv_std_logic_vector(2,12) & conv_std_logic_vector(channel_id,4) &
410 conv_std_logic_vector(1,12) & conv_std_logic_vector(channel_id,4) &
411 conv_std_logic_vector(0,12) & conv_std_logic_vector(channel_id,4);
412 addr_cntr <= addr_cntr + 1;
413 state_generate <= WRITE_START_CELL;
414 when WRITE_START_CELL => -- write start cells
415 state_sig <= X"1C";
416 data_out <= "000000" & drs_s_cell_array (3) &
417 "000000" & drs_s_cell_array (2) &
418 "000000" & drs_s_cell_array (1) &
419 "000000" & drs_s_cell_array (0);
420 addr_cntr <= addr_cntr + 1;
421 state_generate <= WRITE_ROI;
422
423 when WRITE_ROI => -- write ROI
424 state_sig <= X"1D";
425 data_out <= "00000" & conv_std_logic_vector (internal_roi_array((3) * 9 + channel_id), 11) &
426 "00000" & conv_std_logic_vector (internal_roi_array((2) * 9 + channel_id), 11) &
427 "00000" & conv_std_logic_vector (internal_roi_array((1) * 9 + channel_id), 11) &
428 "00000" & conv_std_logic_vector (internal_roi_array((0) * 9 + channel_id), 11);
429 addr_cntr <= addr_cntr + 1;
430 state_generate <= WRITE_FILLING;
431
432 when WRITE_FILLING => -- write FILLING
433 state_sig <= X"1E";
434 data_out <= conv_std_logic_vector(0,64); -- filling
435 addr_cntr <= addr_cntr + 1;
436 state_generate <= WAIT_FOR_ADC;
437
438 when WAIT_FOR_ADC =>
439 state_sig <= X"1F";
440 -- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
441 if (adc_wait_cnt < 4 ) then -- anpassen!!!! -- 3 für Simulation, 4 für FPGA???
442 adc_wait_cnt <= adc_wait_cnt + 1;
443 else
444 state_generate <= WRITE_ADC_DATA;
445 end if;
446
447-- when CATCH_ADC_DATA =>
448-- adc_data_sig <= adc_data_array;
449-- adc_otr_sig <= adc_otr;
450-- state_generate <= PREPARE_ADC_DATA_01;
451--
452-- when PREPARE_ADC_DATA_01 =>
453-- for i in 3 downto 0 loop
454-- if (adc_otr_sig(i)='1') then
455-- if (adc_data_sig(i)(11)='1') then
456-- data_16bit(i) = X"8000" --this is decimal -1
457-- else -- adc_data_sig(i)(11)='0'
458-- data_16bit(i) = X"1001" --this is decimal +4097
459-- end if;
460-- else -- no over/underflow
461-- data_16bit(i) =
462-- end loop;
463
464
465
466 when WRITE_ADC_DATA =>
467 state_sig <= X"20";
468 if (data_cntr < roi_max_int (channel_id)) then
469 data_out <=
470 --DRS chip 3 LOW BYTE
471 (adc_otr(3) xor adc_data_array(3)(7)) &
472 (adc_otr(3) xor adc_data_array(3)(6)) &
473 (adc_otr(3) xor adc_data_array(3)(5)) &
474 (adc_otr(3) xor adc_data_array(3)(4)) &
475 (adc_otr(3) xor adc_data_array(3)(3)) &
476 (adc_otr(3) xor adc_data_array(3)(2)) &
477 (adc_otr(3) xor adc_data_array(3)(1)) &
478 (adc_otr(3) xor adc_data_array(3)(0)) &
479 --DRS chip 3 HIGH BYTE
480 adc_data_array(3)(11) &
481 adc_data_array(3)(11) &
482 adc_data_array(3)(11) &
483 adc_data_array(3)(11) &
484 (adc_otr(3) xor adc_data_array(3)(11)) &
485 (adc_otr(3) xor adc_data_array(3)(10)) &
486 (adc_otr(3) xor adc_data_array(3)(9)) &
487 (adc_otr(3) xor adc_data_array(3)(8)) &
488 --DRS chip 2 LOW BYTE
489 (adc_otr(2) xor adc_data_array(2)(7)) &
490 (adc_otr(2) xor adc_data_array(2)(6)) &
491 (adc_otr(2) xor adc_data_array(2)(5)) &
492 (adc_otr(2) xor adc_data_array(2)(4)) &
493 (adc_otr(2) xor adc_data_array(2)(3)) &
494 (adc_otr(2) xor adc_data_array(2)(2)) &
495 (adc_otr(2) xor adc_data_array(2)(1)) &
496 (adc_otr(2) xor adc_data_array(2)(0)) &
497 --DRS chip 2 HIGH BYTE
498 adc_data_array(2)(11) &
499 adc_data_array(2)(11) &
500 adc_data_array(2)(11) &
501 adc_data_array(2)(11) &
502 (adc_otr(2) xor adc_data_array(2)(11)) &
503 (adc_otr(2) xor adc_data_array(2)(10)) &
504 (adc_otr(2) xor adc_data_array(2)(9)) &
505 (adc_otr(2) xor adc_data_array(2)(8)) &
506 --DRS chip 1 LOW BYTE
507 (adc_otr(1) xor adc_data_array(1)(7)) &
508 (adc_otr(1) xor adc_data_array(1)(6)) &
509 (adc_otr(1) xor adc_data_array(1)(5)) &
510 (adc_otr(1) xor adc_data_array(1)(4)) &
511 (adc_otr(1) xor adc_data_array(1)(3)) &
512 (adc_otr(1) xor adc_data_array(1)(2)) &
513 (adc_otr(1) xor adc_data_array(1)(1)) &
514 (adc_otr(1) xor adc_data_array(1)(0)) &
515 --DRS chip 1 HIGH BYTE
516 adc_data_array(1)(11) &
517 adc_data_array(1)(11) &
518 adc_data_array(1)(11) &
519 adc_data_array(1)(11) &
520 (adc_otr(1) xor adc_data_array(1)(11)) &
521 (adc_otr(1) xor adc_data_array(1)(10)) &
522 (adc_otr(1) xor adc_data_array(1)(9)) &
523 (adc_otr(1) xor adc_data_array(1)(8)) &
524 --DRS chip 0 LOW BYTE
525 (adc_otr(0) xor adc_data_array(0)(7)) &
526 (adc_otr(0) xor adc_data_array(0)(6)) &
527 (adc_otr(0) xor adc_data_array(0)(5)) &
528 (adc_otr(0) xor adc_data_array(0)(4)) &
529 (adc_otr(0) xor adc_data_array(0)(3)) &
530 (adc_otr(0) xor adc_data_array(0)(2)) &
531 (adc_otr(0) xor adc_data_array(0)(1)) &
532 (adc_otr(0) xor adc_data_array(0)(0)) &
533 --DRS chip 0 HIGH BYTE
534 adc_data_array(0)(11) &
535 adc_data_array(0)(11) &
536 adc_data_array(0)(11) &
537 adc_data_array(0)(11) &
538 (adc_otr(0) xor adc_data_array(0)(11)) &
539 (adc_otr(0) xor adc_data_array(0)(10)) &
540 (adc_otr(0) xor adc_data_array(0)(9)) &
541 (adc_otr(0) xor adc_data_array(0)(8)) ;
542
543 --adc_data_array(3)(7 downto 0) & "000" & adc_otr(3) & adc_data_array(3)(11 downto 8) &
544 --adc_data_array(2)(7 downto 0) & "000" & adc_otr(2) & adc_data_array(2)(11 downto 8) &
545 --adc_data_array(1)(7 downto 0) & "000" & adc_otr(1) & adc_data_array(1)(11 downto 8) &
546 --adc_data_array(0)(7 downto 0) & "000" & adc_otr(0) & adc_data_array(0)(11 downto 8) ;
547
548 addr_cntr <= addr_cntr + 1;
549 state_generate <= WRITE_ADC_DATA;
550 data_cntr <= data_cntr + 1;
551 else
552 drs_clk_en <= '0';
553 --adc_output_enable_inverted <= '1'; -- nur für Emulator
554 if (channel_id = 8) then
555 state_generate <= WAIT_FOR_EXTERNAL_TRIGGER_READY;
556 adc_output_enable_inverted <= '1';
557 -- switch off ADC_CLK
558 adc_clk_en <= '0';
559 else
560 channel_id <= channel_id + 1; -- increment channel_id
561 state_generate <= START_DRS_READING;
562 data_cntr <= 0;
563 end if;
564 end if;
565
566 when WAIT_FOR_EXTERNAL_TRIGGER_READY =>
567 state_sig <= X"21";
568 state_generate <= WAIT_FOR_EXTERNAL_TRIGGER_READY;
569 if (FTM_RS485_ready = '1') then
570 --make local copy and proceed
571 FTM_trigger_info_local_copy <= FTM_trigger_info;
572 state_generate <= WRITE_EXTERNAL_TRIGGER;
573 end if;
574
575
576 when WRITE_EXTERNAL_TRIGGER => -- external trigger ID
577 state_sig <= X"22";
578 addr_out <= start_addr + conv_std_logic_vector(1, RAM_ADDR_WIDTH);
579 data_out <= FTM_trigger_info_local_copy(15 downto 0) &
580 FTM_trigger_info_local_copy(31 downto 16) &
581 FTM_trigger_info_local_copy(47 downto 32) &
582 "0000000"& FTM_receiver_status & FTM_trigger_info_local_copy(55 downto 48);
583 state_generate <= WRITE_END_FLAG;
584
585 when WRITE_END_FLAG =>
586 state_sig <= X"23";
587 data_out <= conv_std_logic_vector(0, 32) & X"04FE" & X"4242";
588 addr_cntr <= addr_cntr + 1;
589 state_generate <= WRITE_DATA_END;
590 when WRITE_DATA_END =>
591 state_sig <= X"24";
592 dataRAM_write_ea_o <= "0";
593 --information to: memory manager.
594 -- one Event was completely written into dataRAM.
595
596 -- post writing handshake with MM:
597 -- if 'write_enable' = '1' everything is normal and DG informs MM
598 -- about finished write process by raising 'write_ready'
599 -- if 'write_enable' = '0'
600 -- something strange happened and waiting for 'write_enable' going '1' might cause a dead lock.
601 -- so the reaction is to go back to IDLE state without informing MM.
602 -- this means actually discarding the event.
603 if ( ram_write_ea ='1' ) then
604 ram_write_ready <= '1';
605 state_generate <= WRITE_DATA_END_WAIT;
606 else
607 state_generate <= WRITE_DATA_STOP;
608 end if;
609
610 when WRITE_DATA_END_WAIT =>
611 state_sig <= X"25";
612 if (ram_write_ea = '0') then
613 state_generate <= WRITE_DATA_STOP;
614 ram_write_ready <= '0';
615 end if;
616 when WRITE_DATA_STOP =>
617 state_sig <= X"26";
618 drs_readout_ready <= '1'; --info to: trigger manager.
619 data_cntr <= 0;
620 addr_cntr <= 0;
621 channel_id <= 0;
622 state_generate <= WRITE_DATA_STOP1;
623
624 when WRITE_DATA_STOP1 =>
625 state_sig <= X"27";
626 if (drs_readout_ready_ack = '1') then
627 drs_readout_ready <= '0';
628 state_generate <= IDLE;
629 end if;
630 when others =>
631 null;
632 end case; -- state_generate
633 end if; -- rising_edge (clk)
634end process generate_data;
635end Behavioral;
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