source: firmware/FAD/FACT_FAD_lib/hdl/dcm_50_to_25_BEHAVIORAL.vhd@ 19825

Last change on this file since 19825 was 11755, checked in by neise, 14 years ago
reinit of this svn repos .... it was all too messy deleted the old folders and restarted with FACT_FAD_lib only. (well and the testbenches)
File size: 6.7 KB
Line 
1-- Coregen VHDL wrapper file modified by HDL Designer
2
3--------------------------------------------------------------------------------
4-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
5--------------------------------------------------------------------------------
6-- ____ ____
7-- / /\/ /
8-- /___/ \ / Vendor: Xilinx
9-- \ \ \/ Version : 10.1.03
10-- \ \ Application : xaw2vhdl
11-- / / Filename : dcm_50_to_25.vhd
12-- /___/ /\ Timestamp : 08/24/2010 12:18:50
13-- \ \ / \
14-- \___\/\___\
15--
16--Command: xaw2vhdl-st C:/DOKUME~1/dneise/LOKALE~1/Temp/coregen_dneise/coregen/project/dcm_50_to_25.xaw C:/DOKUME~1/dneise/LOKALE~1/Temp/coregen_dneise/coregen/project/dcm_50_to_25
17--Design Name: dcm_50_to_25
18--Device: xc3s50a-5tq144
19--
20-- Module dcm_50_to_25
21-- Written for synthesis tool: Precision
22
23library ieee;
24use ieee.std_logic_1164.ALL;
25use ieee.numeric_std.ALL;
26library UNISIM;
27use UNISIM.Vcomponents.ALL;
28
29entity dcm_50_to_25 is
30 port ( CLKIN_IN : in std_logic;
31 CLKFX_OUT : out std_logic;
32 CLKIN_IBUFG_OUT : out std_logic;
33 CLK0_OUT : out std_logic);
34end dcm_50_to_25;
35
36architecture BEHAVIORAL of dcm_50_to_25 is
37
38-- hds translate_off
39
40 attribute CLK_FEEDBACK : string ;
41 attribute CLKDV_DIVIDE : string ;
42 attribute CLKFX_DIVIDE : string ;
43 attribute CLKFX_MULTIPLY : string ;
44 attribute CLKIN_DIVIDE_BY_2 : string ;
45 attribute CLKIN_PERIOD : string ;
46 attribute CLKOUT_PHASE_SHIFT : string ;
47 attribute DESKEW_ADJUST : string ;
48 attribute DFS_FREQUENCY_MODE : string ;
49 attribute DLL_FREQUENCY_MODE : string ;
50 attribute DUTY_CYCLE_CORRECTION : string ;
51 attribute FACTORY_JF : string ;
52 attribute PHASE_SHIFT : string ;
53 attribute STARTUP_WAIT : string ;
54 signal CLKFB_IN : std_logic;
55 signal CLKFX_BUF : std_logic;
56 signal CLKIN_IBUFG : std_logic;
57 signal CLK0_BUF : std_logic;
58 signal GND_BIT : std_logic;
59 component BUFG
60 port ( I : in std_logic;
61 O : out std_logic);
62 end component;
63
64 component IBUFG
65 port ( I : in std_logic;
66 O : out std_logic);
67 end component;
68
69 -- Period Jitter (unit interval) for block DCM_SP_INST = 0.02 UI
70 -- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 1.18 ns
71 component DCM_SP
72 -- pragma synthesis_off
73 generic( CLK_FEEDBACK : string := "1X";
74 CLKDV_DIVIDE : real := 2.0;
75 CLKFX_DIVIDE : integer := 1;
76 CLKFX_MULTIPLY : integer := 4;
77 CLKIN_DIVIDE_BY_2 : boolean := FALSE;
78 CLKIN_PERIOD : real := 10.0;
79 CLKOUT_PHASE_SHIFT : string := "NONE";
80 DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
81 DFS_FREQUENCY_MODE : string := "LOW";
82 DLL_FREQUENCY_MODE : string := "LOW";
83 DUTY_CYCLE_CORRECTION : boolean := TRUE;
84 FACTORY_JF : bit_vector := x"C080";
85 PHASE_SHIFT : integer := 0;
86 STARTUP_WAIT : boolean := FALSE;
87 DSS_MODE : string := "NONE");
88 -- pragma synthesis_on
89 port ( CLKIN : in std_logic;
90 CLKFB : in std_logic;
91 RST : in std_logic;
92 PSEN : in std_logic;
93 PSINCDEC : in std_logic;
94 PSCLK : in std_logic;
95 DSSEN : in std_logic;
96 CLK0 : out std_logic;
97 CLK90 : out std_logic;
98 CLK180 : out std_logic;
99 CLK270 : out std_logic;
100 CLKDV : out std_logic;
101 CLK2X : out std_logic;
102 CLK2X180 : out std_logic;
103 CLKFX : out std_logic;
104 CLKFX180 : out std_logic;
105 STATUS : out std_logic_vector (7 downto 0);
106 LOCKED : out std_logic;
107 PSDONE : out std_logic);
108 end component;
109
110 attribute CLK_FEEDBACK of DCM_SP_INST : label is "1X";
111 attribute CLKDV_DIVIDE of DCM_SP_INST : label is "2.0";
112 attribute CLKFX_DIVIDE of DCM_SP_INST : label is "5";
113 attribute CLKFX_MULTIPLY of DCM_SP_INST : label is "2";
114 attribute CLKIN_DIVIDE_BY_2 of DCM_SP_INST : label is "FALSE";
115 attribute CLKIN_PERIOD of DCM_SP_INST : label is "20.000";
116 attribute CLKOUT_PHASE_SHIFT of DCM_SP_INST : label is "NONE";
117 attribute DESKEW_ADJUST of DCM_SP_INST : label is "SYSTEM_SYNCHRONOUS";
118 attribute DFS_FREQUENCY_MODE of DCM_SP_INST : label is "LOW";
119 attribute DLL_FREQUENCY_MODE of DCM_SP_INST : label is "LOW";
120 attribute DUTY_CYCLE_CORRECTION of DCM_SP_INST : label is "TRUE";
121 attribute FACTORY_JF of DCM_SP_INST : label is "C080";
122 attribute PHASE_SHIFT of DCM_SP_INST : label is "0";
123 attribute STARTUP_WAIT of DCM_SP_INST : label is "FALSE";
124
125-- hds translate_on
126
127begin
128
129-- hds translate_off
130
131 GND_BIT <= '0';
132 CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
133 CLK0_OUT <= CLKFB_IN;
134 CLKFX_BUFG_INST : BUFG
135 port map (I=>CLKFX_BUF,
136 O=>CLKFX_OUT);
137
138 CLKIN_IBUFG_INST : IBUFG
139 port map (I=>CLKIN_IN,
140 O=>CLKIN_IBUFG);
141
142 CLK0_BUFG_INST : BUFG
143 port map (I=>CLK0_BUF,
144 O=>CLKFB_IN);
145
146 DCM_SP_INST : DCM_SP
147 -- pragma synthesis_off
148 generic map( CLK_FEEDBACK => "1X",
149 CLKDV_DIVIDE => 2.0,
150 CLKFX_DIVIDE => 5,
151 CLKFX_MULTIPLY => 2,
152 CLKIN_DIVIDE_BY_2 => FALSE,
153 CLKIN_PERIOD => 20.000,
154 CLKOUT_PHASE_SHIFT => "NONE",
155 DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
156 DFS_FREQUENCY_MODE => "LOW",
157 DLL_FREQUENCY_MODE => "LOW",
158 DUTY_CYCLE_CORRECTION => TRUE,
159 FACTORY_JF => x"C080",
160 PHASE_SHIFT => 0,
161 STARTUP_WAIT => FALSE)
162 -- pragma synthesis_on
163 port map (CLKFB=>CLKFB_IN,
164 CLKIN=>CLKIN_IBUFG,
165 DSSEN=>GND_BIT,
166 PSCLK=>GND_BIT,
167 PSEN=>GND_BIT,
168 PSINCDEC=>GND_BIT,
169 RST=>GND_BIT,
170 CLKDV=>open,
171 CLKFX=>CLKFX_BUF,
172 CLKFX180=>open,
173 CLK0=>CLK0_BUF,
174 CLK2X=>open,
175 CLK2X180=>open,
176 CLK90=>open,
177 CLK180=>open,
178 CLK270=>open,
179 LOCKED=>open,
180 PSDONE=>open,
181 STATUS=>open);
182
183
184-- hds translate_on
185
186end BEHAVIORAL;
187
188
189
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