source: firmware/FAD/FACT_FAD_lib/hdl/dcm_ps_38ns_BEHAVIORAL.vhd

Last change on this file was 11755, checked in by neise, 13 years ago
reinit of this svn repos .... it was all too messy deleted the old folders and restarted with FACT_FAD_lib only. (well and the testbenches)
File size: 6.0 KB
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1-- Coregen VHDL wrapper file modified by HDL Designer
2
3--------------------------------------------------------------------------------
4-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
5--------------------------------------------------------------------------------
6-- ____ ____
7-- / /\/ /
8-- /___/ \ / Vendor: Xilinx
9-- \ \ \/ Version : 10.1.03
10-- \ \ Application : xaw2vhdl
11-- / / Filename : dcm_ps_38ns.vhd
12-- /___/ /\ Timestamp : 08/24/2010 12:01:59
13-- \ \ / \
14-- \___\/\___\
15--
16--Command: xaw2vhdl-st C:/DOKUME~1/dneise/LOKALE~1/Temp/coregen_dneise/coregen/project/dcm_ps_38ns.xaw C:/DOKUME~1/dneise/LOKALE~1/Temp/coregen_dneise/coregen/project/dcm_ps_38ns
17--Design Name: dcm_ps_38ns
18--Device: xc3s50a-5tq144
19--
20-- Module dcm_ps_38ns
21-- Written for synthesis tool: Precision
22
23library ieee;
24use ieee.std_logic_1164.ALL;
25use ieee.numeric_std.ALL;
26library UNISIM;
27use UNISIM.Vcomponents.ALL;
28
29entity dcm_ps_38ns is
30 port ( CLKIN_IN : in std_logic;
31 CLK0_OUT : out std_logic);
32end dcm_ps_38ns;
33
34architecture BEHAVIORAL of dcm_ps_38ns is
35
36-- hds translate_off
37
38 attribute CLK_FEEDBACK : string ;
39 attribute CLKDV_DIVIDE : string ;
40 attribute CLKFX_DIVIDE : string ;
41 attribute CLKFX_MULTIPLY : string ;
42 attribute CLKIN_DIVIDE_BY_2 : string ;
43 attribute CLKIN_PERIOD : string ;
44 attribute CLKOUT_PHASE_SHIFT : string ;
45 attribute DESKEW_ADJUST : string ;
46 attribute DFS_FREQUENCY_MODE : string ;
47 attribute DLL_FREQUENCY_MODE : string ;
48 attribute DUTY_CYCLE_CORRECTION : string ;
49 attribute FACTORY_JF : string ;
50 attribute PHASE_SHIFT : string ;
51 attribute STARTUP_WAIT : string ;
52 signal CLKFB_IN : std_logic;
53 signal CLK0_BUF : std_logic;
54 signal GND_BIT : std_logic;
55 component BUFG
56 port ( I : in std_logic;
57 O : out std_logic);
58 end component;
59
60 component DCM_SP
61 -- pragma synthesis_off
62 generic( CLK_FEEDBACK : string := "1X";
63 CLKDV_DIVIDE : real := 2.0;
64 CLKFX_DIVIDE : integer := 1;
65 CLKFX_MULTIPLY : integer := 4;
66 CLKIN_DIVIDE_BY_2 : boolean := FALSE;
67 CLKIN_PERIOD : real := 10.0;
68 CLKOUT_PHASE_SHIFT : string := "NONE";
69 DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
70 DFS_FREQUENCY_MODE : string := "LOW";
71 DLL_FREQUENCY_MODE : string := "LOW";
72 DUTY_CYCLE_CORRECTION : boolean := TRUE;
73 FACTORY_JF : bit_vector := x"C080";
74 PHASE_SHIFT : integer := 0;
75 STARTUP_WAIT : boolean := FALSE;
76 DSS_MODE : string := "NONE");
77 -- pragma synthesis_on
78 port ( CLKIN : in std_logic;
79 CLKFB : in std_logic;
80 RST : in std_logic;
81 PSEN : in std_logic;
82 PSINCDEC : in std_logic;
83 PSCLK : in std_logic;
84 DSSEN : in std_logic;
85 CLK0 : out std_logic;
86 CLK90 : out std_logic;
87 CLK180 : out std_logic;
88 CLK270 : out std_logic;
89 CLKDV : out std_logic;
90 CLK2X : out std_logic;
91 CLK2X180 : out std_logic;
92 CLKFX : out std_logic;
93 CLKFX180 : out std_logic;
94 STATUS : out std_logic_vector (7 downto 0);
95 LOCKED : out std_logic;
96 PSDONE : out std_logic);
97 end component;
98
99 attribute CLK_FEEDBACK of DCM_SP_INST : label is "1X";
100 attribute CLKDV_DIVIDE of DCM_SP_INST : label is "2.0";
101 attribute CLKFX_DIVIDE of DCM_SP_INST : label is "1";
102 attribute CLKFX_MULTIPLY of DCM_SP_INST : label is "4";
103 attribute CLKIN_DIVIDE_BY_2 of DCM_SP_INST : label is "FALSE";
104 attribute CLKIN_PERIOD of DCM_SP_INST : label is "50.000";
105 attribute CLKOUT_PHASE_SHIFT of DCM_SP_INST : label is "FIXED";
106 attribute DESKEW_ADJUST of DCM_SP_INST : label is "SYSTEM_SYNCHRONOUS";
107 attribute DFS_FREQUENCY_MODE of DCM_SP_INST : label is "LOW";
108 attribute DLL_FREQUENCY_MODE of DCM_SP_INST : label is "LOW";
109 attribute DUTY_CYCLE_CORRECTION of DCM_SP_INST : label is "TRUE";
110 attribute FACTORY_JF of DCM_SP_INST : label is "C080";
111 attribute PHASE_SHIFT of DCM_SP_INST : label is "195";
112 attribute STARTUP_WAIT of DCM_SP_INST : label is "FALSE";
113
114-- hds translate_on
115
116begin
117
118-- hds translate_off
119
120 GND_BIT <= '0';
121 CLK0_OUT <= CLKFB_IN;
122 CLK0_BUFG_INST : BUFG
123 port map (I=>CLK0_BUF,
124 O=>CLKFB_IN);
125
126 DCM_SP_INST : DCM_SP
127 -- pragma synthesis_off
128 generic map( CLK_FEEDBACK => "1X",
129 CLKDV_DIVIDE => 2.0,
130 CLKFX_DIVIDE => 1,
131 CLKFX_MULTIPLY => 4,
132 CLKIN_DIVIDE_BY_2 => FALSE,
133 CLKIN_PERIOD => 50.000,
134 CLKOUT_PHASE_SHIFT => "FIXED",
135 DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
136 DFS_FREQUENCY_MODE => "LOW",
137 DLL_FREQUENCY_MODE => "LOW",
138 DUTY_CYCLE_CORRECTION => TRUE,
139 FACTORY_JF => x"C080",
140 PHASE_SHIFT => 195,
141 STARTUP_WAIT => FALSE)
142 -- pragma synthesis_on
143 port map (CLKFB=>CLKFB_IN,
144 CLKIN=>CLKIN_IN,
145 DSSEN=>GND_BIT,
146 PSCLK=>GND_BIT,
147 PSEN=>GND_BIT,
148 PSINCDEC=>GND_BIT,
149 RST=>GND_BIT,
150 CLKDV=>open,
151 CLKFX=>open,
152 CLKFX180=>open,
153 CLK0=>CLK0_BUF,
154 CLK2X=>open,
155 CLK2X180=>open,
156 CLK90=>open,
157 CLK180=>open,
158 CLK270=>open,
159 LOCKED=>open,
160 PSDONE=>open,
161 STATUS=>open);
162
163
164-- hds translate_on
165
166end BEHAVIORAL;
167
168
169
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