source: firmware/FAD/FACT_FAD_lib/hdl/dcm_var_ps_38ns_BEHAVIORAL.vhd@ 18342

Last change on this file since 18342 was 11755, checked in by neise, 13 years ago
reinit of this svn repos .... it was all too messy deleted the old folders and restarted with FACT_FAD_lib only. (well and the testbenches)
File size: 6.3 KB
Line 
1-- Coregen VHDL wrapper file modified by HDL Designer
2
3--------------------------------------------------------------------------------
4-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
5--------------------------------------------------------------------------------
6-- ____ ____
7-- / /\/ /
8-- /___/ \ / Vendor: Xilinx
9-- \ \ \/ Version : 10.1.03
10-- \ \ Application : xaw2vhdl
11-- / / Filename : dcm_var_ps_38ns.vhd
12-- /___/ /\ Timestamp : 08/30/2010 11:48:13
13-- \ \ / \
14-- \___\/\___\
15--
16--Command: xaw2vhdl-st C:/DOKUME~1/dneise/LOKALE~1/Temp/coregen_dneise/coregen/project/dcm_var_ps_38ns.xaw C:/DOKUME~1/dneise/LOKALE~1/Temp/coregen_dneise/coregen/project/dcm_var_ps_38ns
17--Design Name: dcm_var_ps_38ns
18--Device: xc3s700a-4fg400
19--
20-- Module dcm_var_ps_38ns
21-- Written for synthesis tool: Precision
22
23library ieee;
24use ieee.std_logic_1164.ALL;
25use ieee.numeric_std.ALL;
26library UNISIM;
27use UNISIM.Vcomponents.ALL;
28
29entity dcm_var_ps_38ns is
30 port ( CLKIN_IN : in std_logic;
31 PSCLK_IN : in std_logic;
32 PSEN_IN : in std_logic;
33 PSINCDEC_IN : in std_logic;
34 RST_IN : in std_logic;
35 CLK0_OUT : out std_logic;
36 LOCKED_OUT : out std_logic;
37 PSDONE_OUT : out std_logic);
38end dcm_var_ps_38ns;
39
40architecture BEHAVIORAL of dcm_var_ps_38ns is
41
42-- hds translate_off
43
44 attribute CLK_FEEDBACK : string ;
45 attribute CLKDV_DIVIDE : string ;
46 attribute CLKFX_DIVIDE : string ;
47 attribute CLKFX_MULTIPLY : string ;
48 attribute CLKIN_DIVIDE_BY_2 : string ;
49 attribute CLKIN_PERIOD : string ;
50 attribute CLKOUT_PHASE_SHIFT : string ;
51 attribute DESKEW_ADJUST : string ;
52 attribute DFS_FREQUENCY_MODE : string ;
53 attribute DLL_FREQUENCY_MODE : string ;
54 attribute DUTY_CYCLE_CORRECTION : string ;
55 attribute FACTORY_JF : string ;
56 attribute PHASE_SHIFT : string ;
57 attribute STARTUP_WAIT : string ;
58 signal CLKFB_IN : std_logic;
59 signal CLK0_BUF : std_logic;
60 signal GND_BIT : std_logic;
61 component BUFG
62 port ( I : in std_logic;
63 O : out std_logic);
64 end component;
65
66 component DCM_SP
67 -- pragma synthesis_off
68 generic( CLK_FEEDBACK : string := "1X";
69 CLKDV_DIVIDE : real := 2.0;
70 CLKFX_DIVIDE : integer := 1;
71 CLKFX_MULTIPLY : integer := 4;
72 CLKIN_DIVIDE_BY_2 : boolean := FALSE;
73 CLKIN_PERIOD : real := 10.0;
74 CLKOUT_PHASE_SHIFT : string := "NONE";
75 DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
76 DFS_FREQUENCY_MODE : string := "LOW";
77 DLL_FREQUENCY_MODE : string := "LOW";
78 DUTY_CYCLE_CORRECTION : boolean := TRUE;
79 FACTORY_JF : bit_vector := x"C080";
80 PHASE_SHIFT : integer := 0;
81 STARTUP_WAIT : boolean := FALSE;
82 DSS_MODE : string := "NONE");
83 -- pragma synthesis_on
84 port ( CLKIN : in std_logic;
85 CLKFB : in std_logic;
86 RST : in std_logic;
87 PSEN : in std_logic;
88 PSINCDEC : in std_logic;
89 PSCLK : in std_logic;
90 DSSEN : in std_logic;
91 CLK0 : out std_logic;
92 CLK90 : out std_logic;
93 CLK180 : out std_logic;
94 CLK270 : out std_logic;
95 CLKDV : out std_logic;
96 CLK2X : out std_logic;
97 CLK2X180 : out std_logic;
98 CLKFX : out std_logic;
99 CLKFX180 : out std_logic;
100 STATUS : out std_logic_vector (7 downto 0);
101 LOCKED : out std_logic;
102 PSDONE : out std_logic);
103 end component;
104
105 attribute CLK_FEEDBACK of DCM_SP_INST : label is "1X";
106 attribute CLKDV_DIVIDE of DCM_SP_INST : label is "2.0";
107 attribute CLKFX_DIVIDE of DCM_SP_INST : label is "1";
108 attribute CLKFX_MULTIPLY of DCM_SP_INST : label is "4";
109 attribute CLKIN_DIVIDE_BY_2 of DCM_SP_INST : label is "FALSE";
110 attribute CLKIN_PERIOD of DCM_SP_INST : label is "50.000";
111 attribute CLKOUT_PHASE_SHIFT of DCM_SP_INST : label is "VARIABLE";
112 attribute DESKEW_ADJUST of DCM_SP_INST : label is "SYSTEM_SYNCHRONOUS";
113 attribute DFS_FREQUENCY_MODE of DCM_SP_INST : label is "LOW";
114 attribute DLL_FREQUENCY_MODE of DCM_SP_INST : label is "LOW";
115 attribute DUTY_CYCLE_CORRECTION of DCM_SP_INST : label is "TRUE";
116 attribute FACTORY_JF of DCM_SP_INST : label is "C080";
117 attribute PHASE_SHIFT of DCM_SP_INST : label is "0";
118 attribute STARTUP_WAIT of DCM_SP_INST : label is "FALSE";
119
120-- hds translate_on
121
122begin
123
124-- hds translate_off
125
126 GND_BIT <= '0';
127 CLK0_OUT <= CLKFB_IN;
128 CLK0_BUFG_INST : BUFG
129 port map (I=>CLK0_BUF,
130 O=>CLKFB_IN);
131
132 DCM_SP_INST : DCM_SP
133 -- pragma synthesis_off
134 generic map( CLK_FEEDBACK => "1X",
135 CLKDV_DIVIDE => 2.0,
136 CLKFX_DIVIDE => 1,
137 CLKFX_MULTIPLY => 4,
138 CLKIN_DIVIDE_BY_2 => FALSE,
139 CLKIN_PERIOD => 50.000,
140 CLKOUT_PHASE_SHIFT => "VARIABLE",
141 DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
142 DFS_FREQUENCY_MODE => "LOW",
143 DLL_FREQUENCY_MODE => "LOW",
144 DUTY_CYCLE_CORRECTION => TRUE,
145 FACTORY_JF => x"C080",
146 PHASE_SHIFT => 0,
147 STARTUP_WAIT => FALSE)
148 -- pragma synthesis_on
149 port map (CLKFB=>CLKFB_IN,
150 CLKIN=>CLKIN_IN,
151 DSSEN=>GND_BIT,
152 PSCLK=>PSCLK_IN,
153 PSEN=>PSEN_IN,
154 PSINCDEC=>PSINCDEC_IN,
155 RST=>RST_IN,
156 CLKDV=>open,
157 CLKFX=>open,
158 CLKFX180=>open,
159 CLK0=>CLK0_BUF,
160 CLK2X=>open,
161 CLK2X180=>open,
162 CLK90=>open,
163 CLK180=>open,
164 CLK270=>open,
165 LOCKED=>LOCKED_OUT,
166 PSDONE=>PSDONE_OUT,
167 STATUS=>open);
168
169
170-- hds translate_on
171
172end BEHAVIORAL;
173
174
175
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