source: firmware/FAD/FACT_FAD_lib/hdl/debouncer.vhd@ 17370

Last change on this file since 17370 was 11755, checked in by neise, 13 years ago
reinit of this svn repos .... it was all too messy deleted the old folders and restarted with FACT_FAD_lib only. (well and the testbenches)
File size: 2.7 KB
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1----------------------------------------------------------------------------------
2-- Company:
3-- Engineer:
4--
5-- Create Date: 13:42:35 01/08/2010
6-- Design Name:
7-- Module Name: debouncer - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description:
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20-- hds interface_start
21LIBRARY IEEE;
22USE IEEE.STD_LOGIC_1164.ALL;
23USE IEEE.NUMERIC_STD.ALL;
24
25-- -- Uncomment the following library declaration if instantiating
26-- -- any Xilinx primitives in this code.
27-- library UNISIM;
28-- use UNISIM.VComponents.all;
29--
30ENTITY debouncer IS
31 GENERIC(
32 WIDTH : INTEGER := 17
33 );
34 PORT(
35 clk : IN STD_LOGIC;
36 -- rst : in STD_LOGIC;
37 trigger_in : IN STD_LOGIC;
38 trigger_out : OUT STD_LOGIC := '0'
39 );
40
41-- Declarations
42
43END debouncer ;
44-- hds interface_end
45
46architecture Behavioral of debouncer is
47
48 signal counter : STD_LOGIC_VECTOR(WIDTH-1 downto 0) := (others => '0');
49 signal int_trigger : std_logic := '0';
50 signal temp_trig : std_logic_vector(1 downto 0) := "00";
51 signal trigger_flag : std_logic := '0';
52 signal temp_signal : std_logic := '0';
53
54begin
55
56 debounce_proc: process (clk)
57 begin
58-- if (rst = '1') then
59-- counter <= (others => '0');
60-- trigger_out <= '0';
61-- elsif rising_edge(clk) then
62 if rising_edge(clk) then
63 if (trigger_in = '1') then
64 if (unsigned(counter) = 2**WIDTH-1) then
65 int_trigger <= '1';
66 counter <= (others => '1');
67 else
68 counter <= std_logic_vector(unsigned(counter) + to_unsigned(1,WIDTH));
69 end if;
70 else
71 if (unsigned(counter) = 0) then
72 int_trigger <= '0';
73 counter <= (others => '0');
74 else
75 counter <= std_logic_vector(unsigned(counter) - to_unsigned(1,WIDTH));
76 end if;
77 end if;
78 end if;
79 end process debounce_proc;
80
81 shaping_proc : process (clk)
82 begin
83-- if (rst = '1') then
84-- trigger_out <= '0';
85-- trigger_flag <= '0';
86-- temp_signal <= '0';
87-- elsif rising_edge(clk) then
88 if rising_edge(clk) then
89-- temp_trig <= temp_trig(2 downto 0) & trigger_in;
90-- trigger_out <= not temp_trig(3) and temp_trig(2);
91 temp_trig <= temp_trig(0) & int_trigger;
92 temp_signal <= not temp_trig(1) and temp_trig(0);
93 trigger_out <= temp_signal and not trigger_flag;
94 if (int_trigger = '0') then
95 trigger_flag <= '0';
96 end if;
97 if (temp_signal = '1') then
98 trigger_flag <= '1';
99 end if;
100 end if;
101 end process shaping_proc;
102
103
104end Behavioral;
105
106
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