| 1 | ----------------------------------------------------------------------------------
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| 2 | -- Company:
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| 3 | -- Engineer:
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| 4 | --
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| 5 | -- Create Date: 13:42:35 01/08/2010
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| 6 | -- Design Name:
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| 7 | -- Module Name: debouncer - Behavioral
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| 8 | -- Project Name:
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| 9 | -- Target Devices:
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| 10 | -- Tool versions:
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| 11 | -- Description:
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| 12 | --
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| 13 | -- Dependencies:
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| 14 | --
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| 15 | -- Revision:
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| 16 | -- Revision 0.01 - File Created
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| 17 | -- Additional Comments:
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| 18 | --
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| 19 | ----------------------------------------------------------------------------------
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| 20 | -- hds interface_start
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| 21 | LIBRARY IEEE;
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| 22 | USE IEEE.STD_LOGIC_1164.ALL;
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| 23 | USE IEEE.NUMERIC_STD.ALL;
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| 24 |
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| 25 | -- -- Uncomment the following library declaration if instantiating
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| 26 | -- -- any Xilinx primitives in this code.
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| 27 | -- library UNISIM;
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| 28 | -- use UNISIM.VComponents.all;
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| 29 | --
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| 30 | ENTITY debouncer IS
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| 31 | GENERIC(
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| 32 | WIDTH : INTEGER := 17
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| 33 | );
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| 34 | PORT(
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| 35 | clk : IN STD_LOGIC;
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| 36 | -- rst : in STD_LOGIC;
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| 37 | trigger_in : IN STD_LOGIC;
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| 38 | trigger_out : OUT STD_LOGIC := '0'
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| 39 | );
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| 40 |
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| 41 | -- Declarations
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| 42 |
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| 43 | END debouncer ;
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| 44 | -- hds interface_end
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| 45 |
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| 46 | architecture Behavioral of debouncer is
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| 47 |
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| 48 | signal counter : STD_LOGIC_VECTOR(WIDTH-1 downto 0) := (others => '0');
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| 49 | signal int_trigger : std_logic := '0';
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| 50 | signal temp_trig : std_logic_vector(1 downto 0) := "00";
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| 51 | signal trigger_flag : std_logic := '0';
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| 52 | signal temp_signal : std_logic := '0';
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| 53 |
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| 54 | begin
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| 55 |
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| 56 | debounce_proc: process (clk)
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| 57 | begin
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| 58 | -- if (rst = '1') then
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| 59 | -- counter <= (others => '0');
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| 60 | -- trigger_out <= '0';
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| 61 | -- elsif rising_edge(clk) then
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| 62 | if rising_edge(clk) then
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| 63 | if (trigger_in = '1') then
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| 64 | if (unsigned(counter) = 2**WIDTH-1) then
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| 65 | int_trigger <= '1';
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| 66 | counter <= (others => '1');
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| 67 | else
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| 68 | counter <= std_logic_vector(unsigned(counter) + to_unsigned(1,WIDTH));
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| 69 | end if;
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| 70 | else
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| 71 | if (unsigned(counter) = 0) then
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| 72 | int_trigger <= '0';
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| 73 | counter <= (others => '0');
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| 74 | else
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| 75 | counter <= std_logic_vector(unsigned(counter) - to_unsigned(1,WIDTH));
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| 76 | end if;
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| 77 | end if;
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| 78 | end if;
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| 79 | end process debounce_proc;
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| 80 |
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| 81 | shaping_proc : process (clk)
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| 82 | begin
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| 83 | -- if (rst = '1') then
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| 84 | -- trigger_out <= '0';
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| 85 | -- trigger_flag <= '0';
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| 86 | -- temp_signal <= '0';
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| 87 | -- elsif rising_edge(clk) then
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| 88 | if rising_edge(clk) then
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| 89 | -- temp_trig <= temp_trig(2 downto 0) & trigger_in;
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| 90 | -- trigger_out <= not temp_trig(3) and temp_trig(2);
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| 91 | temp_trig <= temp_trig(0) & int_trigger;
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| 92 | temp_signal <= not temp_trig(1) and temp_trig(0);
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| 93 | trigger_out <= temp_signal and not trigger_flag;
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| 94 | if (int_trigger = '0') then
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| 95 | trigger_flag <= '0';
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| 96 | end if;
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| 97 | if (temp_signal = '1') then
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| 98 | trigger_flag <= '1';
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| 99 | end if;
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| 100 | end if;
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| 101 | end process shaping_proc;
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| 102 |
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| 103 |
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| 104 | end Behavioral;
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| 105 |
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| 106 |
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