source: firmware/FAD/FACT_FAD_lib/hdl/drs_pulser.vhd@ 20115

Last change on this file since 20115 was 11755, checked in by neise, 13 years ago
reinit of this svn repos .... it was all too messy deleted the old folders and restarted with FACT_FAD_lib only. (well and the testbenches)
File size: 3.7 KB
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1library IEEE;
2use IEEE.STD_LOGIC_1164.ALL;
3use IEEE.STD_LOGIC_ARITH.ALL;
4use IEEE.std_logic_signed.all;
5
6library fact_fad_lib;
7use fact_fad_lib.fad_definitions.all;
8
9
10ENTITY drs_pulser is
11 port (
12 CLK : in std_logic;
13
14 start_endless_mode : in std_logic;
15 start_read_stop_pos_mode : in std_logic;
16
17 SROUT_in_0 : in std_logic;
18 SROUT_in_1 : in std_logic;
19 SROUT_in_2 : in std_logic;
20 SROUT_in_3 : in std_logic;
21
22 stop_pos : out drs_s_cell_array_type;
23 stop_pos_valid : out std_logic := '0';
24
25 start_srin_write_8b : in std_logic;
26 srin_write_ready : out std_logic := '0';
27 srin_write_ack : out std_logic := '0';
28 srin_data : in std_logic_vector (7 downto 0);
29 SRIN_out : out std_logic := '0';
30
31 RSRLOAD : out std_logic := '0';
32 SRCLK : out std_logic := '0'
33 );
34end drs_pulser;
35
36
37ARCHITECTURE behavior of drs_pulser IS
38
39type state_main_type is (MAIN, SRIN_WRITE_8B, SRIN_WRITE_END, READ_STOP_POS, ENDLESS_MODE);
40signal state_main : state_main_type := MAIN;
41signal stop_pos_cntr, wait_cntr : integer range 0 to 31 := 0;
42
43signal stop_pos_int : drs_s_cell_array_type;
44signal RSRLOAD_EN, SRCLK_EN : std_logic := '0';
45
46signal srin_cntr : integer range 0 to 7 := 1;
47
48begin
49
50
51 main_proc: process (clk) begin
52
53 RSRLOAD <= (clk and RSRLOAD_EN);
54 SRCLK <= (clk and SRCLK_EN);
55
56 if rising_edge(clk) then
57 case state_main is
58 when MAIN =>
59 if (start_srin_write_8b = '1') then
60 srin_write_ready <= '0';
61 srin_write_ack <= '1';
62 srin_cntr <= 0;
63 --SRCLK_EN <= '1';
64 state_main <= SRIN_WRITE_8B;
65 end if;
66 if (start_read_stop_pos_mode = '1') then
67 RSRLOAD_EN <= '1';
68 stop_pos_valid <= '0';
69 state_main <= READ_STOP_POS;
70 end if;
71 if (start_endless_mode = '1') then
72 RSRLOAD_EN <= '1';
73 state_main <= ENDLESS_MODE;
74 end if;
75
76 when SRIN_WRITE_8B =>
77 SRCLK_EN <= '1';
78 srin_out <= srin_data (7 - srin_cntr);
79 if (srin_cntr = 7) then
80 --SRCLK_EN <= '0';
81 state_main <= SRIN_WRITE_END;
82 else
83 srin_cntr <= srin_cntr + 1;
84 end if;
85 when SRIN_WRITE_END =>
86 SRCLK_EN <= '0';
87 srin_out <= '0';
88 srin_write_ready <= '1';
89 srin_write_ack <= '0';
90 state_main <= MAIN;
91
92
93 when ENDLESS_MODE =>
94 RSRLOAD_EN <= '0';
95 if (wait_cntr = 3) then
96 SRCLK_EN <= '1';
97 else
98 wait_cntr <= wait_cntr + 1;
99 end if;
100 if (start_endless_mode = '0') then
101 SRCLK_EN <= '0';
102 wait_cntr <= 0;
103 state_main <= MAIN;
104 end if;
105
106 when READ_STOP_POS =>
107 RSRLOAD_EN <= '0';
108 if (stop_pos_cntr = 10) then
109 stop_pos (0) <= stop_pos_int (0);
110 stop_pos (1) <= stop_pos_int (1);
111 stop_pos (2) <= stop_pos_int (2);
112 stop_pos (3) <= stop_pos_int (3);
113 stop_pos_valid <= '1';
114 stop_pos_cntr <= 0;
115 SRCLK_EN <= '0';
116 state_main <= MAIN;
117 else
118 SRCLK_EN <= '1';
119 stop_pos_int (0) <= stop_pos_int (0) (8 downto 0) & SROUT_in_0;
120 stop_pos_int (1) <= stop_pos_int (1) (8 downto 0) & SROUT_in_1;
121 stop_pos_int (2) <= stop_pos_int (2) (8 downto 0) & SROUT_in_2;
122 stop_pos_int (3) <= stop_pos_int (3) (8 downto 0) & SROUT_in_3;
123 stop_pos_cntr <= stop_pos_cntr + 1;
124 end if;
125
126 end case; -- state_main
127 end if;
128
129 end process main_proc;
130
131end behavior;
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