source: firmware/FAD/FACT_FAD_lib/hdl/fad_board_struct.vhd@ 19366

Last change on this file since 19366 was 11801, checked in by neise, 14 years ago
hex: v214; dec: v220. FAD operates with socket 0 and 1 only. (TX MEM 60kb)
File size: 14.0 KB
Line 
1-- VHDL Entity FACT_FAD_lib.FAD_Board.symbol
2--
3-- Created:
4-- by - daqct3.UNKNOWN (IHP110)
5-- at - 17:22:06 05.08.2011
6--
7-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
8--
9LIBRARY ieee;
10USE ieee.std_logic_1164.all;
11USE ieee.std_logic_arith.all;
12
13ENTITY FAD_Board IS
14 PORT(
15 A0_D : IN std_logic_vector (11 DOWNTO 0);
16 A1_D : IN std_logic_vector (11 DOWNTO 0);
17 A2_D : IN std_logic_vector (11 DOWNTO 0);
18 A3_D : IN std_logic_vector (11 DOWNTO 0);
19 A_OTR : IN std_logic_vector (3 DOWNTO 0);
20 D0_SROUT : IN std_logic;
21 D1_SROUT : IN std_logic;
22 D2_SROUT : IN std_logic;
23 D3_SROUT : IN std_logic;
24 D_PLLLCK : IN std_logic_vector (3 DOWNTO 0);
25 D_T_in : IN std_logic_vector (1 DOWNTO 0);
26 LINE : IN std_logic_vector ( 5 DOWNTO 0 );
27 REFCLK : IN std_logic;
28 RS485_E_DI : IN std_logic;
29 TRG : IN STD_LOGIC;
30 W_INT : IN std_logic;
31 X_50M : IN STD_LOGIC;
32 A0_T : OUT std_logic_vector (7 DOWNTO 0) := (others => '0');
33 A1_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
34 AMBER_LED : OUT std_logic;
35 A_CLK : OUT std_logic_vector (3 DOWNTO 0);
36 DAC_CS : OUT std_logic;
37 DENABLE : OUT std_logic := '0';
38 DSRCLK : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
39 DWRITE : OUT std_logic := '0';
40 D_A : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
41 D_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
42 D_T2 : OUT std_logic_vector (1 DOWNTO 0) := (others => '0');
43 EE_CS : OUT std_logic;
44 GREEN_LED : OUT std_logic;
45 MOSI : OUT std_logic := '0';
46 OE_ADC : OUT STD_LOGIC;
47 RED_LED : OUT std_logic;
48 RS485_C_DE : OUT std_logic;
49 RS485_C_DO : OUT std_logic;
50 RS485_C_RE : OUT std_logic;
51 RS485_E_DE : OUT std_logic;
52 RS485_E_DO : OUT std_logic;
53 RS485_E_RE : OUT std_logic;
54 RSRLOAD : OUT std_logic := '0';
55 SRIN : OUT std_logic := '0';
56 S_CLK : OUT std_logic;
57 TCS : OUT std_logic_vector (3 DOWNTO 0);
58 TRG_V : OUT std_logic := '0';
59 W_A : OUT std_logic_vector (9 DOWNTO 0);
60 W_CS : OUT std_logic := '1';
61 W_RD : OUT std_logic := '1';
62 W_RES : OUT std_logic := '1';
63 W_T : OUT std_logic_vector ( 3 DOWNTO 0 ) := (others => '0');
64 W_WR : OUT std_logic := '1';
65 MISO : INOUT std_logic;
66 W_D : INOUT std_logic_vector (15 DOWNTO 0)
67 );
68
69-- Declarations
70
71END FAD_Board ;
72
73--
74-- VHDL Architecture FACT_FAD_lib.FAD_Board.struct
75--
76-- Created:
77-- by - daqct3.UNKNOWN (IHP110)
78-- at - 17:22:07 05.08.2011
79--
80-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
81--
82LIBRARY ieee;
83USE ieee.std_logic_1164.all;
84USE ieee.std_logic_arith.all;
85USE IEEE.NUMERIC_STD.all;
86USE ieee.std_logic_unsigned.all;
87
88LIBRARY FACT_FAD_lib;
89USE FACT_FAD_lib.fad_definitions.all;
90
91LIBRARY FACT_FAD_lib;
92
93ARCHITECTURE struct OF FAD_Board IS
94
95 -- Architecture declarations
96
97 -- Internal signal declarations
98 SIGNAL ADC_CLK : std_logic;
99 SIGNAL CLK_50 : std_logic;
100 -- for debugging
101 SIGNAL DG_state : std_logic_vector(7 DOWNTO 0);
102 SIGNAL SRCLK : std_logic := '0';
103 SIGNAL adc_data_array : adc_data_array_type;
104 SIGNAL alarm_refclk_too_high : std_logic := '0';
105 SIGNAL alarm_refclk_too_low : std_logic := '0';
106 SIGNAL board_id : std_logic_vector(3 DOWNTO 0);
107 SIGNAL counter_result : std_logic_vector(11 DOWNTO 0) := (others => '0');
108 SIGNAL crate_id : std_logic_vector(1 DOWNTO 0);
109 SIGNAL dac_cs1 : std_logic;
110 SIGNAL debug_data_ram_empty : std_logic;
111 SIGNAL debug_data_valid : std_logic;
112 SIGNAL led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
113 SIGNAL mem_manager_state : std_logic_vector(3 DOWNTO 0); -- state is encoded here ... useful for debugging.
114 SIGNAL mosi1 : std_logic;
115 SIGNAL sclk : std_logic;
116 SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0);
117 SIGNAL socket_tx_free_out : std_logic_vector(16 DOWNTO 0); -- 17bit value .. that's true
118 SIGNAL trigger_veto : std_logic := '1';
119 SIGNAL w5300_state : std_logic_vector(7 DOWNTO 0); -- state is encoded here ... useful for debugging.
120
121 -- Implicit buffer signal declarations
122 SIGNAL TRG_V_internal : std_logic;
123
124
125 -- Component Declarations
126 COMPONENT FAD_main
127 GENERIC (
128 RAMADDRWIDTH64b : integer := 12
129 );
130 PORT (
131 CLK : IN std_logic ;
132 D_T_in : IN std_logic_vector (1 DOWNTO 0);
133 FTM_RS485_rx_d : IN std_logic ;
134 SROUT_in_0 : IN std_logic ;
135 SROUT_in_1 : IN std_logic ;
136 SROUT_in_2 : IN std_logic ;
137 SROUT_in_3 : IN std_logic ;
138 adc_data_array : IN adc_data_array_type ;
139 adc_otr_array : IN std_logic_vector (3 DOWNTO 0);
140 board_id : IN std_logic_vector (3 DOWNTO 0);
141 crate_id : IN std_logic_vector (1 DOWNTO 0);
142 drs_refclk_in : IN std_logic ; -- used TO check if DRS REFCLK exsists, if not DENABLE inhibit
143 plllock_in : IN std_logic_vector (3 DOWNTO 0); -- high level, if dominowave is running and DRS PLL locked
144 trigger : IN std_logic ;
145 wiz_int : IN std_logic ;
146 ADC_CLK : OUT std_logic ;
147 CLK_25_PS : OUT std_logic ;
148 CLK_50 : OUT std_logic ;
149 -- for debugging
150 DG_state : OUT std_logic_vector (7 DOWNTO 0);
151 FTM_RS485_rx_en : OUT std_logic ;
152 FTM_RS485_tx_d : OUT std_logic ;
153 FTM_RS485_tx_en : OUT std_logic ;
154 RSRLOAD : OUT std_logic := '0';
155 SRCLK : OUT std_logic := '0';
156 SRIN_out : OUT std_logic := '0';
157 adc_oeb : OUT std_logic := '1';
158 alarm_refclk_too_high : OUT std_logic ;
159 alarm_refclk_too_low : OUT std_logic ;
160 amber : OUT std_logic ;
161 counter_result : OUT std_logic_vector (11 DOWNTO 0);
162 dac_cs : OUT std_logic ;
163 debug_data_ram_empty : OUT std_logic ;
164 debug_data_valid : OUT std_logic ;
165 denable : OUT std_logic := '0'; -- default domino wave off
166 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
167 drs_dwrite : OUT std_logic := '1';
168 green : OUT std_logic ;
169 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
170 mem_manager_state : OUT std_logic_vector (3 DOWNTO 0); -- state is encoded here ... useful for debugging.
171 mosi : OUT std_logic := '0';
172 red : OUT std_logic ;
173 sclk : OUT std_logic ;
174 sensor_cs : OUT std_logic_vector (3 DOWNTO 0);
175 socket_tx_free_out : OUT std_logic_vector (16 DOWNTO 0); -- 17bit value .. that's true
176 trigger_veto : OUT std_logic := '1';
177 w5300_state : OUT std_logic_vector (7 DOWNTO 0); -- state is encoded here ... useful for debugging.
178 wiz_addr : OUT std_logic_vector (9 DOWNTO 0);
179 wiz_cs : OUT std_logic := '1';
180 wiz_rd : OUT std_logic := '1';
181 wiz_reset : OUT std_logic := '1';
182 wiz_wr : OUT std_logic := '1';
183 sio : INOUT std_logic ;
184 wiz_data : INOUT std_logic_vector (15 DOWNTO 0)
185 );
186 END COMPONENT;
187
188 -- Optional embedded configurations
189 -- pragma synthesis_off
190 FOR ALL : FAD_main USE ENTITY FACT_FAD_lib.FAD_main;
191 -- pragma synthesis_on
192
193
194BEGIN
195 -- Architecture concurrent statements
196 -- HDL Embedded Text Block 1 SRCLK
197 DSRCLK <= ( SRCLK, SRCLK,SRCLK,SRCLK);
198
199 -- HDL Embedded Text Block 2 ADC_CLK
200 A_CLK <= (
201 ADC_CLK,
202 ADC_CLK,
203 ADC_CLK,
204 ADC_CLK
205 );
206
207 -- HDL Embedded Text Block 3 ADC_DATA
208 adc_data_array <= ( A0_D, A1_D, A2_D, A3_D );
209
210 -- HDL Embedded Text Block 4 eb_ID
211 -- hard-wired IDs
212 board_id <= LINE(5 downto 2);
213 crate_id <= LINE(1 downto 0);
214
215 -- HDL Embedded Text Block 9 eb3
216 -- testpins D_T2 are used as MAX3485 outputs.
217
218 --D_T <= (others => '0');
219 D_T <= w5300_state;
220 --D_T2(0) <= debug_data_valid;
221 D_T2(0) <= debug_data_ram_empty;
222 --D_T2(1) <= socket_tx_free_out(16);
223
224 D_T2(1) <= TRG_V_internal;
225 --D_T2 <= ( others => '0' );
226
227
228 A0_T <= (others => '0');
229 A1_T <= (others => '1');
230
231
232 --A0_T <= DG_state;
233 W_T(3 downto 0) <= mem_manager_state;
234 --A1_T(7 downto 4) <= "1100";
235
236 --A0_T <= socket_tx_free_out(7 downto 0);
237 --A0_T <= spi_debug_16bit(7 downto 0);
238 --A1_T <= spi_debug_16bit(15 downto 8);
239 --A1_T <= socket_tx_free_out(15 downto 8);
240
241 -- check SPI interfac
242 --A1_T(7) <= sclk;
243 --A1_T(6) <= MISO;
244 --A1_T(5) <= mosi1;
245
246 --A1_T(4) <= dac_cs1;
247 --A1_T( 3 downto 0) <= sensor_cs;
248
249
250 --D_T(3 downto 0) <= counter_result ( 11 downto 8);
251 --D_T(4) <= alarm_refclk_too_low;
252 --D_T(5) <= alarm_refclk_too_high;
253 --D_T(6) <= '0';
254 --D_T(7) <= '0';
255
256
257
258 -- additional MAX3485 is switched to shutdown mode
259 RS485_C_RE <= '1'; --inverted logic
260 RS485_C_DE <= '0';
261 RS485_C_DO <= '0';
262 -- MAX3485 receiver out pit is fed out... should be HIGH-Z
263
264
265 -- EEPROM is not used on FAD. CS is always high.
266 EE_CS <= '1';
267
268
269 -- ModuleWare code(v1.9) for instance 'I0' of 'assignment'
270 DAC_CS <= dac_cs1;
271
272 -- ModuleWare code(v1.9) for instance 'I1' of 'assignment'
273 TCS <= sensor_cs;
274
275 -- ModuleWare code(v1.9) for instance 'I2' of 'assignment'
276 S_CLK <= sclk;
277
278 -- ModuleWare code(v1.9) for instance 'I3' of 'assignment'
279 MOSI <= mosi1;
280
281 -- ModuleWare code(v1.9) for instance 'I4' of 'assignment'
282 TRG_V_internal <= trigger_veto;
283
284 -- Instance port mappings.
285 I_board_main : FAD_main
286 GENERIC MAP (
287 RAMADDRWIDTH64b => LOG2_OF_RAM_SIZE_64B
288 )
289 PORT MAP (
290 CLK => X_50M,
291 D_T_in => D_T_in,
292 FTM_RS485_rx_d => RS485_E_DI,
293 SROUT_in_0 => D0_SROUT,
294 SROUT_in_1 => D1_SROUT,
295 SROUT_in_2 => D2_SROUT,
296 SROUT_in_3 => D3_SROUT,
297 adc_data_array => adc_data_array,
298 adc_otr_array => A_OTR,
299 board_id => board_id,
300 crate_id => crate_id,
301 drs_refclk_in => REFCLK,
302 plllock_in => D_PLLLCK,
303 trigger => TRG,
304 wiz_int => W_INT,
305 ADC_CLK => ADC_CLK,
306 CLK_25_PS => OPEN,
307 CLK_50 => CLK_50,
308 DG_state => DG_state,
309 FTM_RS485_rx_en => RS485_E_RE,
310 FTM_RS485_tx_d => RS485_E_DO,
311 FTM_RS485_tx_en => RS485_E_DE,
312 RSRLOAD => RSRLOAD,
313 SRCLK => SRCLK,
314 SRIN_out => SRIN,
315 adc_oeb => OE_ADC,
316 alarm_refclk_too_high => alarm_refclk_too_high,
317 alarm_refclk_too_low => alarm_refclk_too_low,
318 amber => AMBER_LED,
319 counter_result => counter_result,
320 dac_cs => dac_cs1,
321 debug_data_ram_empty => debug_data_ram_empty,
322 debug_data_valid => debug_data_valid,
323 denable => DENABLE,
324 drs_channel_id => D_A,
325 drs_dwrite => DWRITE,
326 green => GREEN_LED,
327 led => led,
328 mem_manager_state => mem_manager_state,
329 mosi => mosi1,
330 red => RED_LED,
331 sclk => sclk,
332 sensor_cs => sensor_cs,
333 socket_tx_free_out => socket_tx_free_out,
334 trigger_veto => trigger_veto,
335 w5300_state => w5300_state,
336 wiz_addr => W_A,
337 wiz_cs => W_CS,
338 wiz_rd => W_RD,
339 wiz_reset => W_RES,
340 wiz_wr => W_WR,
341 sio => MISO,
342 wiz_data => W_D
343 );
344
345 -- Implicit buffered output assignments
346 TRG_V <= TRG_V_internal;
347
348END struct;
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