source: firmware/FAD/FACT_FAD_lib/hdl/fad_main_struct.vhd@ 19695

Last change on this file since 19695 was 11801, checked in by neise, 14 years ago
hex: v214; dec: v220. FAD operates with socket 0 and 1 only. (TX MEM 60kb)
File size: 50.9 KB
Line 
1-- VHDL Entity FACT_FAD_lib.FAD_main.symbol
2--
3-- Created:
4-- by - daqct3.UNKNOWN (IHP110)
5-- at - 17:22:05 05.08.2011
6--
7-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
8--
9LIBRARY ieee;
10USE ieee.std_logic_1164.all;
11USE ieee.std_logic_arith.all;
12LIBRARY FACT_FAD_lib;
13USE FACT_FAD_lib.fad_definitions.all;
14
15ENTITY FAD_main IS
16 GENERIC(
17 RAMADDRWIDTH64b : integer := 12
18 );
19 PORT(
20 CLK : IN std_logic;
21 D_T_in : IN std_logic_vector (1 DOWNTO 0);
22 FTM_RS485_rx_d : IN std_logic;
23 SROUT_in_0 : IN std_logic;
24 SROUT_in_1 : IN std_logic;
25 SROUT_in_2 : IN std_logic;
26 SROUT_in_3 : IN std_logic;
27 adc_data_array : IN adc_data_array_type;
28 adc_otr_array : IN std_logic_vector (3 DOWNTO 0);
29 board_id : IN std_logic_vector (3 DOWNTO 0);
30 crate_id : IN std_logic_vector (1 DOWNTO 0);
31 drs_refclk_in : IN std_logic; -- used to check if DRS REFCLK exsists, if not DENABLE inhibit
32 plllock_in : IN std_logic_vector (3 DOWNTO 0); -- high level, if dominowave is running and DRS PLL locked
33 trigger : IN std_logic;
34 wiz_int : IN std_logic;
35 ADC_CLK : OUT std_logic;
36 CLK_25_PS : OUT std_logic;
37 CLK_50 : OUT std_logic;
38 -- for debugging
39 DG_state : OUT std_logic_vector (7 DOWNTO 0);
40 FTM_RS485_rx_en : OUT std_logic;
41 FTM_RS485_tx_d : OUT std_logic;
42 FTM_RS485_tx_en : OUT std_logic;
43 RSRLOAD : OUT std_logic := '0';
44 SRCLK : OUT std_logic := '0';
45 SRIN_out : OUT std_logic := '0';
46 adc_oeb : OUT std_logic := '1';
47 alarm_refclk_too_high : OUT std_logic;
48 alarm_refclk_too_low : OUT std_logic;
49 amber : OUT std_logic;
50 counter_result : OUT std_logic_vector (11 DOWNTO 0);
51 dac_cs : OUT std_logic;
52 debug_data_ram_empty : OUT std_logic;
53 debug_data_valid : OUT std_logic;
54 denable : OUT std_logic := '0'; -- default domino wave off
55 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
56 drs_dwrite : OUT std_logic := '1';
57 green : OUT std_logic;
58 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
59 mem_manager_state : OUT std_logic_vector (3 DOWNTO 0); -- state is encoded here ... useful for debugging.
60 mosi : OUT std_logic := '0';
61 red : OUT std_logic;
62 sclk : OUT std_logic;
63 sensor_cs : OUT std_logic_vector (3 DOWNTO 0);
64 socket_tx_free_out : OUT std_logic_vector (16 DOWNTO 0); -- 17bit value .. that's true
65 trigger_veto : OUT std_logic := '1';
66 w5300_state : OUT std_logic_vector (7 DOWNTO 0); -- state is encoded here ... useful for debugging.
67 wiz_addr : OUT std_logic_vector (9 DOWNTO 0);
68 wiz_cs : OUT std_logic := '1';
69 wiz_rd : OUT std_logic := '1';
70 wiz_reset : OUT std_logic := '1';
71 wiz_wr : OUT std_logic := '1';
72 sio : INOUT std_logic;
73 wiz_data : INOUT std_logic_vector (15 DOWNTO 0)
74 );
75
76-- Declarations
77
78END FAD_main ;
79
80--
81-- VHDL Architecture FACT_FAD_lib.FAD_main.struct
82--
83-- Created:
84-- by - daqct3.UNKNOWN (IHP110)
85-- at - 17:22:06 05.08.2011
86--
87-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
88--
89library ieee;
90use ieee.std_logic_1164.all;
91use IEEE.STD_LOGIC_ARITH.all;
92use ieee.STD_LOGIC_UNSIGNED.all;
93
94library fact_fad_lib;
95use fact_fad_lib.fad_definitions.all;
96
97library UNISIM;
98--use UNISIM.VComponents.all;
99USE IEEE.NUMERIC_STD.all;
100USE IEEE.std_logic_signed.all;
101USE fact_fad_lib.fad_rs485_constants.all;
102LIBRARY hds_package_library;
103USE hds_package_library.random_generators.all;
104
105LIBRARY FACT_FAD_lib;
106
107ARCHITECTURE struct OF FAD_main IS
108
109 -- Architecture declarations
110
111 -- Internal signal declarations
112 SIGNAL CLK_25 : std_logic;
113 SIGNAL DCM_PS_status : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
114 SIGNAL DCM_locked_status : std_logic;
115 SIGNAL DCM_ready_status : std_logic;
116 --
117
118-- EVT HEADER - part 2 --> FTM trigger informaton, comes in late ...
119-- during EVT header wrinting, this field is left out ... and only written into event header,
120-- when the DRS chip were read out already.
121 SIGNAL FTM_RS485_ready : std_logic;
122 SIGNAL I_really_want_dwrite : STD_LOGIC;
123 SIGNAL SRCLK1 : std_logic := '0';
124 SIGNAL adc_clk_en : std_logic;
125 SIGNAL adc_data_array_int : adc_data_array_type;
126 SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0);
127 SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0);
128 SIGNAL busy_enable : std_logic := '1';
129 SIGNAL busy_high_active : std_logic;
130 SIGNAL busy_manual : std_logic;
131 SIGNAL c_trigger_enable : std_logic := '0';
132 SIGNAL c_trigger_mult : std_logic_vector(15 DOWNTO 0);
133 SIGNAL cont_trigger : std_logic;
134 SIGNAL current_dac_array : dac_array_type := ( others => 0);
135 SIGNAL dac_setting : dac_array_type := DEFAULT_DAC; --<<-- default defined in fad_definitions.vhd
136 SIGNAL data_out : std_logic_vector(63 DOWNTO 0);
137 SIGNAL data_ram_empty : std_logic;
138 SIGNAL data_valid_ack : std_logic := '0';
139 SIGNAL denable_prim : std_logic := '0'; -- default domino wave off
140 SIGNAL denable_sig : std_logic := '0'; -- default domino wave off
141 SIGNAL dg_config_done : std_logic;
142 SIGNAL dg_start_config : std_logic := '0';
143 SIGNAL din1 : std_logic := '0'; -- default domino wave off
144 SIGNAL dna : STD_LOGIC_VECTOR(63 DOWNTO 0) := (others => '0');
145 SIGNAL dout : STD_LOGIC;
146 SIGNAL dout0 : STD_LOGIC;
147 SIGNAL dout1 : STD_LOGIC;
148 SIGNAL dout2 : STD_LOGIC;
149 SIGNAL dout3 : STD_LOGIC;
150 SIGNAL dout4 : STD_LOGIC;
151 SIGNAL dout5 : std_logic;
152 SIGNAL dout6 : std_logic;
153 SIGNAL dout7 : std_logic;
154 SIGNAL dout8 : std_logic;
155 SIGNAL drs_clk_en : std_logic := '0';
156 SIGNAL drs_read_s_cell : std_logic := '0';
157 SIGNAL drs_read_s_cell_ready : std_logic;
158 -- --
159-- drs_dwrite : out std_logic := '1';
160 SIGNAL drs_readout_ready : std_logic := '0';
161 SIGNAL drs_readout_ready_ack : std_logic;
162 SIGNAL drs_readout_started : std_logic;
163 SIGNAL drs_s_cell_array : drs_s_cell_array_type;
164 SIGNAL drs_srin_data : std_logic_vector(7 DOWNTO 0) := (others => '0');
165 SIGNAL dwrite_enable_w5300 : std_logic := '1';
166 SIGNAL dwrite_global_enable : std_logic := '1';
167 SIGNAL dwrite_trigger_manager : std_logic := '1';
168 SIGNAL enable_i : std_logic;
169 SIGNAL enabled_trigger_or_s_trigger : std_logic;
170 SIGNAL is_idle : std_logic;
171 SIGNAL memory_manager_config_start : std_logic := '0';
172 SIGNAL memory_manager_config_valid : std_logic;
173 SIGNAL not_busy_enable : STD_LOGIC;
174 SIGNAL package_length : std_logic_vector(15 DOWNTO 0);
175 SIGNAL ps_direction : std_logic := '1'; -- default phase shift upwards
176 SIGNAL ps_do_phase_shift : std_logic := '0'; --pulse this to phase shift once
177 SIGNAL ps_reset : std_logic := '0'; -- pulse this to reset the variable phase shift
178 SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0);
179 SIGNAL ram_data : std_logic_vector(15 DOWNTO 0);
180 SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0);
181 SIGNAL ram_write_ea : std_logic;
182 SIGNAL ram_write_ready : std_logic := '0';
183 SIGNAL ready : STD_LOGIC := '0';
184 SIGNAL rec_timeout_occured : std_logic := '0';
185 SIGNAL reset_synch_i : std_logic;
186 SIGNAL reset_trigger_id : std_logic := '0';
187 SIGNAL roi_max : roi_max_type;
188 SIGNAL roi_setting : roi_array_type;
189 SIGNAL rs465_data : std_logic_vector(55 DOWNTO 0); --7 byte
190 -- EVT HEADER - part 6
191 SIGNAL runnumber : std_logic_vector(31 DOWNTO 0);
192 SIGNAL s_trigger : std_logic;
193 SIGNAL sclk_enable : std_logic;
194 SIGNAL sensor_array : sensor_array_type;
195 SIGNAL sensor_ready : std_logic;
196 SIGNAL socket_send_mode_out : std_logic;
197 SIGNAL socks_connected : std_logic;
198 SIGNAL socks_waiting : std_logic;
199 SIGNAL software_trigger_in : std_logic;
200 SIGNAL spi_interface_config_start : std_logic := '0';
201 SIGNAL spi_interface_config_valid : std_logic;
202 SIGNAL srclk_enable : std_logic := '0';
203 SIGNAL srin_write_ack : std_logic := '0';
204 SIGNAL srin_write_ready : std_logic := '0';
205 SIGNAL start_srin_write_8b : std_logic;
206 SIGNAL time : std_logic_vector(31 DOWNTO 0);
207 SIGNAL trig_veto : std_logic;
208 SIGNAL trigger1 : std_logic;
209 SIGNAL trigger_enable : std_logic;
210 SIGNAL trigger_id : std_logic_vector(31 DOWNTO 0);
211 SIGNAL trigger_or_s_trigger : std_logic;
212 SIGNAL trigger_out : std_logic;
213 SIGNAL trigger_veto1 : std_logic := '1';
214 SIGNAL wiz_number_of_channels : std_logic_vector(3 DOWNTO 0) := (others => '0');
215 SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0');
216 SIGNAL wiz_reset1 : std_logic := '1';
217 SIGNAL wiz_write_ea : std_logic := '0';
218 SIGNAL wiz_write_end : std_logic := '0';
219 SIGNAL wiz_write_header : std_logic := '0';
220 SIGNAL wiz_write_length : std_logic_vector(16 DOWNTO 0) := (others => '0');
221 SIGNAL write_ea : std_logic_vector(0 DOWNTO 0) := "0";
222
223 -- Implicit buffer signal declarations
224 SIGNAL CLK_25_PS_internal : std_logic;
225 SIGNAL CLK_50_internal : std_logic;
226 SIGNAL alarm_refclk_too_high_internal : std_logic;
227 SIGNAL alarm_refclk_too_low_internal : std_logic;
228 SIGNAL counter_result_internal : std_logic_vector (11 DOWNTO 0);
229
230
231 -- ModuleWare signal declarations(v1.9) for instance 'U_0' of 'split'
232 SIGNAL mw_U_0temp_din : std_logic_vector(3 DOWNTO 0);
233
234 -- Component Declarations
235 COMPONENT FAD_rs485_receiver
236 GENERIC (
237 -- defined in fad_rs485_definitions.fad_rs485_constants
238 RX_BYTES : integer := RS485_MESSAGE_LEN_BYTES; -- no. of bytes to receive
239 RX_WIDTH : integer := RS485_MESSAGE_LEN_BYTES * 8 -- no. of bits to receive
240 );
241 PORT (
242 rec_clk : IN std_logic;
243 rec_start : IN std_logic;
244 rx_d : IN std_logic;
245 rec_dout : OUT std_logic_vector (RX_WIDTH - 1 DOWNTO 0) := (others => '0');
246 rec_timeout_occured : OUT std_logic := '0';
247 rec_valid : OUT std_logic := '0';
248 rx_en : OUT std_logic;
249 tx_d : OUT std_logic;
250 tx_en : OUT std_logic
251 );
252 END COMPONENT;
253 COMPONENT REFCLK_counter
254 PORT (
255 clk : IN std_logic;
256 refclk_in : IN std_logic;
257 alarm_refclk_too_high : OUT std_logic := '0';
258 alarm_refclk_too_low : OUT std_logic := '0';
259 counter_result : OUT std_logic_vector (11 DOWNTO 0) := (others => '0')
260 );
261 END COMPONENT;
262 COMPONENT adc_buffer
263 PORT (
264 adc_data_array : IN adc_data_array_type;
265 adc_otr_array : IN std_logic_vector (3 DOWNTO 0);
266 clk_ps : IN std_logic;
267 adc_data_array_int : OUT adc_data_array_type;
268 adc_otr : OUT std_logic_vector (3 DOWNTO 0)
269 );
270 END COMPONENT;
271 COMPONENT clock_generator_var_ps
272 PORT (
273 CLK : IN std_logic ;
274 RST_IN : IN std_logic ;
275 direction : IN std_logic ;
276 do_shift : IN std_logic ;
277 CLK_25 : OUT std_logic ;
278 CLK_25_PS : OUT std_logic ;
279 CLK_50 : OUT std_logic ;
280 locked_status_o : OUT std_logic ;
281 offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
282 ready_status_o : OUT std_logic
283 );
284 END COMPONENT;
285 COMPONENT continous_pulser
286 GENERIC (
287 MINIMAL_TRIGGER_WAIT_TIME : integer := 250000;
288 TRIGGER_WIDTH : integer := 5
289 );
290 PORT (
291 CLK : IN std_logic;
292 enable : IN std_logic;
293 multiplier : IN std_logic_vector (15 DOWNTO 0);
294 trigger : OUT std_logic
295 );
296 END COMPONENT;
297 COMPONENT dataRAM_64b_16b_width14_5
298 PORT (
299 clka : IN std_logic ;
300 dina : IN std_logic_VECTOR (63 DOWNTO 0);
301 addra : IN std_logic_VECTOR (14 DOWNTO 0);
302 wea : IN std_logic_VECTOR (0 DOWNTO 0);
303 clkb : IN std_logic ;
304 addrb : IN std_logic_VECTOR (16 DOWNTO 0);
305 doutb : OUT std_logic_VECTOR (15 DOWNTO 0)
306 );
307 END COMPONENT;
308 COMPONENT data_generator
309 GENERIC (
310 RAM_ADDR_WIDTH : integer := 12
311 );
312 PORT (
313 -- for debugging
314 state : OUT std_logic_vector (7 DOWNTO 0);
315 is_idle : OUT std_logic ;
316 clk : IN std_logic ; -- CLK_25.
317 data_out : OUT std_logic_vector (63 DOWNTO 0);
318 addr_out : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
319 dataRAM_write_ea_o : OUT std_logic_vector (0 DOWNTO 0) := "0";
320 ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
321 ram_write_ea : IN std_logic ;
322 ram_write_ready : OUT std_logic := '0';
323 roi_array : IN roi_array_type ;
324 roi_max : IN roi_max_type ;
325 sensor_array : IN sensor_array_type ;
326 sensor_ready : IN std_logic ;
327 dac_array : IN dac_array_type ;
328 config_start : IN std_logic ;
329 config_done : OUT std_logic := '0';
330 -- EVT HEADER - part 1
331 package_length : IN std_logic_vector (15 DOWNTO 0);
332 pll_lock : IN std_logic_vector ( 3 DOWNTO 0);
333 dwrite_enable_in : IN std_logic ;
334 denable_enable_in : IN std_logic ;
335 busy_enable_in : IN std_logic ;
336 trigger_enable_in : IN std_logic ;
337 cont_trigger_en_in : IN std_logic ;
338 socket_send_mode_in : IN std_logic ;
339 busy_manual_in : IN std_logic ;
340 -- EVT HEADER - part 2 --> FTM trigger informaton, comes in late ...
341 -- during EVT header wrinting, this field is left out ... and only written into event header,
342 -- when the DRS chip were read out already.
343 FTM_RS485_ready : IN std_logic ;
344 FTM_trigger_info : IN std_logic_vector (55 DOWNTO 0); --7 byte
345 FTM_receiver_status : IN std_logic ;
346 -- EVT HEADER - part 3
347 fad_event_counter : IN std_logic_vector (31 DOWNTO 0);
348 refclk_counter : IN std_logic_vector (11 DOWNTO 0);
349 refclk_too_high : IN std_logic ;
350 refclk_too_low : IN std_logic ;
351 -- EVT HEADER - part 4
352 board_id : IN std_logic_vector (3 DOWNTO 0);
353 crate_id : IN std_logic_vector (1 DOWNTO 0);
354 DCM_PS_status : IN std_logic_vector (7 DOWNTO 0);
355 DCM_locked_status : IN std_logic ;
356 DCM_ready_status : IN std_logic ;
357 SPI_SCLK_enable_status : IN std_logic ;
358 TRG_GEN_div : IN std_logic_vector (15 DOWNTO 0);
359 -- EVT HEADER - part 5
360 dna : IN std_logic_vector (63 DOWNTO 0);
361 -- EVT HEADER - part 6
362 runnumber : IN std_logic_vector (31 DOWNTO 0);
363 timer_value : IN std_logic_vector (31 DOWNTO 0); -- time in units of 100us
364 hardware_trigger_in : IN std_logic ;
365 software_trigger_in : IN std_logic ;
366 adc_data_array : IN adc_data_array_type ;
367 adc_output_enable_inverted : OUT std_logic := '1';
368 adc_clk_en : OUT std_logic := '0';
369 adc_otr : IN std_logic_vector (3 DOWNTO 0);
370 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
371 --drs_dwrite : out std_logic := '1';
372 drs_readout_ready : OUT std_logic := '0';
373 drs_readout_ready_ack : IN std_logic ;
374 drs_clk_en : OUT std_logic := '0';
375 start_read_drs_stop_cell : OUT std_logic := '0';
376 drs_srin_write_8b : OUT std_logic := '0';
377 drs_srin_write_ack : IN std_logic ;
378 drs_srin_data : OUT std_logic_vector (7 DOWNTO 0) := (others => '0');
379 drs_srin_write_ready : IN std_logic ;
380 drs_read_s_cell_ready : IN std_logic ;
381 drs_s_cell_array : IN drs_s_cell_array_type ;
382 drs_readout_started : OUT std_logic := '0';
383 trigger_veto : OUT std_logic := '1'
384 );
385 END COMPONENT;
386 COMPONENT dna_gen
387 PORT (
388 clk : IN STD_LOGIC ;
389 dna : OUT STD_LOGIC_VECTOR (63 DOWNTO 0) := (others => '0');
390 ready : OUT STD_LOGIC := '0'
391 );
392 END COMPONENT;
393 COMPONENT drs_pulser
394 PORT (
395 CLK : IN std_logic;
396 SROUT_in_0 : IN std_logic;
397 SROUT_in_1 : IN std_logic;
398 SROUT_in_2 : IN std_logic;
399 SROUT_in_3 : IN std_logic;
400 srin_data : IN std_logic_vector (7 DOWNTO 0);
401 start_endless_mode : IN std_logic;
402 start_read_stop_pos_mode : IN std_logic;
403 start_srin_write_8b : IN std_logic;
404 RSRLOAD : OUT std_logic := '0';
405 SRCLK : OUT std_logic := '0';
406 SRIN_out : OUT std_logic := '0';
407 srin_write_ack : OUT std_logic := '0';
408 srin_write_ready : OUT std_logic := '0';
409 stop_pos : OUT drs_s_cell_array_type;
410 stop_pos_valid : OUT std_logic := '0'
411 );
412 END COMPONENT;
413 COMPONENT led_controller
414 GENERIC (
415 HEARTBEAT_PWM_DIVIDER : integer := 500;
416 WAITING_DIVIDER : integer := 500000000
417 );
418 PORT (
419 CLK : IN std_logic;
420 refclk_too_high : IN std_logic;
421 refclk_too_low : IN std_logic;
422 socks_connected : IN std_logic;
423 socks_waiting : IN std_logic;
424 trigger : IN std_logic;
425 trigger_veto : IN std_logic;
426 w5300_reset : IN std_logic;
427 additional_flasher_out : OUT std_logic;
428 amber : OUT std_logic;
429 green : OUT std_logic;
430 red : OUT std_logic
431 );
432 END COMPONENT;
433 COMPONENT memory_manager_2
434 GENERIC (
435 RAM_ADDR_WIDTH_64B : integer := 12;
436 RAM_ADDR_WIDTH_16B : integer := 14
437 );
438 PORT (
439 clk : IN std_logic;
440 config_start : IN std_logic;
441 dg_config_done : IN std_logic;
442 ram_write_ready : IN std_logic;
443 roi_array : IN roi_array_type;
444 wiz_read_done : IN std_logic;
445 config_ready : OUT std_logic := '1';
446 data_ram_empty : OUT std_logic;
447 dg_start_config : OUT std_logic := '0';
448 package_length : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
449 ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0');
450 ram_write_ea : OUT std_logic := '0';
451 roi_max : OUT roi_max_type := (others => conv_std_logic_vector (0, 11));
452 state : OUT std_logic_vector (3 DOWNTO 0);
453 wiz_number_of_channels : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
454 wiz_ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_16B-1 DOWNTO 0) := (others => '0');
455 wiz_write_ea : OUT std_logic := '0';
456 wiz_write_end : OUT std_logic := '0';
457 wiz_write_header : OUT std_logic := '0';
458 wiz_write_length : OUT std_logic_vector (16 DOWNTO 0) := (others => '0')
459 );
460 END COMPONENT;
461 COMPONENT spi_interface
462 PORT (
463 clk_50MHz : IN std_logic ;
464 config_start : IN std_logic ;
465 dac_array : IN dac_array_type ;
466 sclk_enable_i : IN std_logic ;
467 config_ready : OUT std_logic ;
468 current_dac_array : OUT dac_array_type := ( others => 0);
469 dac_cs : OUT std_logic ;
470 mosi : OUT std_logic := '0';
471 sclk : OUT std_logic ;
472 sensor_array : OUT sensor_array_type ;
473 sensor_cs : OUT std_logic_vector (3 DOWNTO 0);
474 sensor_ready : OUT std_logic ;
475 miso : INOUT std_logic
476 );
477 END COMPONENT;
478 COMPONENT timer
479 GENERIC (
480 TIMER_WIDTH : integer := 32;
481 PRESCALER : integer := 5000
482 );
483 PORT (
484 clk : IN std_logic;
485 enable_i : IN std_logic;
486 reset_synch_i : IN std_logic;
487 synch_i : IN std_logic;
488 synched_o : OUT std_logic := '0';
489 time_o : OUT std_logic_vector ( TIMER_WIDTH-1 DOWNTO 0)
490 );
491 END COMPONENT;
492 COMPONENT trigger_counter
493 PORT (
494 trigger_id : OUT std_logic_vector (31 DOWNTO 0);
495 trigger : IN std_logic ;
496 reset : IN std_logic ;
497 clk : IN std_logic
498 );
499 END COMPONENT;
500 COMPONENT trigger_manager
501 PORT (
502 clk : IN std_logic;
503 drs_readout_ready : IN std_logic;
504 trigger_in : IN std_logic;
505 drs_readout_ready_ack : OUT std_logic := '0';
506 drs_write : OUT std_logic := '1';
507 trigger_out : OUT std_logic := '0'
508 );
509 END COMPONENT;
510 COMPONENT w5300_modul
511 GENERIC (
512 RAM_ADDR_WIDTH : integer := 14
513 );
514 PORT (
515 state : OUT std_logic_vector (7 DOWNTO 0); -- state is encoded here ... useful for debugging.
516 debug_data_ram_empty : OUT std_logic ;
517 debug_data_valid : OUT std_logic ;
518 data_generator_idle_i : IN std_logic ;
519 data_ram_not_full : IN std_logic ;
520 socket_tx_free_out : OUT std_logic_vector (16 DOWNTO 0); -- 17bit value .. that's true
521 clk : IN std_logic ;
522 wiz_reset : OUT std_logic := '1';
523 addr : OUT std_logic_vector (9 DOWNTO 0);
524 data : INOUT std_logic_vector (15 DOWNTO 0);
525 cs : OUT std_logic := '1';
526 wr : OUT std_logic := '1';
527 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
528 rd : OUT std_logic := '1';
529 int : IN std_logic ;
530 write_length : IN std_logic_vector (16 DOWNTO 0);
531 ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
532 ram_data : IN std_logic_vector (15 DOWNTO 0);
533 ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
534 data_valid : IN std_logic ;
535 data_valid_ack : OUT std_logic := '0';
536 busy : OUT std_logic := '1';
537 write_header_flag : IN std_logic ;
538 write_end_flag : IN std_logic ;
539 fifo_channels : IN std_logic_vector (3 DOWNTO 0);
540 -- softtrigger:
541 s_trigger : OUT std_logic := '0';
542 c_trigger_enable : OUT std_logic := '0';
543 c_trigger_mult : OUT std_logic_vector (15 DOWNTO 0) := conv_std_logic_vector(0 ,16); --subject TO changes
544 -- FAD configuration signals:
545 ------------------------------------------------------------------------------
546 memory_manager_config_start_o : OUT std_logic := '0';
547 memory_manager_config_valid_i : IN std_logic ;
548 spi_interface_config_start_o : OUT std_logic := '0';
549 spi_interface_config_valid_i : IN std_logic ;
550 --data_generator_config_start_o : out std_logic := '0';
551 --data_generator_config_valid_i : in std_logic;
552 dac_setting : OUT dac_array_type := DEFAULT_DAC; --<<-- default defined in fad_definitions.vhd
553 roi_setting : OUT roi_array_type := DEFAULT_ROI; --<<-- default defined in fad_definitions.vhd
554 runnumber : OUT std_logic_vector (31 DOWNTO 0) := conv_std_logic_vector(0 ,32);
555 reset_trigger_id : OUT std_logic := '0';
556 data_ram_empty : IN std_logic ;
557 ------------------------------------------------------------------------------
558
559 -- MAC/IP calculation signals:
560 ------------------------------------------------------------------------------
561 MAC_jumper : IN std_logic_vector (1 DOWNTO 0);
562 BoardID : IN std_logic_vector (3 DOWNTO 0);
563 CrateID : IN std_logic_vector (1 DOWNTO 0);
564 ------------------------------------------------------------------------------
565
566 -- user controllable enable signals
567 ------------------------------------------------------------------------------
568 trigger_enable : OUT std_logic ;
569 denable : OUT std_logic := '0'; -- default domino wave on. ... in case if REFCLK error ... REFCLK counter will override.
570 dwrite_enable : OUT std_logic := '1'; -- default DWRITE low.
571 sclk_enable : OUT std_logic := '1'; -- default DWRITE HIGH.
572 srclk_enable : OUT std_logic := '1'; -- default SRCLK on.
573 busy_enable : OUT std_logic := '1';
574 socket_send_mode_out : OUT std_logic ;
575 busy_manual : OUT std_logic := '0';
576 ------------------------------------------------------------------------------
577
578 -- ADC CLK generator, is able to shift phase with respect to X_50M
579 -- these signals control the behavior of the digital clock manager (DCM)
580 ------------------------------------------------------------------------------
581 ps_direction : OUT std_logic := '1'; -- default phase shift upwards
582 ps_do_phase_shift : OUT std_logic := '0'; --pulse this TO phase shift once
583 ps_reset : OUT std_logic := '0'; -- pulse this TO reset the variable phase shift
584 ps_ready : IN std_logic ;
585 ------------------------------------------------------------------------------
586
587 -- signals used to control FAD LED bahavior:
588 -- one of the three LEDs is used for com-status info
589 ------------------------------------------------------------------------------
590 socks_waiting : OUT std_logic ;
591 socks_connected : OUT std_logic
592 ------------------------------------------------------------------------------
593 );
594 END COMPONENT;
595
596 -- Optional embedded configurations
597 -- pragma synthesis_off
598 FOR ALL : FAD_rs485_receiver USE ENTITY FACT_FAD_lib.FAD_rs485_receiver;
599 FOR ALL : REFCLK_counter USE ENTITY FACT_FAD_lib.REFCLK_counter;
600 FOR ALL : adc_buffer USE ENTITY FACT_FAD_lib.adc_buffer;
601 FOR ALL : clock_generator_var_ps USE ENTITY FACT_FAD_lib.clock_generator_var_ps;
602 FOR ALL : continous_pulser USE ENTITY FACT_FAD_lib.continous_pulser;
603 FOR ALL : dataRAM_64b_16b_width14_5 USE ENTITY FACT_FAD_lib.dataRAM_64b_16b_width14_5;
604 FOR ALL : data_generator USE ENTITY FACT_FAD_lib.data_generator;
605 FOR ALL : dna_gen USE ENTITY FACT_FAD_lib.dna_gen;
606 FOR ALL : drs_pulser USE ENTITY FACT_FAD_lib.drs_pulser;
607 FOR ALL : led_controller USE ENTITY FACT_FAD_lib.led_controller;
608 FOR ALL : memory_manager_2 USE ENTITY FACT_FAD_lib.memory_manager_2;
609 FOR ALL : spi_interface USE ENTITY FACT_FAD_lib.spi_interface;
610 FOR ALL : timer USE ENTITY FACT_FAD_lib.timer;
611 FOR ALL : trigger_counter USE ENTITY FACT_FAD_lib.trigger_counter;
612 FOR ALL : trigger_manager USE ENTITY FACT_FAD_lib.trigger_manager;
613 FOR ALL : w5300_modul USE ENTITY FACT_FAD_lib.w5300_modul;
614 -- pragma synthesis_on
615
616
617BEGIN
618
619 -- ModuleWare code(v1.9) for instance 'I6' of 'and'
620 SRCLK <= SRCLK1 AND srclk_enable;
621
622 -- ModuleWare code(v1.9) for instance 'U_1' of 'and'
623 dout <= dout0 AND dout1 AND dout2 AND dout3;
624
625 -- ModuleWare code(v1.9) for instance 'U_4' of 'and'
626 dwrite_global_enable <= dwrite_enable_w5300 AND dout4;
627
628 -- ModuleWare code(v1.9) for instance 'U_7' of 'and'
629 dout7 <= busy_high_active AND not_busy_enable;
630
631 -- ModuleWare code(v1.9) for instance 'U_10' of 'and'
632 cont_trigger <= trigger1 AND dout8;
633
634 -- ModuleWare code(v1.9) for instance 'and_1' of 'and'
635 ADC_CLK <= adc_clk_en AND CLK_25_PS_internal;
636
637 -- ModuleWare code(v1.9) for instance 'and_2' of 'and'
638 denable_sig <= denable_prim AND din1;
639
640 -- ModuleWare code(v1.9) for instance 'and_4' of 'and'
641 dout6 <= trigger_or_s_trigger AND trigger_enable;
642
643 -- ModuleWare code(v1.9) for instance 'and_5' of 'and'
644 drs_dwrite <= dwrite_trigger_manager AND dwrite_global_enable;
645
646 -- ModuleWare code(v1.9) for instance 'U_5' of 'assignment'
647 denable <= denable_sig;
648
649 -- ModuleWare code(v1.9) for instance 'U_8' of 'assignment'
650 trigger_veto <= trig_veto;
651
652 -- ModuleWare code(v1.9) for instance 'U_9' of 'assignment'
653 wiz_reset <= wiz_reset1;
654
655 -- ModuleWare code(v1.9) for instance 'U_6' of 'gnd'
656 software_trigger_in <= '0';
657
658 -- ModuleWare code(v1.9) for instance 'U_15' of 'gnd'
659 reset_synch_i <= '0';
660
661 -- ModuleWare code(v1.9) for instance 'inverter_1' of 'inv'
662 din1 <= NOT(alarm_refclk_too_low_internal);
663
664 -- ModuleWare code(v1.9) for instance 'inverter_2' of 'inv'
665 dout5 <= NOT(ram_write_ea);
666
667 -- ModuleWare code(v1.9) for instance 'inverter_3' of 'inv'
668 dout8 <= NOT(busy_high_active);
669
670 -- ModuleWare code(v1.9) for instance 'inverter_4' of 'inv'
671 not_busy_enable <= NOT(busy_enable);
672
673 -- ModuleWare code(v1.9) for instance 'U_2' of 'or'
674 dout4 <= dout OR I_really_want_dwrite;
675
676 -- ModuleWare code(v1.9) for instance 'or_1' of 'or'
677 enabled_trigger_or_s_trigger <= s_trigger OR dout6;
678
679 -- ModuleWare code(v1.9) for instance 'or_2' of 'or'
680 busy_high_active <= trigger_veto1 OR dout5;
681
682 -- ModuleWare code(v1.9) for instance 'or_3' of 'or'
683 trig_veto <= busy_manual OR dout7;
684
685 -- ModuleWare code(v1.9) for instance 'or_5' of 'or'
686 trigger_or_s_trigger <= cont_trigger OR trigger;
687
688 -- ModuleWare code(v1.9) for instance 'U_0' of 'split'
689 mw_U_0temp_din <= plllock_in;
690 u_0combo_proc: PROCESS (mw_U_0temp_din)
691 VARIABLE temp_din: std_logic_vector(3 DOWNTO 0);
692 BEGIN
693 temp_din := mw_U_0temp_din(3 DOWNTO 0);
694 dout0 <= temp_din(0);
695 dout1 <= temp_din(1);
696 dout2 <= temp_din(2);
697 dout3 <= temp_din(3);
698 END PROCESS u_0combo_proc;
699
700 -- ModuleWare code(v1.9) for instance 'U_3' of 'vdd'
701 I_really_want_dwrite <= '1';
702
703 -- ModuleWare code(v1.9) for instance 'U_14' of 'vdd'
704 enable_i <= '1';
705
706 -- Instance port mappings.
707 Inst_rs485_receiver : FAD_rs485_receiver
708 GENERIC MAP (
709 RX_BYTES => RS485_MESSAGE_LEN_BYTES, -- no. of bytes to receive
710 RX_WIDTH => RS485_MESSAGE_LEN_BYTES * 8 -- no. of bits to receive
711 )
712 PORT MAP (
713 rec_clk => CLK_50_internal,
714 rx_d => FTM_RS485_rx_d,
715 rx_en => FTM_RS485_rx_en,
716 tx_d => FTM_RS485_tx_d,
717 tx_en => FTM_RS485_tx_en,
718 rec_start => drs_readout_started,
719 rec_timeout_occured => rec_timeout_occured,
720 rec_dout => rs465_data,
721 rec_valid => FTM_RS485_ready
722 );
723 REFCLK_counter_main : REFCLK_counter
724 PORT MAP (
725 clk => CLK_50_internal,
726 refclk_in => drs_refclk_in,
727 counter_result => counter_result_internal,
728 alarm_refclk_too_high => alarm_refclk_too_high_internal,
729 alarm_refclk_too_low => alarm_refclk_too_low_internal
730 );
731 I_main_adc_buffer : adc_buffer
732 PORT MAP (
733 clk_ps => CLK_25_PS_internal,
734 adc_data_array => adc_data_array,
735 adc_otr_array => adc_otr_array,
736 adc_data_array_int => adc_data_array_int,
737 adc_otr => adc_otr
738 );
739 clock_generator_instance : clock_generator_var_ps
740 PORT MAP (
741 CLK => CLK,
742 RST_IN => ps_reset,
743 direction => ps_direction,
744 do_shift => ps_do_phase_shift,
745 CLK_25 => CLK_25,
746 CLK_25_PS => CLK_25_PS_internal,
747 CLK_50 => CLK_50_internal,
748 locked_status_o => DCM_locked_status,
749 offset => DCM_PS_status,
750 ready_status_o => DCM_ready_status
751 );
752 continous_pulser_instance : continous_pulser
753 GENERIC MAP (
754 MINIMAL_TRIGGER_WAIT_TIME => 25000,
755 TRIGGER_WIDTH => 5
756 )
757 PORT MAP (
758 CLK => CLK_25,
759 enable => c_trigger_enable,
760 multiplier => c_trigger_mult,
761 trigger => trigger1
762 );
763 data_RAM_inst : dataRAM_64b_16b_width14_5
764 PORT MAP (
765 clka => CLK_25,
766 dina => data_out,
767 addra => addr_out,
768 wea => write_ea,
769 clkb => CLK_50_internal,
770 addrb => ram_addr,
771 doutb => ram_data
772 );
773 I_main_data_generator : data_generator
774 GENERIC MAP (
775 RAM_ADDR_WIDTH => RAMADDRWIDTH64b
776 )
777 PORT MAP (
778 state => DG_state,
779 is_idle => is_idle,
780 clk => CLK_25,
781 data_out => data_out,
782 addr_out => addr_out,
783 dataRAM_write_ea_o => write_ea,
784 ram_start_addr => ram_start_addr,
785 ram_write_ea => ram_write_ea,
786 ram_write_ready => ram_write_ready,
787 roi_array => roi_setting,
788 roi_max => roi_max,
789 sensor_array => sensor_array,
790 sensor_ready => sensor_ready,
791 dac_array => current_dac_array,
792 config_start => dg_start_config,
793 config_done => dg_config_done,
794 package_length => package_length,
795 pll_lock => plllock_in,
796 dwrite_enable_in => dwrite_enable_w5300,
797 denable_enable_in => denable_sig,
798 busy_enable_in => busy_enable,
799 trigger_enable_in => trigger_enable,
800 cont_trigger_en_in => c_trigger_enable,
801 socket_send_mode_in => socket_send_mode_out,
802 busy_manual_in => busy_manual,
803 FTM_RS485_ready => FTM_RS485_ready,
804 FTM_trigger_info => rs465_data,
805 FTM_receiver_status => rec_timeout_occured,
806 fad_event_counter => trigger_id,
807 refclk_counter => counter_result_internal,
808 refclk_too_high => alarm_refclk_too_high_internal,
809 refclk_too_low => alarm_refclk_too_low_internal,
810 board_id => board_id,
811 crate_id => crate_id,
812 DCM_PS_status => DCM_PS_status,
813 DCM_locked_status => DCM_locked_status,
814 DCM_ready_status => DCM_ready_status,
815 SPI_SCLK_enable_status => sclk_enable,
816 TRG_GEN_div => c_trigger_mult,
817 dna => dna,
818 runnumber => runnumber,
819 timer_value => time,
820 hardware_trigger_in => trigger_out,
821 software_trigger_in => software_trigger_in,
822 adc_data_array => adc_data_array_int,
823 adc_output_enable_inverted => adc_oeb,
824 adc_clk_en => adc_clk_en,
825 adc_otr => adc_otr,
826 drs_channel_id => drs_channel_id,
827 drs_readout_ready => drs_readout_ready,
828 drs_readout_ready_ack => drs_readout_ready_ack,
829 drs_clk_en => drs_clk_en,
830 start_read_drs_stop_cell => drs_read_s_cell,
831 drs_srin_write_8b => start_srin_write_8b,
832 drs_srin_write_ack => srin_write_ack,
833 drs_srin_data => drs_srin_data,
834 drs_srin_write_ready => srin_write_ready,
835 drs_read_s_cell_ready => drs_read_s_cell_ready,
836 drs_s_cell_array => drs_s_cell_array,
837 drs_readout_started => drs_readout_started,
838 trigger_veto => trigger_veto1
839 );
840 dna_gen_instance : dna_gen
841 PORT MAP (
842 clk => CLK_25,
843 dna => dna,
844 ready => ready
845 );
846 I_main_drs_pulser : drs_pulser
847 PORT MAP (
848 CLK => CLK_25,
849 start_endless_mode => drs_clk_en,
850 start_read_stop_pos_mode => drs_read_s_cell,
851 SROUT_in_0 => SROUT_in_0,
852 SROUT_in_1 => SROUT_in_1,
853 SROUT_in_2 => SROUT_in_2,
854 SROUT_in_3 => SROUT_in_3,
855 stop_pos => drs_s_cell_array,
856 stop_pos_valid => drs_read_s_cell_ready,
857 start_srin_write_8b => start_srin_write_8b,
858 srin_write_ready => srin_write_ready,
859 srin_write_ack => srin_write_ack,
860 srin_data => drs_srin_data,
861 SRIN_out => SRIN_out,
862 RSRLOAD => RSRLOAD,
863 SRCLK => SRCLK1
864 );
865 led_controller_instance : led_controller
866 GENERIC MAP (
867 HEARTBEAT_PWM_DIVIDER => 50000,
868 WAITING_DIVIDER => 50000000
869 )
870 PORT MAP (
871 CLK => CLK_50_internal,
872 green => green,
873 amber => amber,
874 red => red,
875 additional_flasher_out => OPEN,
876 trigger => drs_readout_started,
877 w5300_reset => wiz_reset1,
878 trigger_veto => trig_veto,
879 refclk_too_high => alarm_refclk_too_high_internal,
880 refclk_too_low => alarm_refclk_too_low_internal,
881 socks_waiting => socks_waiting,
882 socks_connected => socks_connected
883 );
884 Inst_memory_manager_2 : memory_manager_2
885 GENERIC MAP (
886 RAM_ADDR_WIDTH_64B => RAMADDRWIDTH64b,
887 RAM_ADDR_WIDTH_16B => RAMADDRWIDTH64b+2
888 )
889 PORT MAP (
890 state => mem_manager_state,
891 clk => CLK_25,
892 config_start => memory_manager_config_start,
893 config_ready => memory_manager_config_valid,
894 roi_array => roi_setting,
895 roi_max => roi_max,
896 package_length => package_length,
897 wiz_number_of_channels => wiz_number_of_channels,
898 dg_start_config => dg_start_config,
899 dg_config_done => dg_config_done,
900 ram_write_ready => ram_write_ready,
901 ram_write_ea => ram_write_ea,
902 ram_start_addr => ram_start_addr,
903 wiz_read_done => data_valid_ack,
904 wiz_write_ea => wiz_write_ea,
905 wiz_write_length => wiz_write_length,
906 wiz_ram_start_addr => wiz_ram_start_addr,
907 wiz_write_header => wiz_write_header,
908 wiz_write_end => wiz_write_end,
909 data_ram_empty => data_ram_empty
910 );
911 I_main_SPI_interface : spi_interface
912 PORT MAP (
913 clk_50MHz => CLK_50_internal,
914 config_start => spi_interface_config_start,
915 dac_array => dac_setting,
916 sclk_enable_i => sclk_enable,
917 config_ready => spi_interface_config_valid,
918 current_dac_array => current_dac_array,
919 dac_cs => dac_cs,
920 mosi => mosi,
921 sclk => sclk,
922 sensor_array => sensor_array,
923 sensor_cs => sensor_cs,
924 sensor_ready => sensor_ready,
925 miso => sio
926 );
927 timer_instance : timer
928 GENERIC MAP (
929 TIMER_WIDTH => 32,
930 PRESCALER => 5000
931 )
932 PORT MAP (
933 clk => CLK_50_internal,
934 time_o => time,
935 synch_i => trigger_out,
936 synched_o => OPEN,
937 reset_synch_i => reset_synch_i,
938 enable_i => enable_i
939 );
940 trigger_counter_instance : trigger_counter
941 PORT MAP (
942 trigger_id => trigger_id,
943 trigger => trigger_out,
944 reset => reset_trigger_id,
945 clk => CLK_25_PS_internal
946 );
947 trigger_manager_instance : trigger_manager
948 PORT MAP (
949 clk => CLK_25,
950 trigger_in => enabled_trigger_or_s_trigger,
951 trigger_out => trigger_out,
952 drs_write => dwrite_trigger_manager,
953 drs_readout_ready => drs_readout_ready,
954 drs_readout_ready_ack => drs_readout_ready_ack
955 );
956 w5300_modul_instance : w5300_modul
957 GENERIC MAP (
958 RAM_ADDR_WIDTH => RAMADDRWIDTH64b+2
959 )
960 PORT MAP (
961 state => w5300_state,
962 debug_data_ram_empty => debug_data_ram_empty,
963 debug_data_valid => debug_data_valid,
964 data_generator_idle_i => is_idle,
965 data_ram_not_full => ram_write_ea,
966 busy_manual => busy_manual,
967 socket_tx_free_out => socket_tx_free_out,
968 clk => CLK_50_internal,
969 wiz_reset => wiz_reset1,
970 addr => wiz_addr,
971 data => wiz_data,
972 cs => wiz_cs,
973 wr => wiz_wr,
974 led => led,
975 rd => wiz_rd,
976 int => wiz_int,
977 write_length => wiz_write_length,
978 ram_start_addr => wiz_ram_start_addr,
979 ram_data => ram_data,
980 ram_addr => ram_addr,
981 data_valid => wiz_write_ea,
982 data_valid_ack => data_valid_ack,
983 busy => OPEN,
984 write_header_flag => wiz_write_header,
985 write_end_flag => wiz_write_end,
986 fifo_channels => wiz_number_of_channels,
987 s_trigger => s_trigger,
988 c_trigger_enable => c_trigger_enable,
989 c_trigger_mult => c_trigger_mult,
990 memory_manager_config_start_o => memory_manager_config_start,
991 memory_manager_config_valid_i => memory_manager_config_valid,
992 spi_interface_config_start_o => spi_interface_config_start,
993 spi_interface_config_valid_i => spi_interface_config_valid,
994 dac_setting => dac_setting,
995 roi_setting => roi_setting,
996 runnumber => runnumber,
997 reset_trigger_id => reset_trigger_id,
998 data_ram_empty => data_ram_empty,
999 MAC_jumper => D_T_in,
1000 BoardID => board_id,
1001 CrateID => crate_id,
1002 trigger_enable => trigger_enable,
1003 denable => denable_prim,
1004 dwrite_enable => dwrite_enable_w5300,
1005 sclk_enable => sclk_enable,
1006 srclk_enable => srclk_enable,
1007 busy_enable => busy_enable,
1008 socket_send_mode_out => socket_send_mode_out,
1009 ps_direction => ps_direction,
1010 ps_do_phase_shift => ps_do_phase_shift,
1011 ps_reset => ps_reset,
1012 ps_ready => DCM_ready_status,
1013 socks_waiting => socks_waiting,
1014 socks_connected => socks_connected
1015 );
1016
1017 -- Implicit buffered output assignments
1018 CLK_25_PS <= CLK_25_PS_internal;
1019 CLK_50 <= CLK_50_internal;
1020 alarm_refclk_too_high <= alarm_refclk_too_high_internal;
1021 alarm_refclk_too_low <= alarm_refclk_too_low_internal;
1022 counter_result <= counter_result_internal;
1023
1024END struct;
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