| 1 | library ieee;
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| 2 | use ieee.std_logic_1164.all;
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| 3 | use IEEE.STD_LOGIC_ARITH.all;
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| 4 | use ieee.STD_LOGIC_UNSIGNED.all;
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| 5 |
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| 6 | library FACT_FAD_lib;
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| 7 | use FACT_FAD_lib.fad_definitions.all;
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| 8 |
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| 9 | -- library UNISIM;
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| 10 | -- use UNISIM.VComponents.all;
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| 11 | -- USE IEEE.NUMERIC_STD.all;
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| 12 |
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| 13 | -- RAM_ADDR_WIDTH_64B is used for
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| 14 | -- output ram_start_addr
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| 15 |
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| 16 | -- RAM_ADDR_WIDTH_16B is used for
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| 17 | -- output wiz_ram_start_addr
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| 18 |
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| 19 |
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| 20 | ENTITY memory_manager_2 IS
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| 21 | generic(
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| 22 | RAM_ADDR_WIDTH_64B : integer := 12;
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| 23 | RAM_ADDR_WIDTH_16B : integer := 14
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| 24 | );
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| 25 | PORT(
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| 26 | state : OUT std_logic_vector (3 DOWNTO 0); -- state is encoded here ... useful for debugging.
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| 27 |
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| 28 | clk : IN std_logic;
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| 29 |
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| 30 | -- CONFIG handshake:
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| 31 | config_start : IN std_logic;
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| 32 | config_ready : OUT std_logic := '1';
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| 33 | -- output of CONFIG states
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| 34 | roi_array : IN roi_array_type;
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| 35 | roi_max : OUT roi_max_type := (others => conv_std_logic_vector (0, 11));
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| 36 | package_length : OUT std_logic_vector (15 downto 0) := (others => '0');
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| 37 |
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| 38 | wiz_number_of_channels : OUT std_logic_vector (3 downto 0) := (others => '0');
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| 39 |
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| 40 | -- interface to DG:
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| 41 | dg_start_config : OUT std_logic := '0';
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| 42 | dg_config_done : IN std_logic;
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| 43 | ram_write_ready : IN std_logic;
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| 44 | ram_write_ea : OUT std_logic := '0';
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| 45 | ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0');
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| 46 |
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| 47 | -- interface to W5300:
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| 48 | wiz_read_done : IN std_logic;
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| 49 | wiz_write_ea : OUT std_logic := '0';
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| 50 | wiz_write_length : OUT std_logic_vector (16 downto 0) := (others => '0');
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| 51 | wiz_ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_16B-1 downto 0) := (others => '0');
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| 52 | wiz_write_header : OUT std_logic := '0';
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| 53 | wiz_write_end : OUT std_logic := '0';
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| 54 |
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| 55 |
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| 56 | data_ram_empty : out std_logic -- stupid signal, I need to get rid of it. DN 23.05.2011
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| 57 | );
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| 58 |
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| 59 | -- Declarations
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| 60 |
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| 61 | END memory_manager_2 ;
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| 62 |
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| 63 | --
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| 64 | ARCHITECTURE beha OF memory_manager_2 IS
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| 65 |
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| 66 | type state_mm_type is ( MM_CONFIG, MAX_ROI, MAX_ROI1, MAX_ROI2, FIFO_CALC, RAM_CALC, RAM_CALC1, RAM_CALC2,
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| 67 | CONFIG_DG, WAIT_FOR_CONFIG_DG,
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| 68 | MM_MAIN,
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| 69 | WRITE_FIN, READ_FIN, UPDATE_OUTPUT, UPDATE_OUTPUT_2);
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| 70 | signal state_mm : state_mm_type := MM_CONFIG;
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| 71 |
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| 72 | --type roi_array_type is array (0 to 35) of integer range 0 to 1024;
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| 73 | type roi_max_array_type is array (0 to 8) of integer range 0 to 1024;
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| 74 | type channel_size_type is array (0 to 8) of integer range 0 to W5300_TX_FIFO_SIZE;
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| 75 | type fifo_write_length_type is array (0 to 8) of integer range 0 to W5300_TX_FIFO_SIZE;
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| 76 | type fifo_channels_array_type is array (0 to 8) of integer range 0 to 9;
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| 77 | type fifo_package_size_ram_type is array (0 to 8) of integer range 0 to RAM_SIZE_16B;
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| 78 |
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| 79 | signal roi_max_array : roi_max_array_type := (others => 0);
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| 80 |
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| 81 | -- size of channel groups (16 bit)
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| 82 | signal channel_size : channel_size_type := (others => 0);
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| 83 | -- write length of packages (16 bit)
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| 84 | signal fifo_write_length : fifo_write_length_type := (others => 0);
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| 85 | -- number of channels per package
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| 86 | signal fifo_channels_array : fifo_channels_array_type := (others => 0);
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| 87 | -- size of packages in ram (16 bit)
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| 88 | signal fifo_package_size_ram : fifo_package_size_ram_type := (others => 0);
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| 89 | --
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| 90 | signal event_size_ram : integer range 0 to RAM_SIZE_16B := 0;
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| 91 | signal event_size_ram_64b : integer range 0 to RAM_SIZE_64B := 0;
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| 92 | signal event_size : integer range 0 to RAM_SIZE_16B := 0;
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| 93 |
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| 94 | signal drs_id : integer range 0 to 4 := 0;
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| 95 | signal channel_id : integer range 0 to 9 := 0;
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| 96 | signal channel_index : integer range 0 to 9 := 0;
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| 97 | signal package_index : integer range 0 to 9 := 0;
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| 98 | signal number_of_packages : integer range 0 to 9 := 0;
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| 99 | signal max_events_ram : integer range 0 to 2048;
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| 100 | signal events_in_ram : integer range 0 to 2048;
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| 101 | signal event_start_addr : integer range 0 to (RAM_SIZE_64B - 1);
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| 102 | signal write_start_addr : integer range 0 to (RAM_SIZE_16B - 1);
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| 103 |
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| 104 |
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| 105 | signal roi_index : integer range 0 to 45 := 0;
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| 106 | signal temp_roi : integer range 0 to 1024 := 0;
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| 107 |
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| 108 | -- SYNCH IN INPUT SIGNALS -----------------------------------------
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| 109 |
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| 110 | signal config_start_sr : std_logic_vector(1 downto 0) := "00";
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| 111 | signal ram_write_ready_sr : std_logic_vector(1 downto 0) := "00";
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| 112 | signal wiz_read_ready_sr : std_logic_vector(1 downto 0) := "00";
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| 113 | signal dg_config_done_sr : std_logic_vector(1 downto 0) := "00";
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| 114 | -- no shift register, but local copy.
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| 115 | signal roi_array_local : roi_array_type;
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| 116 |
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| 117 |
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| 118 | signal state_sig : std_logic_vector( 3 downto 0 ) := "0000";
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| 119 |
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| 120 | BEGIN
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| 121 | state <= state_sig;
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| 122 |
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| 123 | data_ram_empty <= '1' when events_in_ram = 0 else '0';
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| 124 |
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| 125 | mm : process (clk)
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| 126 | begin
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| 127 | if rising_edge (clk) then
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| 128 | -- here: the synchin in of asynchronous input signals takes place.
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| 129 | config_start_sr <= config_start_sr(0) & config_start;
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| 130 | ram_write_ready_sr <= ram_write_ready_sr(0) & ram_write_ready;
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| 131 | wiz_read_ready_sr <= wiz_read_ready_sr(0) & wiz_read_done;
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| 132 | dg_config_done_sr <= dg_config_done_sr(0) & dg_config_done;
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| 133 | roi_array_local <= roi_array;
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| 134 |
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| 135 | case state_mm is
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| 136 |
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| 137 |
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| 138 |
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| 139 |
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| 140 | when MM_CONFIG =>
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| 141 | state_sig <= X"1";
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| 142 |
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| 143 |
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| 144 | config_ready <= '0';
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| 145 | roi_max_array <= (others => 0);
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| 146 | channel_size <= (others => 0);
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| 147 | fifo_write_length <= (others => 0);
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| 148 | fifo_channels_array <= (others => 0);
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| 149 | event_size <= 0;
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| 150 | ram_write_ea <= '0';
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| 151 | wiz_write_ea <= '0';
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| 152 | state_mm <= MAX_ROI;
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| 153 |
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| 154 |
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| 155 | -- calculate max ROIs and channel sizes
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| 156 | when MAX_ROI =>
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| 157 | state_sig <= X"2";
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| 158 | roi_index <= (drs_id * 9) + channel_id;
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| 159 | state_mm <= MAX_ROI1;
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| 160 | when MAX_ROI1 =>
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| 161 | state_sig <= X"3";
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| 162 | temp_roi <= roi_array_local (roi_index);
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| 163 | state_mm <= MAX_ROI2;
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| 164 | when MAX_ROI2 =>
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| 165 | state_sig <= X"4";
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| 166 | if (channel_id < 9) then
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| 167 | if ( temp_roi > roi_max_array (channel_id)) then
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| 168 | roi_max_array (channel_id) <= temp_roi;
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| 169 | end if;
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| 170 | channel_size (channel_id) <= channel_size (channel_id) + temp_roi + CHANNEL_HEADER_SIZE;
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| 171 | drs_id <= drs_id + 1;
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| 172 | state_mm <= MAX_ROI;
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| 173 | if (drs_id = 3) then
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| 174 | drs_id <= 0;
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| 175 | channel_id <= channel_id + 1;
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| 176 | end if;
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| 177 | else
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| 178 | drs_id <= 0;
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| 179 | channel_id <= 0;
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| 180 | channel_size (0) <= channel_size (0) + PACKAGE_HEADER_LENGTH;
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| 181 | channel_size (8) <= channel_size (8) + PACKAGE_END_LENGTH;
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| 182 | state_mm <= FIFO_CALC;
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| 183 | end if;
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| 184 |
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| 185 | -- calculate number of channels that fit in FIFO
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| 186 | when FIFO_CALC =>
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| 187 | state_sig <= X"5";
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| 188 | if (channel_id < 9) then
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| 189 | if ((fifo_write_length (package_index) + channel_size (channel_id)) <= W5300_TX_FIFO_SIZE) then
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| 190 | fifo_write_length (package_index) <= fifo_write_length (package_index) + channel_size (channel_id);
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| 191 | fifo_channels_array (package_index) <= fifo_channels_array (package_index) + 1;
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| 192 | channel_id <= channel_id + 1;
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| 193 | event_size <= event_size + channel_size (channel_id);
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| 194 | else
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| 195 | package_index <= package_index + 1;
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| 196 | end if;
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| 197 | else
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| 198 | number_of_packages <= package_index + 1;
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| 199 | package_index <= 0;
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| 200 | channel_index <= 0;
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| 201 | channel_id <= 0;
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| 202 | fifo_package_size_ram <= (others => 0);
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| 203 | fifo_package_size_ram (0) <= PACKAGE_HEADER_LENGTH + PACKAGE_HEADER_ZEROS;
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| 204 | event_size_ram <= 0;
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| 205 | event_size_ram_64b <= 0;
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| 206 | max_events_ram <= 0;
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| 207 | state_mm <= RAM_CALC;
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| 208 | end if;
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| 209 |
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| 210 | when RAM_CALC =>
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| 211 | state_sig <= X"6";
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| 212 | if (package_index < number_of_packages) then
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| 213 | if (channel_index < fifo_channels_array (package_index)) then
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| 214 | fifo_package_size_ram (package_index) <=
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| 215 | fifo_package_size_ram (package_index) + ((roi_max_array (channel_id) + CHANNEL_HEADER_SIZE) * NUMBER_OF_DRS);
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| 216 | channel_index <= channel_index + 1;
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| 217 | channel_id <= channel_id + 1;
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| 218 | else
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| 219 | package_index <= package_index + 1;
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| 220 | event_size_ram <= event_size_ram + fifo_package_size_ram (package_index);
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| 221 | channel_index <= 0;
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| 222 | end if;
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| 223 | else
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| 224 | fifo_package_size_ram (package_index - 1) <= fifo_package_size_ram (package_index - 1) + PACKAGE_END_LENGTH + PACKAGE_END_ZEROS;
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| 225 | event_size_ram <= event_size_ram + PACKAGE_END_LENGTH + PACKAGE_END_ZEROS;
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| 226 | state_mm <= RAM_CALC1;
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| 227 | end if;
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| 228 | when RAM_CALC1 =>
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| 229 | state_sig <= X"7";
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| 230 | max_events_ram <= max_events_ram + 1;
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| 231 | if ((max_events_ram * event_size_ram) <= RAM_SIZE_16B) then
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| 232 | state_mm <= RAM_CALC1;
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| 233 | else
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| 234 | max_events_ram <= max_events_ram - 1;
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| 235 | state_mm <= RAM_CALC2;
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| 236 | end if;
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| 237 | when RAM_CALC2 =>
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| 238 | state_sig <= X"8";
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| 239 | event_size_ram_64b <= (event_size_ram / 4);
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| 240 | events_in_ram <= 0;
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| 241 | event_start_addr <= 0;
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| 242 | write_start_addr <= 0;
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| 243 | package_index <= 0;
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| 244 | channel_id <= 0;
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| 245 | ram_start_addr <= (others => '0');
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| 246 |
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| 247 | package_length <= conv_std_logic_vector (event_size, 16);
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| 248 | for i in 0 to 8 loop
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| 249 | roi_max(i) <= conv_std_logic_vector(roi_max_array(i), 11);
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| 250 | end loop;
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| 251 | state_mm <= CONFIG_DG;
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| 252 |
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| 253 | when CONFIG_DG =>
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| 254 | state_sig <= X"9";
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| 255 | dg_start_config <= '1';
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| 256 | state_mm <= CONFIG_DG;
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| 257 | if (dg_config_done_sr(1) = '0') then
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| 258 | dg_start_config <= '0';
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| 259 | state_mm <= WAIT_FOR_CONFIG_DG;
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| 260 | end if;
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| 261 |
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| 262 | when WAIT_FOR_CONFIG_DG =>
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| 263 | state_sig <= X"E";
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| 264 | state_mm <= WAIT_FOR_CONFIG_DG;
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| 265 | if (dg_config_done_sr(1) = '1') then
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| 266 | state_mm <= UPDATE_OUTPUT;
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| 267 | end if;
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| 268 |
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| 269 |
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| 270 | when MM_MAIN =>
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| 271 | state_sig <= X"A";
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| 272 | state_mm <= MM_MAIN;
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| 273 |
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| 274 | config_ready <= '1';
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| 275 |
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| 276 | if (config_start_sr(1) = '1') then
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| 277 | state_mm <= MM_CONFIG;
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| 278 |
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| 279 | elsif (ram_write_ready_sr(1) = '1') then
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| 280 | -- this is part of the DG - MM handshake.
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| 281 | -- pulling write_ea low shows that MM understood DG is ready
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| 282 | ram_write_ea <= '0';
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| 283 |
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| 284 | events_in_ram <= events_in_ram + 1;
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| 285 | if ((event_start_addr + event_size_ram_64b) < (RAM_SIZE_64B - event_size_ram_64b)) then
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| 286 | event_start_addr <= event_start_addr + event_size_ram_64b;
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| 287 | else
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| 288 | event_start_addr <= 0;
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| 289 | end if;
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| 290 | state_mm <= WRITE_FIN;
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| 291 |
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| 292 | elsif (wiz_read_ready_sr(1) = '1') then
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| 293 | wiz_write_ea <= '0';
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| 294 |
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| 295 | if (package_index = (number_of_packages - 1)) then
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| 296 |
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| 297 | -- next address
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| 298 | if ((write_start_addr + fifo_package_size_ram (package_index)) < (RAM_SIZE_16B - event_size_ram)) then
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| 299 | write_start_addr <= write_start_addr + fifo_package_size_ram (package_index);
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| 300 | else
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| 301 | write_start_addr <= 0;
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| 302 | end if;
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| 303 | else
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| 304 | write_start_addr <= write_start_addr + fifo_package_size_ram (package_index);
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| 305 | end if;
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| 306 |
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| 307 | -- increase pack_index
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| 308 | -- the package_index goes from 0..NumOfPack-1
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| 309 |
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| 310 | if ( package_index < (number_of_packages - 1)) then
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| 311 | package_index <= package_index + 1;
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| 312 | else
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| 313 | package_index <= 0;
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| 314 | events_in_ram <= events_in_ram - 1;
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| 315 | end if;
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| 316 |
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| 317 |
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| 318 |
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| 319 |
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| 320 | state_mm <= READ_FIN;
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| 321 |
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| 322 | end if;
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| 323 |
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| 324 | ------------------------- WRITING to MEM was finished ------------------------------------
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| 325 | ------------------------------------------------------------------------------------------
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| 326 | when WRITE_FIN =>
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| 327 | state_sig <= X"B";
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| 328 | ram_start_addr <= conv_std_logic_vector(event_start_addr, RAM_ADDR_WIDTH_64B);
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| 329 | -- 2nd part of hand shake is, that DG pulls low ram_write_ready
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| 330 | if (ram_write_ready_sr(1) = '0') then
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| 331 | state_mm <= UPDATE_OUTPUT;
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| 332 | end if;
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| 333 |
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| 334 |
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| 335 | ------------------------- READING from MEM was finished ----------------------------------
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| 336 | ------------------------------------------------------------------------------------------
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| 337 |
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| 338 | when READ_FIN =>
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| 339 | state_sig <= X"C";
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| 340 | if (wiz_read_ready_sr(1) = '0') then
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| 341 |
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| 342 |
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| 343 | state_mm <= UPDATE_OUTPUT;
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| 344 | end if;
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| 345 |
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| 346 |
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| 347 |
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| 348 |
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| 349 | when UPDATE_OUTPUT =>
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| 350 |
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| 351 |
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| 352 | wiz_ram_start_addr <= conv_std_logic_vector(write_start_addr, RAM_ADDR_WIDTH_16B);
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| 353 | wiz_write_length <= conv_std_logic_vector(fifo_write_length (package_index), 17);
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| 354 | wiz_number_of_channels <= conv_std_logic_vector(fifo_channels_array (package_index), 4);
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| 355 |
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| 356 | if (package_index = 0) then
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| 357 | -- first package -> write header
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| 358 | wiz_write_header <= '1';
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| 359 | else
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| 360 | wiz_write_header <= '0';
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| 361 | end if;
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| 362 |
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| 363 | if (package_index = (number_of_packages - 1)) then
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| 364 | -- last package -> write end-flag
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| 365 | wiz_write_end <= '1';
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| 366 | else
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| 367 | wiz_write_end <= '0';
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| 368 | end if;
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| 369 |
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| 370 | state_mm <= UPDATE_OUTPUT_2;
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| 371 |
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| 372 |
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| 373 | when UPDATE_OUTPUT_2 =>
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| 374 | state_sig <= X"D";
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| 375 | state_mm <= MM_MAIN;
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| 376 |
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| 377 | if (events_in_ram > 0) then
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| 378 | wiz_write_ea <= '1';
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| 379 | else
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| 380 | wiz_write_ea <= '0';
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| 381 | end if;
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| 382 |
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| 383 | if (events_in_ram < max_events_ram) then
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| 384 | ram_write_ea <= '1';
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| 385 | else
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| 386 | ram_write_ea <= '0';
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| 387 | end if;
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| 388 |
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| 389 |
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| 390 | when others =>
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| 391 | state_sig <= X"F";
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| 392 | state_mm <= MM_CONFIG;
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| 393 |
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| 394 | end case; -- state_mm
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| 395 | end if;
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| 396 | end process mm;
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|---|
| 397 |
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|---|
| 398 |
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|---|
| 399 |
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| 400 | END ARCHITECTURE beha;
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|---|
| 401 |
|
|---|
