source: firmware/FAD/FACT_FAD_lib/hdl/mod7_beha.vhd@ 13414

Last change on this file since 13414 was 11755, checked in by neise, 13 years ago
reinit of this svn repos .... it was all too messy deleted the old folders and restarted with FACT_FAD_lib only. (well and the testbenches)
File size: 3.9 KB
Line 
1--
2-- VHDL Architecture FACT_FAD_lib.mod7.beha
3--
4-- Created:
5-- by - dneise.UNKNOWN (E5B-LABOR6)
6-- at - 09:55:28 16.02.2011
7--
8-- using Mentor Graphics HDL Designer(TM) 2009.2 (Build 10)
9--
10LIBRARY ieee;
11USE ieee.std_logic_1164.all;
12--USE ieee.std_logic_arith.all;
13USE ieee.std_logic_unsigned.all;
14
15ENTITY mod7 IS
16 PORT(
17 clk : IN std_logic;
18
19 number : in std_logic_vector(31 downto 0);
20 start : in std_logic;
21
22 remainder : out std_logic_vector(2 downto 0) := (others => '0');
23 started : out std_logic := '0';
24 valid : out std_logic :='0'
25 );
26END ENTITY mod7;
27
28--
29ARCHITECTURE beha OF mod7 IS
30 signal local_number : std_logic_vector (32 downto 0) := (OTHERS => '0'); --33bit number, easy to divide into 3bit-words
31
32 type state_type is (
33 IDLE_STATE,
34 SUBMOD1_STATE,
35 SUM1_STATE,
36 SUBMOD2_STATE,
37 SUM2_STATE,
38 SUBMOD3_STATE,
39 SUM3_STATE,
40 RESULT_STATE);
41
42 signal state : state_type := IDLE_STATE;
43
44 signal sum1 : std_logic_vector (8 downto 0) := (OTHERS => '0'); -- eigentlich reichen 7bit, aber 9 lassen sich leichter teilen
45 signal sum2 : std_logic_vector (5 downto 0) := (OTHERS => '0'); -- eigentlich reichen 4 bit, aber 6 lassen sich leichter teilen
46 signal sum3 : std_logic_vector (2 downto 0) := (OTHERS => '0');
47 signal result : std_logic_vector (2 downto 0) := (OTHERS => '0');
48
49 type sm1_type is array (0 to 10) of std_logic_vector (8 downto 0); -- eigentlich sind es 3 bit werte, aber wenn ich summiere brauche ich die breite (fast)
50 type sm2_type is array (0 to 2) of std_logic_vector (5 downto 0); -- eigentlich sind es 3 bit werte, aber wenn ich summiere brauche ich die breite (fast)
51 type sm3_type is array (0 to 1) of std_logic_vector (2 downto 0);
52
53
54 signal submod1 : sm1_type := (others => "000000000");
55 signal submod2 : sm2_type := (others => "000000");
56 signal submod3 : sm3_type := (others => "000");
57
58
59BEGIN
60 remainder <= result;
61
62 process (clk)
63 begin
64
65
66 if rising_edge(clk) then
67
68 case state is
69
70 when IDLE_STATE =>
71 started <= '0';
72 if (start = '1') then
73 started <= '1';
74 valid <= '0';
75 local_number <= '0' & number;
76 state <= SUBMOD1_STATE;
77 else
78 state <= IDLE_STATE;
79 end if;
80
81 when SUBMOD1_STATE =>
82 for i in 0 to 10 loop
83 if (local_number( 3*i+2 downto 3*i ) = "111" ) then
84 submod1(i) <= "000000000";
85 else
86 submod1(i) <= "000000" & local_number( 3*i+2 downto 3*i );
87 end if;
88 end loop;
89 state <= SUM1_STATE;
90
91 when SUM1_STATE =>
92 sum1 <= submod1(0) +
93 submod1(1) +
94 submod1(2) +
95 submod1(3) +
96 submod1(4) +
97 submod1(5) +
98 submod1(6) +
99 submod1(7) +
100 submod1(8) +
101 submod1(9) +
102 submod1(10);
103
104 state <= SUBMOD2_STATE;
105
106 when SUBMOD2_STATE =>
107 for i in 0 to 2 loop
108 if (sum1( 3*i+2 downto 3*i ) = "111" ) then
109 submod2(i) <= "000000";
110 else
111 submod2(i) <= "000" & sum1( 3*i+2 downto 3*i );
112 end if;
113 end loop;
114 state <= SUM2_STATE;
115
116 when SUM2_STATE =>
117 sum2 <= submod2(0) + submod2(1) + submod2(2);
118 state <= SUBMOD3_STATE;
119
120 when SUBMOD3_STATE =>
121 for i in 0 to 1 loop
122 if (sum2( 3*i+2 downto 3*i ) = "111" ) then
123 submod3(i) <= "000";
124 else
125 submod3(i) <= sum2( 3*i+2 downto 3*i );
126 end if;
127 end loop;
128 state <= SUM3_STATE;
129
130 when SUM3_STATE =>
131 sum3 <= submod3(0) + submod3(1);
132 state <= RESULT_STATE;
133
134 when RESULT_STATE =>
135 started <= '0';
136 valid <= '1';
137 if (sum3( 2 downto 0 ) = "111" ) then
138 result <= "000";
139 else
140 result <= sum3( 2 downto 0 );
141 end if;
142 state <= IDLE_STATE;
143
144 when others =>
145 null;
146 end case;
147
148 end if;
149 end process;
150
151END ARCHITECTURE beha;
152
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