source: firmware/FAD/FACT_FAD_lib/hdl/spi_distributor_beha.vhd@ 17713

Last change on this file since 17713 was 11755, checked in by neise, 14 years ago
reinit of this svn repos .... it was all too messy deleted the old folders and restarted with FACT_FAD_lib only. (well and the testbenches)
File size: 6.4 KB
Line 
1--
2-- VHDL Architecture FACT_FAD_lib.spi_distributor.beha
3--
4-- Created:
5-- by - Benjamin Krumm.UNKNOWN (EEPC8)
6-- at - 09:24:21 23.04.2010
7--
8-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12)
9--
10LIBRARY ieee;
11USE ieee.std_logic_1164.all;
12USE ieee.std_logic_arith.all;
13USE ieee.std_logic_unsigned.all;
14LIBRARY FACT_FAD_lib;
15USE FACT_FAD_lib.fad_definitions.all;
16
17ENTITY spi_distributor IS
18
19-- TEMP_MEASUREMENT_BEAT * clk ist the measurement period of the
20-- Temperature measurement
21-- e.g. 5*10**6 means every second
22
23 GENERIC(
24 TEMP_MEASUREMENT_BEAT : integer := 5*10**6
25 );
26
27 PORT(
28 clk : IN std_logic;
29
30 -- interface nach aussen
31 config_start : IN std_logic;
32 config_ready : OUT std_logic := '1';
33
34 dac_array : IN dac_array_type;
35 current_dac_array : OUT dac_array_type := ( others => 0);
36 sensor_array : OUT sensor_array_type;
37 sensor_valid : OUT std_logic := '0';
38
39
40 sensor_read_start : OUT std_logic := '0';
41 sensor_read_valid : IN std_logic;
42 dac_config_start : OUT std_logic := '0';
43 dac_config_ready : IN std_logic;
44 spi_channel_ready : IN std_logic;
45
46 sclk_enable_override : OUT std_logic := '0';
47 dac_id : OUT std_logic_vector(2 downto 0) := (others => '0');
48 sensor_id : OUT std_logic_vector(1 downto 0) := (others => '0');
49 data : INOUT std_logic_vector(15 downto 0) := (others => 'Z');
50 measured_temp_data : IN std_logic_vector(15 downto 0)
51 );
52END ENTITY spi_distributor;
53
54ARCHITECTURE beha OF spi_distributor IS
55
56 type TYPE_SPI_DISTRIBUTION_STATE is (INIT, IDLE,
57 PRE_READ_SENSOR,
58 SENSOR_READ_START_ACK,
59 READ_SENSOR,
60 PRE_CONFIG_DAC,
61 DAC_CONFIG_START_ACK,
62 CONFIG_DAC);
63
64 signal spi_distr_state : TYPE_SPI_DISTRIBUTION_STATE := INIT;
65 signal int_sensor_read_start : std_logic := '0';
66 signal int_sensor_valid : std_logic := '0';
67 signal int_sensor_array : sensor_array_type;
68 signal sensor_id_cnt : integer range 0 to 4 := 0;
69 signal dac_id_cnt : integer range 0 to 7 := 0;
70
71 signal internal_dac_array : dac_array_type;
72 signal sclk_enable_override_sig : std_logic := '0';
73
74 -- synching signals
75 signal config_start_sr : std_logic_vector (1 downto 0) := "00";
76
77
78 signal sensor_read_valid_sr : std_logic_vector (1 downto 0) := "00";
79 signal dac_config_ready_sr : std_logic_vector (1 downto 0) := "00";
80 signal spi_channel_ready_sr : std_logic_vector (1 downto 0) := "00";
81
82BEGIN
83 sclk_enable_override <= sclk_enable_override_sig;
84
85 spi_distribute_proc: process (clk)
86 begin
87
88
89 if rising_edge(clk) then
90 sensor_read_valid_sr <= sensor_read_valid_sr(0) & sensor_read_valid;
91 dac_config_ready_sr <= dac_config_ready_sr(0) & dac_config_ready;
92 spi_channel_ready_sr <= spi_channel_ready_sr(0) & spi_channel_ready;
93 -- synch in
94 config_start_sr <= config_start_sr(0) & config_start;
95
96 data <= (others => 'Z');
97 case spi_distr_state is
98 when INIT =>
99 data <= (others => 'Z');
100 int_sensor_valid <= '0';
101 spi_distr_state <= PRE_READ_SENSOR;
102
103 when IDLE =>
104 sclk_enable_override_sig <= '0';
105 if (int_sensor_valid = '1') then
106 sensor_array <= int_sensor_array;
107 sensor_valid <= '1';
108 end if;
109 data <= (others => 'Z');
110 -- start DAC configuration
111 if (config_start_sr(1) = '1' AND int_sensor_valid = '1') then
112 internal_dac_array <= dac_array;
113 spi_distr_state <= PRE_CONFIG_DAC;
114 -- start temperature sensor reading
115 elsif (dac_config_ready <= '1' AND int_sensor_read_start = '1' ) then
116 spi_distr_state <= PRE_READ_SENSOR;
117 end if;
118
119 when PRE_READ_SENSOR =>
120
121 int_sensor_valid <= '0';
122 sensor_read_start <= '1';
123 sensor_id <= conv_std_logic_vector(sensor_id_cnt, sensor_id'length);
124 spi_distr_state <= SENSOR_READ_START_ACK;
125
126 when SENSOR_READ_START_ACK =>
127 if (spi_channel_ready_sr(1) = '0') then
128 sensor_read_start <= '0';
129 spi_distr_state <= READ_SENSOR;
130 end if;
131
132 when PRE_CONFIG_DAC =>
133 config_ready <= '0';
134 sclk_enable_override_sig <= '1';
135 dac_config_start <= '1';
136 dac_id <= conv_std_logic_vector(dac_id_cnt, dac_id'length);
137 data <= conv_std_logic_vector(internal_dac_array(dac_id_cnt),data'length);
138 spi_distr_state <= DAC_CONFIG_START_ACK;
139
140
141 when DAC_CONFIG_START_ACK =>
142 dac_id <= conv_std_logic_vector(dac_id_cnt, dac_id'length);
143 data <= conv_std_logic_vector(internal_dac_array(dac_id_cnt),data'length);
144
145 if (spi_channel_ready_sr(1) = '0') then
146 dac_config_start <= '0';
147 spi_distr_state <= CONFIG_DAC;
148 end if;
149
150 -- sensor reading
151 when READ_SENSOR =>
152
153 if (sensor_read_valid_sr(1) = '1') then
154 int_sensor_array(sensor_id_cnt) <= conv_integer(measured_temp_data);
155 --sensor_read_start <= '0';
156 if (sensor_id_cnt < 3) then
157 sensor_id_cnt <= sensor_id_cnt + 1;
158 --sensor_read_start <= '1';
159 spi_distr_state <= PRE_READ_SENSOR;
160 else
161 sensor_id_cnt <= 0;
162 sensor_valid <= '0';
163 int_sensor_valid <= '1';
164 spi_distr_state <= IDLE;
165 end if;
166 end if;
167
168
169
170
171 -- DAC configuration
172 when CONFIG_DAC =>
173 --dac_config_start <= '1';
174 --dac_id <= conv_std_logic_vector(dac_id_cnt, dac_id'length);
175 --data <= conv_std_logic_vector(internal_dac_array(dac_id_cnt),data'length);
176 --if (dac_config_ready = '1') then
177 if (spi_channel_ready_sr(1) = '1') then
178 --dac_config_start <= '0';
179 if (dac_id_cnt < 7) then
180 dac_id_cnt <= dac_id_cnt + 1;
181 --dac_config_start <= '1';
182 spi_distr_state <= PRE_CONFIG_DAC;
183 else
184 dac_id_cnt <= 0;
185 config_ready <= '1';
186 current_dac_array <= internal_dac_array;
187 spi_distr_state <= IDLE;
188 end if;
189 end if;
190 end case;
191 end if;
192
193 end process spi_distribute_proc;
194
195 sensor_tmr_proc: process (clk)
196 variable Z: integer range 0 to (TEMP_MEASUREMENT_BEAT - 1);
197 begin
198 if rising_edge(clk) then
199 int_sensor_read_start <= '0';
200 if (Z < TEMP_MEASUREMENT_BEAT - 1) then
201 Z := Z + 1;
202 else
203 Z := 0;
204 end if;
205 if (Z = 0) then
206 int_sensor_read_start <= '1';
207 end if;
208 end if;
209 end process sensor_tmr_proc;
210
211
212END ARCHITECTURE beha;
213
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