source: firmware/FAD/FACT_FAD_lib/hdl/spi_interface_struct.vhd@ 20115

-- VHDL Entity FACT_FAD_lib.spi_interface.symbol
--
-- Created:
--          by - daqct3.UNKNOWN (IHP110)
--          at - 16:56:36 09.06.2011
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
LIBRARY FACT_FAD_lib;
USE FACT_FAD_lib.fad_definitions.all;

ENTITY spi_interface IS
   PORT( 
      clk_50MHz         : IN     std_logic;
      config_start      : IN     std_logic;
      dac_array         : IN     dac_array_type;
      sclk_enable_i     : IN     std_logic;
      config_ready      : OUT    std_logic;
      current_dac_array : OUT    dac_array_type  := ( others => 0);
      dac_cs            : OUT    std_logic;
      mosi              : OUT    std_logic       := '0';
      sclk              : OUT    std_logic;
      sensor_array      : OUT    sensor_array_type;
      sensor_cs         : OUT    std_logic_vector (3 DOWNTO 0);
      sensor_ready      : OUT    std_logic;
      miso              : INOUT  std_logic
   );

-- Declarations

END spi_interface ;

--
-- VHDL Architecture FACT_FAD_lib.spi_interface.struct
--
-- Created:
--          by - daqct3.UNKNOWN (IHP110)
--          at - 16:56:36 09.06.2011
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
LIBRARY FACT_FAD_lib;
USE FACT_FAD_lib.fad_definitions.all;
USE IEEE.NUMERIC_STD.ALL;

LIBRARY FACT_FAD_lib;

ARCHITECTURE struct OF spi_interface IS

   -- Architecture declarations

   -- Internal signal declarations
   SIGNAL T_sensor_start       : std_logic;
   SIGNAL clk_2Mhz             : std_logic                     := '0';
   SIGNAL dac_config_ready     : std_logic;
   SIGNAL dac_config_start     : std_logic;
   SIGNAL dac_id               : std_logic_vector(2 DOWNTO 0);
   SIGNAL data                 : std_logic_vector(15 DOWNTO 0);
   SIGNAL measured_temp_data   : std_logic_vector(15 DOWNTO 0) := (others => '0');
   SIGNAL sclk_enable_override : std_logic                     := '0';
   SIGNAL sclk_enable_sig      : std_logic                     := '0';
   SIGNAL sensor_id            : std_logic_vector(1 DOWNTO 0);
   SIGNAL sensor_start         : std_logic;
   SIGNAL sensor_valid         : std_logic;
   SIGNAL spi_channel_ready    : std_logic                     := '1';

   -- Implicit buffer signal declarations
   SIGNAL sclk_internal : std_logic;


   -- Component Declarations
   COMPONENT clk_divider
   GENERIC (
      DIVIDER : integer := 25
   );
   PORT (
      clk  : IN     std_logic;
      sclk : OUT    std_logic  := '0'
   );
   END COMPONENT;
   COMPONENT spi_controller
   PORT (
      clk                : IN     std_logic;
      dac_id             : IN     std_logic_vector (2 DOWNTO 0);
      dac_start          : IN     std_logic;
      sensor_id          : IN     std_logic_vector (1 DOWNTO 0);
      sensor_start       : IN     std_logic;
      dac_cs             : OUT    std_logic                      := '1';
      dac_ready          : OUT    std_logic                      := '0';
      measured_temp_data : OUT    std_logic_vector (15 DOWNTO 0) := (others => '0');
      mosi               : OUT    std_logic                      := '0';
      sensor_cs          : OUT    std_logic_vector (3 DOWNTO 0)  := (others => '1');
      sensor_valid       : OUT    std_logic                      := '0';
      spi_channel_ready  : OUT    std_logic                      := '1';
      data               : INOUT  std_logic_vector (15 DOWNTO 0) := (others => 'Z');
      miso               : INOUT  std_logic                      := 'Z'
   );
   END COMPONENT;
   COMPONENT spi_distributor
   GENERIC (
      TEMP_MEASUREMENT_BEAT : integer := 5*10**6
   );
   PORT (
      clk                  : IN     std_logic;
      config_start         : IN     std_logic;
      dac_array            : IN     dac_array_type;
      dac_config_ready     : IN     std_logic;
      measured_temp_data   : IN     std_logic_vector (15 DOWNTO 0);
      sensor_read_valid    : IN     std_logic;
      spi_channel_ready    : IN     std_logic;
      config_ready         : OUT    std_logic                      := '1';
      current_dac_array    : OUT    dac_array_type                 := ( others => 0);
      dac_config_start     : OUT    std_logic                      := '0';
      dac_id               : OUT    std_logic_vector (2 DOWNTO 0)  := (others => '0');
      sclk_enable_override : OUT    std_logic                      := '0';
      sensor_array         : OUT    sensor_array_type;
      sensor_id            : OUT    std_logic_vector (1 DOWNTO 0)  := (others => '0');
      sensor_read_start    : OUT    std_logic                      := '0';
      sensor_valid         : OUT    std_logic                      := '0';
      data                 : INOUT  std_logic_vector (15 DOWNTO 0) := (others => 'Z')
   );
   END COMPONENT;

   -- Optional embedded configurations
   -- pragma synthesis_off
   FOR ALL : clk_divider USE ENTITY FACT_FAD_lib.clk_divider;
   FOR ALL : spi_controller USE ENTITY FACT_FAD_lib.spi_controller;
   FOR ALL : spi_distributor USE ENTITY FACT_FAD_lib.spi_distributor;
   -- pragma synthesis_on


BEGIN

   -- ModuleWare code(v1.9) for instance 'I0' of 'and'
   sclk_internal <= clk_2Mhz AND sclk_enable_sig;

   -- ModuleWare code(v1.9) for instance 'I2' of 'or'
   sclk_enable_sig <= sclk_enable_i OR sclk_enable_override;

   -- Instance port mappings.
   I1 : clk_divider
      GENERIC MAP (
         DIVIDER => 25
      )
      PORT MAP (
         clk  => clk_50MHz,
         sclk => clk_2Mhz
      );
   Measure_Temperature_Timer : clk_divider
      GENERIC MAP (
         DIVIDER => 25
      )
      PORT MAP (
         clk  => sclk_internal,
         sclk => T_sensor_start
      );
   I_spi_controller : spi_controller
      PORT MAP (
         clk                => sclk_internal,
         miso               => miso,
         mosi               => mosi,
         dac_cs             => dac_cs,
         sensor_cs          => sensor_cs,
         dac_id             => dac_id,
         sensor_id          => sensor_id,
         data               => data,
         measured_temp_data => measured_temp_data,
         dac_start          => dac_config_start,
         dac_ready          => dac_config_ready,
         sensor_start       => sensor_start,
         sensor_valid       => sensor_valid,
         spi_channel_ready  => spi_channel_ready
      );
   I_spi_distributor : spi_distributor
      GENERIC MAP (
         TEMP_MEASUREMENT_BEAT => 5*10**6
      )
      PORT MAP (
         clk                  => sclk_internal,
         config_start         => config_start,
         config_ready         => config_ready,
         dac_array            => dac_array,
         current_dac_array    => current_dac_array,
         sensor_array         => sensor_array,
         sensor_valid         => sensor_ready,
         sensor_read_start    => sensor_start,
         sensor_read_valid    => sensor_valid,
         dac_config_start     => dac_config_start,
         dac_config_ready     => dac_config_ready,
         spi_channel_ready    => spi_channel_ready,
         sclk_enable_override => sclk_enable_override,
         dac_id               => dac_id,
         sensor_id            => sensor_id,
         data                 => data,
         measured_temp_data   => measured_temp_data
      );

   -- Implicit buffered output assignments
   sclk <= sclk_internal;

END struct;