source: firmware/FAD/FACT_FAD_lib/hdl/timer_beha.vhd@ 13414

Last change on this file since 13414 was 11755, checked in by neise, 13 years ago
reinit of this svn repos .... it was all too messy deleted the old folders and restarted with FACT_FAD_lib only. (well and the testbenches)
File size: 2.8 KB
Line 
1--
2-- VHDL Architecture FACT_FAD_lib.timer.beha
3--
4-- Created:
5-- by - dneise.UNKNOWN (E5B-LABOR6)
6-- at - 13:44:41 22.02.2011
7--
8-- using Mentor Graphics HDL Designer(TM) 2009.2 (Build 10)
9
10LIBRARY ieee;
11USE ieee.std_logic_1164.all;
12USE ieee.std_logic_arith.all;
13USE ieee.std_logic_unsigned.all;
14
15ENTITY timer IS
16 generic(
17 TIMER_WIDTH : integer := 32;
18 PRESCALER : integer := 5000
19 );
20 port (
21 clk : in std_logic; -- assumed to be 25MHz, if not 25MHz adjust PRESCALER
22 time_o : out std_logic_vector ( TIMER_WIDTH-1 downto 0);
23 synch_i : in std_logic ;
24 synched_o : out std_logic := '0';
25 reset_synch_i : in std_logic;
26 enable_i : in std_logic
27 );
28END ENTITY timer;
29
30--
31ARCHITECTURE beha OF timer IS
32 signal prescale_counter : integer range 0 to PRESCALER - 1 := 0;
33
34 --signal time_s : integer range 0 to 2**(TIMER_WIDTH-1);
35 signal time_s : std_logic_vector ( TIMER_WIDTH-1 downto 0);
36
37 signal en_sr : std_logic_vector(1 downto 0) := "00";
38 signal sy_sr : std_logic_vector(1 downto 0) := "00";
39 signal reset_synch_sr : std_logic_vector(1 downto 0) := "00";
40
41 signal timer_proc_enabled : std_logic := '0';
42 signal synched : std_logic := '0';
43
44BEGIN
45 --time_o <= conv_std_logic_vector(time_s, TIMER_WIDTH);
46 time_o <= time_s;
47 synched_o <= synched;
48
49
50 main_proc: process (clk)
51 begin
52 if rising_edge(clk) then
53 en_sr <= en_sr(0) & enable_i;
54 sy_sr <= sy_sr(0) & synch_i;
55 reset_synch_sr <= reset_synch_sr(0) & reset_synch_i;
56
57 if ( reset_synch_sr = "01" ) then
58 synched <= '0';
59 end if;
60
61 if (sy_sr = "01" and synched = '0') then -- rising edge on synchronizstion_input detected AND if not already synched
62 time_s <= conv_std_logic_vector(0,TIMER_WIDTH);
63 prescale_counter <= 1;
64 synched <= '1';
65 end if;
66
67 if (en_sr = "01") then -- rising edge on enable_input detected
68 time_s <= conv_std_logic_vector(0,TIMER_WIDTH);
69 prescale_counter <= 1;
70 timer_proc_enabled <= '1';
71 elsif (en_sr = "10") then -- falling edge on enable_input detected
72 time_s <= conv_std_logic_vector(0,TIMER_WIDTH);
73 prescale_counter <= 0;
74 timer_proc_enabled <= '0';
75 end if;
76
77 -- PRESCALER PART OF PROCESS
78 if (timer_proc_enabled = '1') then
79 if (prescale_counter < PRESCALER - 1) then
80 prescale_counter <= prescale_counter + 1;
81 else
82 prescale_counter <= 0;
83 end if;
84 if (prescale_counter = PRESCALER - 1) then
85 if ( time_s < conv_std_logic_vector(2**TIMER_WIDTH-1 ,TIMER_WIDTH) ) then
86 time_s <= time_s + conv_std_logic_vector(1,TIMER_WIDTH);
87 else
88 time_s <= conv_std_logic_vector(0,TIMER_WIDTH);
89 end if;
90 end if;
91 else -- not timer_proc_enabled
92 time_s <= conv_std_logic_vector(0,TIMER_WIDTH);
93 end if; -- if timer_proc_enabled
94 end if; -- rising_edge(clk)
95 end process main_proc;
96END ARCHITECTURE beha;
97
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